8051 Embedded Microcontroller STK Data Sheet

Transcription

1 8051 Embedded Microcontroller STK60516 Data Sheet Rev. 1.0 March 16, 2010 Taipei Office 10F, No. 1, Alley 30, Lane 358, Rueiguang Road, Neihu District, Taipei, Taiwan R.O.C. 台北市內湖區瑞光路 358 巷 30 弄 1 號 10 樓 TEL: FAX: Hsinchu Office 3F, No. 24-2, Industry E. Road IV, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. 新竹市科學工業園區工業東四路 24-2 號 3 樓 TEL: FAX: Caution! The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this data sheet. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy, or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this data sheet or product. Product names appearing in this data sheet are for identification purpose only, and trademarks and product names or brand names appearing in this document are property of their respective owners. All rights reserved. No part of this data sheet may be reproduced, transmitted, or transcribed without the expressed written permission of the manufacturer and authors of this data sheet. Data Sheet 1 / 122 STK60516

2 Revision History Rev. Date Author Description Rev /01/28 Apollo First release Data Sheet 2 / 122 STK60516

3 Table of Contents 1. Product Overview: Product Features Ordering Information Functional Block Diagram Pin Connection Pin diagram(stk60516a5plg PLCC44) Pin diagram(stk60516a5lqg LQFP48) Pin diagram(stk60516a5qpg QFP44) Pin diagram(stk60516a5tplg PLCC44) Pin diagram(stk60516a5tlqg LQFP48) Pin diagram(stk60516a5tqpg QFP44) Pin Description Functional Description Instruction Set and Addressing Modes CPU Clock and Chip Configuration Register (SFR CHIPCON) Instruction Cycle Program Status Word Memory Organization Program Memory Program ROM Space On-Chip Program Memory Versus External Program Memory ISP Programming for The 64K Flash Memory Main Data RAM and Special Function Register (SFR) The Lower 128 Bytes of The Main Data Ram AUX Memory AUX Memory Space On-Chip AUX Memory DUAL Data Pointer (Data Pointer 0 and Data Pointer 1) and DPTR Select Register (SFR DPS) Stretch Memory Cycles for Accessing External AUX Memory and Clock Control Register Special Function Registers SFR Map Overview (95 SFRs) SFR of Each Functional Block Port 0, Port 1, Port 2, Port 3, and Port General Description Port Data Sheet 3 / 122 STK60516

4 10.3. Port 1, Port 2, and Port Port Timer/Counter 0, Timer/Counter General Description Mode Selection Register, SFR TMOD ( at 89H of SFR space) Timer 0/1 Control Register (SFR TCON at 88 H of the SFR space) Clock Control Register, SFR CKCON, at address 8E hex of the SFR map Operating Modes Mode 0 (13-Bit Timer/Counter) Mode 1 (16-Bit Timer/Counter) Mode 2 (8-Bit Counter with Auto-Reload) Mode 3 (Two 8-Bit Counters from Timer 0) Timer/Counter General Description and operation modes Special Function Registers associated with Timer The T2M Bit of Clock Control Register (SFR CKCON) Timer 2 Control Register (SFR T2CON) Timer 2 Mode Control Register bit Timer/Counter Mode bit Timer/Counter with Capture capability (Capture Mode) bit Timer/Counter with Auto-Reload capability (Auto-Reload Mode) Baud Rate Generator Mode Calculating The Value of RCAP2H and RCAP2L for a Desired Baud Rate More about Timer Timer 2 in Baud Rate Generator Mode Reset Sources of Reset Power-On- Reset (POR) with fast-rising power supply Asynchronous reset by adding a HIGH pulse to the RESET pin Low-power detection and reset Reset by the Watchdog Timer overflow Oscillator Circuit The Oscillator Circuit The values for R, C1, and C Interrupts General Description Interrupt Enable Registers Data Sheet 4 / 122 STK60516

5 15.3. Interrupt Priority Register SFR IP Description of Interrupt Priority Register SFR IP Interrupt Vectors Overall View of The Interrupt System UART0 and UART General Description Summary of operation Modes of UART0 and UART Control/Status Register and operation Mode of UART Control/Status Register (SFR SCON0) of UART Operation mode of UART Multiprocessor communications Control/status Register and operation mode of UART Operation Modes of UART Control/Status Register (SFR SCON1) of UART Multiprocessor communications Power-Saving Modes Idle Mode Stop mode Status of external pins during power-saving modes Summary of Power-saving Modes Watchdog Timer Functional Block Diagram Watchdog Timer Control Register bit Analog-to-Digital Converter (10-bit ADC) ADC functional description ADC resolution and characteristics ADC Timing diagram Programmable Counter Array (PCA) PCA clock select PCA module 0 Timer mode PCA positive edge capture mode PCA negative edge capture mode Both PCA positive edge and negative edge capture mode High speed output mode PCA 8-bit PWM mode PCA 16-bit PWM mode PCA Control Register Data Sheet 5 / 122 STK60516

6 22. Serial Peripheral interface (SPI) Control Registers of SPI SPI connection Master Mode Slave Mode Master with multiple slaves SPI Communication Timing diagram SPI slave mode with SPICPHA= slave mode with SPICPHA= SPI master mode with SPICPHA= SPI master mode with SPICPHA= IAP IAP Programming SFRs associated with IAP Real Time Clock(RTC) Description of Real Time Clock(RTC) SFRs associated with RTC The procedure of setting RTC Control Register Descriptions of RTC MHz RC Oscillator Control Registers of 6MHz RC Oscillator Setting table of 6MHz Oscillator coarse frequency adjustment Fine tuning adjustment Electrical Parameters DC Characteristics Absolute Maximum Ratings Operating Conditions Allowable Package Outline Drawing PLCC Package Outline Drawing QFP44 Package Outline Drawing LQFP48 Package Outline Drawing Data Sheet 6 / 122 STK60516

7 1. Product Overview: The STK60516 is an 8-bit micro-controller. It consists of a 4T 8051 core, a 64K-byte internal program Flash ROM, support hardware ISP function, 2304-byte SRAM, five 8-bit I/O ports, max. 40 I/O pins (for LQFP48), four 16-bit timer/counter, two UART serial ports, 11 interrupt sources, a watchdog timer, and a 6-channel 10 bits A/D converter. 2. Product Features 40 bi-directional I/O pins (max.). 5 channels of PCA. 6 channels of 10-bit ADC (max.).(adc clock frequency is adjustable, and open the ADC ready flag) 64K bytes of program Flash ROM. 2304( ) bytes of SRAM. PSEN enabled only when access external RAM. Built in RC oscillator (6 MHz). Hardware SPI that could work as mater or slave. Watchdog timer featuring programmable interval. Four 16-bit counters/timers. Two full-duplex serial ports. RTC function.(bounding option with ALE and PSEN pin) 11 interrupt sources. Hardware code protection. The features to protect the intellectual property of customers. Hardware In System Programming (ISP) function. [UART Type and I2C type both] Operating frequency up to 32MHz. (with gain control) Enhanced the noise immunity capability for crystal pads. 3.3V to 5.0V power supply. Power consumption under 1mA at idle mode. -40 C ~+85 C working range. EFT >= 4KV. ESD test >= 8KV without system reset. Package designed with PLCC44, QFP44, and LQFP48 Data Sheet 7 / 122 STK60516

8 3. Ordering Information TYPE NUMBER PACKAGE FEATURE STK60516A5PLG PLCC44 General STK60516A5LQG LQFP48 General STK60516A5QPG QFP44 General STK60516A5TPLG PLCC44 RTC STK60516A5TLQG LQFP48 RTC STK60516A5TQPG QFP44 RTC Data Sheet 8 / 122 STK60516

9 4. Functional Block Diagram ALE PSEN EA P3.1/TXD0 P3.0/RXD0 P2.7/TXD1 P2.6/RXD1 ISP Control (Uart or I2C) P3.4/T0 P3.5/T1 P1.0/T2 P1.1/T2EX P3.2/INT0 P3.3/INT CPU Program flash Memory(64K) MainDataMe mory (256 Bytes) AUX Memory (2048 Bytes) Full-duplex Uart x2 Timer 0 Timer 1 Timer 2 Interrupt Control Internal Bus Port0 Port2 Port1 Port3 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P1.0/PCA0 P1.1/PCA1 P1.2/PCA2 P1.3/PCA3 P1.4/PCA4 P1.5/PCA_EI P1.6 P1.7 P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P4.0/ADC0 P4.1/ADC1 P4.2/ADC2 P4.3/ADC3 P4.4/ADC4 P4.5/ADC5 P1.0/PCA0 P1.1/PCA1 P1.2/PCA2 P1.3/PCA3 P1.4/PCA4 P1.5/PCA_EI 6 channal 10 bit ADC 5 channal PCA Port4 Watch Dog Timer Real Time Clock P4.0/ADC0 P4.1/ADC1 P4.2/ADC2 P4.3/ADC3 P4.4/ADC4 P4.5/ADC5 P4.6 P4.7 ALE/XTAL_RTCI PSEN/XTAL_RTCO Data Sheet 9 / 122 STK60516

10 5. Pin Connection 5.1. Pin diagram(stk60516a5plg PLCC44) Data Sheet 10 / 122 STK60516

11 5.2. Pin diagram(stk60516a5lqg LQFP48) Data Sheet 11 / 122 STK60516

12 5.3. Pin diagram(stk60516a5qpg QFP44) Data Sheet 12 / 122 STK60516

13 5.4. Pin diagram(stk60516a5tplg PLCC44) Data Sheet 13 / 122 STK60516

14 5.5. Pin diagram(stk60516a5tlqg LQFP48) Data Sheet 14 / 122 STK60516

15 5.6. Pin diagram(stk60516a5tqpg QFP44) Data Sheet 15 / 122 STK60516

16 6. Pin Description Name I/O Type Description P0.0 I/O General purpose I/O (open drain) P0.1 I/O General purpose I/O (open drain) P0.2 I/O General purpose I/O (open drain) P0.3 I/O General purpose I/O (open drain) P0.4 I/O General purpose I/O (open drain) P0.5 I/O General purpose I/O (open drain) P0.6 I/O General purpose I/O (open drain) P0.7 I/O General purpose I/O (open drain) P1.0/PCA0 I/O General purpose I/O (8051 standard) /PCA0 P1.1/PCA1 I/O General purpose I/O (8051 standard) /PCA1 P1.2/PCA2 I/O General purpose I/O (8051 standard) /PCA2 P1.3/PCA3 I/O General purpose I/O (8051 standard) /PCA3 P1.4/PCA4 I/O General purpose I/O (8051 standard) /PCA4 P1.5/PCA_EI I/O General purpose I/O (8051 standard) /PCA external input clock P1.6 I/O General purpose I/O (8051 standard) P1.7 I/O General purpose I/O (8051 standard) P2.0/MISO I/O General purpose I/O (8051 standard) /SPI MISO P2.1/MOSI I/O General purpose I/O (8051 standard) /SPI MOSI P2.2/SPICLK I/O General purpose I/O (8051 standard) /SPICLK P2.3/SS I/O General purpose I/O (8051 standard) /SS P2.4 I/O General purpose I/O (8051 standard) P2.5 I/O General purpose I/O (8051 standard) P2.6/RXD1 I/O General purpose I/O (8051 standard) /RXD1 P2.7/TXD1 I/O General purpose I/O (8051 standard) /TXD1 P3.0/RXD0 I/O General purpose I/O (8051 standard) /RXD0 P3.1/TXD0 I/O General purpose I/O (8051 standard) /TXD0 P3.2/INT0# I/O General purpose I/O (8051 standard) /INT0# P3.3/INT1# I/O General purpose I/O (8051 standard) /INT0# P3.4/T0 I/O General purpose I/O (8051 standard) /T0 P3.5/T1 I/O General purpose I/O (8051 standard) /T1 P3.6/WR# I/O General purpose I/O (8051 standard) /WR# P3.7/RD# I/O General purpose I/O (8051 standard) /RD# P4.0/AD0 I/O General purpose I/O (8051 standard) /ADC0 Input P4.1/AD1 I/O General purpose I/O (8051 standard) /ADC1 Input P4.2/AD2 I/O General purpose I/O (8051 standard) /ADC2 Input P4.3/AD3 I/O General purpose I/O (8051 standard) /ADC3 Input P4.4/AD4 I/O General purpose I/O (8051 standard) /ADC4 Input P4.5/AD5 I/O General purpose I/O (8051 standard) /ADC5 Input P4.6 I/O General purpose I/O (8051 standard) P4.7 I/O General purpose I/O (8051 standard) V DD - Power Supply V SS - Ground X2 O Oscillator output X1 I Oscillator input RST I Active-high reset ALE/XTAL_RTCO O Address Latch Enable / KHz crystal XO PSEN#/XTAL_RTCI O Program Store Enable / KHz crystal XI EA# I External Access Enable Data Sheet 16 / 122 STK60516

17 7. Functional Description 7.1. Instruction Set and Addressing Modes The STK60516 s instruction set and addressing modes are completely compatible with that of industrial standard 80C51.User codes written in traditional 80C51 instruction set can be ported directly to the STK However, due to difference in CPU instruction clocks and timing, applications in which delay loops are used may need modification in the number of loops CPU Clock and Chip Configuration Register (SFR CHIPCON) There are four clock sources in STK60516 which are XTAL1, 6MHz RC_CLK, LDO_CLK, and RTC_CLK. 6MHz RC_CLK is a built-in RC oscillator. Its initial frequency is 6MHz. LDO_CLK is also a built-in RC oscillator. Its initial frequency is 2.5MHz.RTC_CLK is a real time clock source. Its frequency is 32K.The STK60516 can be configured to run at different clock frequencies by use of bit 2 and bit 1 of the Chip Configuration Register (SFR CHIPCON) and bit 2 and bit 1 of the Clock Select Register (SFR CLKSEL). XTAL 1 RC_CLK LDO_CLK Multiplexers SELCLK Divided by 3 X2 Multiplexers CPUCLK RTC_CLK CLK SEL [1] CLK SEL [0] C P U C L K C P U R A T A CLKSEL[1] CLKSEL[0] SELCLK CPUCLK CPURATE CPUCLK 0 0 SELCLK=XTAL1 0 0 CPUCLK=SELCLK 0 1 SELCLK=RC_CLK 0 1 CPUCLK=SELCLK/3 1 0 SELCLK=LDO_CLK 1 0 CPUCLK=SELCLK/3 1 1 SELCLK=RTC_CLK 1 1 CPUCLK=SELCLKx2 CPU Clock Data Sheet 17 / 122 STK60516

18 The Clock Selection Register (SFR CLKSEL, at SFR map address D7 hex) controls the following selection of CPU clock. Table listed below is description of Clock Selection Register. Chip Configuration Register (SFR CLKSEL), located at D7 hex of the SFR map, Read/Write Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics x x x x x x CLKSEL[1] CLKSEL[0] Reset value x x x x x x 0 0 The Chip Configuration Register (SFR CHIPCON, at SFR map address BF hex) controls the following: Enable or disable the on-chip AUX memory access, (XRAMEN = 1 Enable AUXRAM access for MOVX) Enable or disable of the ALE output, (ALEDIS = 0 Enable ALE output) Selection of CPU clock, and Enable or disable of low-power reset.(lvr = 0 Enable LVR function) Table listed below is description of Chip Configuration Register. Chip Configuration Register (SFR CHIPCON), located at BF hex of the SFR map, Read/Write Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics x x x XRAMEN ALEDIS CPUCLK CLKRATE LVR Reset value x x x Instruction Cycle CPU CLK Instruction cycle n+1 n+2 CPU cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 ALE CPU timing for single-cycle instruction Data Sheet 18 / 122 STK60516

19 7.4. Program Status Word The current state of the CPU is reflected in the Program Status Word (PSW) register, which is located at SFR address D0 (hex). PROGRAM STATUS WORD (SFR PSW), LOCATED AT D0H OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics CY AC F0 RS1 RS0 OV F1 P Reset value MNEMONIC BIT POSITION CY PSW. 7 AC PSW. 6 FUNCTION Carry flag. The Carry flag receives Carry-out from bit 7of ALU, It is set to HIGH, when last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction) ;otherwise, it is cleared to LOW by all arithmetic operations. Auxiliary Carry Flag. Auxiliary Carry Flag receives Carry-out from bit 3 of addition operands. It is set to HIGH. When last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction, the high-order nibble otherwise, it is cleared to LOW by all arithmetic operations. F0 PSW.5 General purpose flag. This bit is uncommitted and may be used ms general purpose status flag. RS1 RS0 PSW.4 PSW.3 Register Bank selects control bits. RS1, RS0 = 00 selects register bank 0, address 00h ~ 07h. RS1, RS0 = 01 selects register bank 1, address 08h ~ 0Fh. RS1, RS0 = 10 selects register bank 2, address 10h ~ 17h. RS1, RS0 = 11 selects register bank 3, address 18h ~1Fh. OV PSW.2 Overflow flag. This bit Is set to HIGH, when last arithmetic operation resulted in a carry (Addition), borrow (subtraction), or overflow (multiply or divide); otherwise, it is cleared to LOW by all arithmetic operation. Fl PSW.1 General purpose flag. This bit is uncommitted and may be used as general purpose status flag. P PSW.0 Parity flag. Set/Clear by hardware each Instruction cycle to Indicate an odd/even number of 1s in the accumulator, i.e., even parity. Data Sheet 19 / 122 STK60516

20 8. Memory Organization The STK60516 has 4 blocks of memory physically implemented on-chip. These are: bytes of flash program memory, 256 bytes of Main Data Memory, 2048 bytes of AUX memory, and 95 bytes of Special Function Register Program Memory Program ROM Space The STK60516 CPU fetches instructions either from the on-chip program memory or the off-chip program memory. For both memories, the address range is from 0000 (hex) to FFFF (hex) On-Chip Program Memory Versus External Program Memory If, during reset, the EA (External Access) pin is held HIGH, the STK60516 always executes out of the on-chip Program Memory. If the EA pin is held LOW during reset, the STK60516 fetches instructions from off-chip Program Memory. The EA input is latched during reset and is ignored after reset. After reset, the CPU starts fetching program ROM code at location 0000H. The off-chip memory is accessed via Port 0 and Port ISP Programming for The 64K Flash Memory The on-chip program memory is implemented using flash memory, with ISP (In-System Programming) capability. Detailed description of ISP programming is given in another document ROM CODE PROTECTION ROM code protection is implemented in the 64K flash memory Main Data RAM and Special Function Register (SFR) The STK60516 has 256 bytes of on-chip Main Data RAM and 95 bytes of SFR. Although the Main Data RAM and the SFRs shares overlapped memory space, they are two physically separate blocks. The upper 128 bytes of the Main Data RAM, from address 80H to FFH can be accessed only by Indirect Addressing. The lower 128 bytes of the Main RAM, from address 00H to 7FH, can be accessed by Direct Addressing or Indirect Addressing. The SFRs occupy the address range from 80H to FFH and are only accessible using Direct Addressing. Data Sheet 20 / 122 STK60516

21 7Fh Direct RAM Indirect addressing only 30h 2Fh 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h Bit- Addressable Registers Bank 3 Bank 2 Bank 1 Bank 0 FF(hex) Upper 128 bytes 80(hex) 7F(hex) Lower 128 bytes 00(hex) Main Data RAM SFR Direct or indirect addressing Direct addressing only PSW SFR Bit 4 Bit 3 Selected bank Main Data Memory and SFRs The Lower 128 Bytes of The Main Data Ram The lower 128 bytes are organized as shown in Figure of Main Data Memory and SFRs. The lower 32 bytes form 4 banks of eight registers (R0 - R7). Two bits on the Program Status Word (PSW) select which bank is active (in use). The next 16 bytes, from 20 (hex) to 2F (hex), form a block of bit-addressable memory space, at bit address 00(hex) ~ 07(hex) AUX Memory AUX Memory Space The STK60516 has 64K bytes of auxiliary memory (AUX RAM) space, which can be accessed by executing MOVX instruction. The AUX RAM space is physically divided into two blocks: the on-chip block and the off-chip block. The on-chip block has a capacity of 2048 bytes and starts from address 0 to address 2047(decimal). The off-chip block starts from address 2048(decimal) to address The instruction, where i=0 or 1, can access only the lowest 256-bytes of the on-chip AUX RAM. The MOVX@DTPR instruction can access the whole range of the AUX RAM space. Data Sheet 21 / 122 STK60516

22 AUX RAM space from address 2048 to address is allocated as external AUX RAM and can only be accessed by the instruction. The external AUX RAM is externally expandable, with Port 0 used as low-byte address/data, Port 2 used as high-byte address, P3.6 used as Write strobe, and P3.7 used as Read strobe Total AUX Memory Space Read/write to this block can be disbabled by programming bit 4 of SFR CHIPCON to LOW On-chip AUX memory 2048 Externally expandable The AUX Memory Space On-Chip AUX Memory The on-chip AUX RAM from address 0 to address 2047 can be accessed by the CPU as normal data memory, by performing a MOVX instruction. Read/Write access to this memory can be disabled by setting bit 4 of the SFR CHIPCON to LOW. Please refer to Table of CHIPCON register for detailed description of the SFR CHIPCON. When executing MOVX instruction from internal program memory, an access (read or write) to the internal AUX RAM will not affect the status of Port 0, Port 2, P3.6 (write) and P3.7. (read) DUAL Data Pointer (Data Pointer 0 and Data Pointer 1) and DPTR Select Register (SFR DPS) The STK60516 has two data pointers, Data Pointer 0 and Data Pointer 1. Data Pointer 0 is the traditional 8051 data pointer for MOVX instructions. Data Pointer 1 is an extra data pointer for fast moving a block of data. Before executing a MOVX instruction, an active data pointer must be selected by programming the Data Pointer Select Register (SFR DPS). Please refer to Table of DPS register for detailed description of SFR DPS. Address R/W SYMBOLS DESCRIPTION Reset Value (Hex) 82 R/W DPL0 Data Pointer 0 Low (traditional 80C51 data pointer) R/W DPH0 Data Pointer 0 High (traditional 80C51 data pointer) Data Sheet 22 / 122 STK60516

23 84 R/W DPL1 Data Pointer 1 Low (extra data pointer), specific to the STK R/W DPH1 Data Pointer 1 High (extra data pointer), specific to the STK DPTR Select Register (DPS), specific to the STK The DPS register has only one bit. Only its bit 0, called SEL bit, is implemented on-chip. When SEL=0, instructions that 86 R/W DPS use the DPTR will use SFR DPL0 and SFR DPH0. When SEL=1, instructions that use the DPTR will use SFR DPL1 and SFR DPH1. Bits 7~1 of SFR DPS can not be written to, and, when read, always return a 0 for any of these 7 bits All DPTR-related instructions use the currently selected data pointer. To switch the active pointer, toggle the SEL bit, by use of the instruction INC DPS. The 6 instructions that use the DPTR are given in the following table. An active DPTR must be selected before executing these instructions. INSTRUCITON INC DPTR MOV DPTR, #data16 MOVC A+DPTR MOVX A A+DPTR DESCRIPTION Increment the data pointer by1. Load the DPTR with a 16-bit constant. Move code byte relative to DPTR to Accumulator (ACC). Move AUX Memory byte (16-bit address) to Accumulator (ACC) Move ACC to AUX memory byte. Jump indirect relative to DPTR Stretch Memory Cycles for Accessing External AUX Memory and Clock Control Register By default (after a reset), the MOVX instruction is executed in 3 instruction cycles. However, it is possible to shorten or lengthen, dynamically by user program, the instruction cycles needed to execute a MOVX instruction, by use of the M2, M1, and M0 bits of the Clock Control Register (SFR CKCON). The added extra cycles affects the width of the read/write strobe and all related timing. Using a higher stretch value results in a wider read/write strobe, which then allows the memory more time to respond. Table listed below gives description of the Clock Control Register and stretched cycles for various values of M2, M1, and M0. Clock Control Register (SFR CKCON), located at 8E(hex) of the SFR map Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics Reserved T2M T1M T0M MD2 MD1 MD0 Reset value Description of the CKCON Register MNEMONIC BIT FUNCTION POSITION T2M CKCON.5 Select Timer 2 clock frequency. When T2M=0, Timer 2 uses (CPU CLK / 12) as clock frequency. When T2M=1, Timer 2 uses (CPU CLK / 4) as clock frequency. T1M CKCON.4 Select Timer 1 clock frequency. When T1M=0, Timer 1 uses (CPU CLK / 12) as clock frequency. Data Sheet 23 / 122 STK60516

24 When T1M=1, Timer 1 uses (CPU CLK / 4) as clock frequency. T0M CKCON.3 Select Timer 0 clock frequency. When T0M=0, Timer 0 uses (CPU CLK / 12) as clock frequency. When T0M=1, Timer 0 uses (CPU CLK / 4) as clock frequency. MD2 CKCON.2 Control the number of cycles to be used for accessing external AUX memory, MD1 CKCON.1 using the MOVX instruction. MD0 CKCON.0 Data Memory Stretch Values for the MOVX instruction MD2 MD1 MD0 Instruction cycles for executing MOVX Read/Write Strobe Width (CPU CLK) Strobe Width MHz ns (default) 4 160ns ns ns ns ns ns ns Assume that XTAL1=CPU CLK. Data Sheet 24 / 122 STK60516

25 9. Special Function Registers The STK60516 has 95 Special Function Registers (SFR) SFR Map Overview (95 SFRs) The SFR Map Address R/W SYMBOLS DESCRIPTION Reset Value (Hex) 80 R/W P0 Port 0 output latch (bit-addressable) R/W SP Stack Pointer R/W DPL0 Data Pointer 0 Low (traditional 80C51 data pointer) R/W DPH0 Data Pointer 0 High (traditional 80C51 data pointer) R/W DPL1 Data Pointer 1 Low (extra data pointer), specific to the STK R/W DPH1 Data Pointer 1 High (extra data pointer), specific to the STK R/W DPS DPTR Select Register (DPS), specific to the STK R/W PCON Power Control Register R/W TCON Timer0/1 Control Register (bit-addressable) R/W TMOD Timer0/1 Mode Register A R/W TL0 Timer0, Low byte B R/W TL1 Timer1, Low byte C R/W TH0 Timer0, High byte D R/W TH1 Timer1, High byte E R/W CKCON Clock Control register, specific to the STK The register is for controlling the frequency of the clock added to Timer 0, Timer 1, and Timer 2, and memory stretch cycle for the MOVX instruction F not used. 90 R/W P1 Port 1 output latch (bit-addressable) , 92, 93, 94, 95, 96, 97, not used. 98 RW SCON0 Serial Port Control/Status Register 0(bit-addressable) RW SBUF0 Serial Port Buffer Register A, 9B, 9C, 9D, 9E, 9F not used A0 RW P2 Port 2 output latch (bit-addressable ) A1 RW PCA_EN_REG PCA Enable Register A2 RW PCA_FG_REG PCA Flag Register A3 RW PCA_CNTH PCA Counter High Byte Register A4 RW PCA_CNTL PCA Counter Low Byte Register A5 RW PCA0_CON PCA Channel 0 Control Register A6 RW PCA0_DH PCA Channel 0 Data High Byte Register A7 RW PCA0_DL PCA Channel 0 Data Low Byte Register A8 RW IE Interrupt Enable Register (bit-addressable) A9 RW PCA1_CON PCA Channel 1 Control Register AA RW PCA1_DH PCA Channel 1 Data High Byte Register AB RW PCA1_DL PCA Channel 1 Data Low Byte Register AC RW PCA2_CON PCA Channel 2 Control Register AD RW PCA2_DH PCA Channel 2 Data High Byte Register AE RW PCA2_DL PCA Channel 2 Data Low Byte Register AF RW PCA3_CON PCA Channel 3 Control Register B0 RW P3 Port 3 output latch (bit-addressable) B1 RW PCA3_DH PCA Channel 3 Data High Byte Register B2 RW PCA3_DL PCA Channel 3 Data Low Byte Register Data Sheet 25 / 122 STK60516

26 B3 RW PCA4_CON PCA Channel 4 Control Register B4 RW PCA4_DH PCA Channel 4 Data High Byte Register B5 RW PCA4_DL PCA Channel 4 Data Low Byte Register B6 not used. B7 RW ADCCLKSEL ADC Clock Select Register B8 RW IP Interrupt Priority Register (bit-addressable) B9, BA, BB, BC, BD, BE, not used. BE RW P4 Port 4 output latch BF RW CHIPCON Chip Configuration Register xxx C0 RW SCON1 Serial Port Control/Status Register 1(bit-addressable) C1 RW SBUF1 Serial Port Buffer Register C2, C3, C4, C5 not used. C6 RW OSC_CON Oscillator Control Register C7 not used. C8 RW T2CON Timer 2 Control Register (bit-addressable) C9 RW T2MOD Timer 2 Mode Control Register 0000 xx0x CA RW RCAP2L Timer 2 Reload Capture Register, Low byte CB RW RCAP2H Timer 2 Reload Capture Register, High byte CC RW TL2 Timer 2, Low byte CD RW TH2 Timer 2, High byte CE RW RC_CON0 RC Control Register CF RW RC_CON1 RC Control Register D0 RW PSW Program Status Word Register (bit-addressable) D1~ D8 not used. D9 RW P4_OPT Selecting Port 4 pin function, as normal port pin or ADC xx input DA RW ADCSE Select a channel as ADC input and enable ADC DB RW ADCVALH Buffer for storing the upper 8 bits ( Bits 9 ~ 2)of the 10-bit ADC DC RW ADCVALL Buffer for storing the lower 2 bits ( Bits 1 ~ 0) of the 10-bit xxxx xx00 ADC DD RW P0_OPT Port 0 pin option for normal I/O or external memory address/data DE RW P2_OPT Port 2 pin option for normal I/O or external memory address DF not used E0 RW ACC Accumulator (bit-addressable) E1 RW WDT Watchdog Timer Control 00xx x000 E2 RW ISPSLV ISP Control Slave address E3 RW ISPEN ISP Enable Register (write 93hex to enable the ISP mode) E4 RW IAPEN IAP Enable Register 0000 xxxx E5 RW IAP_ADRL Low-byte address of the flash memory location for IAP E6 RW IAP_ADRH High-byte address of the flash memory location for IAP E7 RW IAPDATA IAP Data Register F8 not used E9 RW SPICTL SPI Control Register EA RW SPITXDATA SPI Data Register EB RW SPIMASTER SPI Master or Slave Select Register xxxx xxx1 EC,ED,EE,EF not used F0 RW B B Register (bit-addressable) F1 RW RTCSEC The Present Second Register TBD F2 RW RTCMIN The Present Minute Register TBD F3 RW RTCHOUR The Present Hour Register TBD Data Sheet 26 / 122 STK60516

27 F4 RW RTCDAYH The Present Day High Byte Register TBD F5 RW RTCDAYL The Present Day Low Byte Register TBD F6 RW RTCCTL RTC Control Register 000x xxxx F7, F8 not used F9 RW PRSEC Program RTC Second Register FA RW PRMIN Program RTC Minute Register FB RW PRHOUR Program RTC Hour Register FC RW PRDAYH Program RTC Day High Byte Register FD RW PRDAYL Program RTC Day Low Byte Register FE R ALMIN Alarm Minute Setting Register FF R ALHOUR Alarm Hour Setting Register SFR of Each Functional Block BLOCK SYMBOL NAME Address CPU RESET VALUE (Hex format) ACC Accumulator. E B B register F SP Stack Pointer DPL0 Data Pointer 0, Low byte DPH0 Data Pointer 0, High byte DPL1 Data Pointer 1, Low byte DPH1 Data Pointer 1, High byte DPS Selection for active Data Pointer PCON Power Control Register PSW Program Status Word D CHIPCON Chip Configuration Register BF xxx CKCON Clock Control Register 8E CLK_SEL Clock Select Register D Interrupt IE Interrupt Enable Register A System IP Interrupt Priority Register B8 x P0 Port 0 latch(bit-addressable ) P0_OPT Port 0 pin option for I/O or external DD memory access P1 Port 1 latch P2 Port 2(bit-addressable ) A Ports P2_OPT Port 2 pin option for I/O or external DE memory access P3 Port 3 latch(bit-addressable ) B P4 Port 4 latch BE P4_OPT Port 4 pin option for I/O or ADC inputs D9 xx SBUF0 Serial Port Buffer Register UART SCON0 Serial Port Control/Status Register SBUF1 Serial Port Buffer Register 1 C Timer 0 / Time 1 SCON1 Serial Port Control/Status Register 1 C TCON Timer 0/1 Control Register TMOD Timer 0/1 Mode Register TL0 Timer 0, Low byte 8A TL1 Timer 1, Low byte 8B TH0 Timer 0, High byte 8C TH1 Timer 1, High byte 8D CKCON Clock Control Register 8E CLK_SEL Clock Select Register D T2CON Timer 2 Control Register C Data Sheet 27 / 122 STK60516

28 Timer 2 Watchdog Timer T2MOD Timer 2 Mode Control Register C xx0x RCAP2L Timer 2 Reload Capture Register, Low CA byte RCAP2H Timer 2 Reload Capture Register, High CB byte TL2 Timer 2, Low byte CC TH2 Timer 2, High byte CD CKCON Clock Control Register 8E CLK_SEL Clock Select Register D WDT Watchdog Timer Control Register E1 00xx x000 P4_OPT Selecting Port 4 pin function, as normal D9 xxxx 0000 port pin or ADC input ADCSEL Select ADC input channel for conversion DA 0xxx 0000 ADCVALH Buffer for the upper 8 bits of the converted DB ADC ADC value. ADCVALL Buffer for the lower 2 bits of the converted ADC value. DC xxxx xx00 ADCCLKSEL ADC Clock Select Register B ISPSLV ISP Control Slave Address E ISP ISPEN Write 93 (hex) to Enable The ISP mode E IAPEN IAP Enable Register E xxxx IAP RTC PCA IAP_ADRL Low-byte address of the flash memory E Location for IAP. IAP_ADRH High-byte address of the flash memory Location for IAP E IAPDATA IAP Data Register E RTCSEC The Present Second Register F1 TBD RTCMIN The Present Minute Register F2 TBD RTCHOUR The Present Hour Register F3 TBD RTCDAYH The Present Day High Byte Register F4 TBD RTCDAYL The Present Day Low Byte Register F5 TBD RTCCTL RTC Control Register F6 000x xxxx PRSEC Program RTC Second Register F PRMIN Program RTC Minute Register FA PRHOUR Program RTC Hour Register FB PRDAYH Program RTC Second High Byte Register FC PRDAYL Program RTC Second Low ByteRegister FD ALMIN Alarm Minute Setting Register FE ALHOUR Alarm Hour Setting Register FF PCA_EN_REG PCA Enable Register A PCA_FG_REG PCA Flag Register A PCA_CNTH PCA Counter High Byte Register A PCA_CNTL PCA Counter Low Byte Register A PCA0_CON PCA Channel 0 Control Register A PCA0_DH PCA Channel 0 Data High Byte Register A PCA0_DL PCA Channel 0 Data Low Byte Register A PCA1_CON PCA Channel 1 Control Register A PCA1_DH PCA Channel 1 Data High Byte Register AA PCA1_DL PCA Channel 1 Data Low Byte Register AB PCA2_CON PCA Channel 2 Control Register AC PCA2_DH PCA Channel 2 Data High Byte Register AD PCA2_DL PCA Channel 2 Data Low Byte Register AE PCA3_CON PCA Channel 3 Control Register AF Data Sheet 28 / 122 STK60516

29 SPI PCA3_DH PCA Channel 3 Data High Byte Register B PCA3_DL PCA Channel 3 Data Low Byte Register B PCA4_CON PCA Channel 4 Control Register B PCA4_DH PCA Channel 4 Data High Byte Register B PCA4_DL PCA Channel 4 Data Low Byte Register B SPICTL SPI Control Register E SPITXDATA SPI Data Register EA SPIMASTER SPI Master or Slave Select Register EB xxxx xxx1 Data Sheet 29 / 122 STK60516

30 10. Port 0, Port 1, Port 2, Port 3, and Port General Description The STK60516 has four 8-bits ports (Ports 0 ~ 4). All bits of Port 0 are push-pull output. All bits of Port 1, Port 2, Port 3 and Port 4 are push-pull outputs with internal weak pull-high PMOS Port 0 Port 0 pins are open-drain outputs. It has three functions: Pure bidirectional I/O data ports Low-byte address (A0 ~ A7) output and OP code input, when executing program in external program ROM mode (EA= 0, during power-on reset). Low-byte address (A0 ~ A7) and data bus during read/write to off-chip AUX memory. SFR P0_OPT must be properly programmed to ensure proper operation of Port 0. Output_enable Data_out Output Port 0 pins are open-drain outputs. Input_enable Data_in Port 0 schematics Port 1, Port 2, and Port 3 The Figure of Port 1, Port 2, and Port 3 shows Port 1, Port 2, and Port 3. They are push-pull outputs with internal weak pull-up. Port 1shares with the 5-channel, 8-bit, PCA for data input/output. Port 2 acts as data I/O or address bus (A8 ~ A15) during access to external Program ROM and AUX memory. SFR P2_OPT must be properly programmed to ensure proper operation of Port 2. Port 3 are multi-functional I/O port. Data Sheet 30 / 122 STK60516

31 VDD Pull-up Output_enable Data_out Output Input_enable Data_in Pins of Port 1, Port 2, and Port 3 are push-pull outputs with weak internal pull-up. The output sinking and sourcing capability is 4mA (typ.) The typical value of the equivalent resistance of the pull-up PMOS is 15K ohm. Port1, Port2, and Port3 Schematic Port 4 Port 4 share inputs with the 10-bit ADC. SFR P4_OPT needs to be properly programmed to ensure the proper operation of Port 4. VDD SFR P4_OPT Output_enable Data_out Output Input_enable Data_in Analog_in Port 4 Schematic Data Sheet 31 / 122 STK60516

32 11. Timer/Counter 0, Timer/Counter General Description There are seven SFRs associated with Timer/Counter 0 and Timer/Counter 1, as given in Table listed below. Both Timer/Counter 0 and Timer/Counter 1 can be configured to operate either as timers or event counters. SFRs associated with Timer/Counter 0 and Timer/Counter 1. SFR name Address (hex) Description Reset value (hex) TL0 8A These two SFRs are the lower 8 bits and higher 8 bits of 00 TH0 8C Timer/Counter TL1 8B These two SFRs are the lower 8 bits and higher 8 bits of 00 TH1 8D Timer/Counter TCON 88 Control register for Timer/Counter 0 and Timer/Counter TMOD 89 Mode selection register for Timer/Counter 0 and 00 Timer/Counter 1. CKCON 8E Clock frequency selection for Timer/Counter 0 and 01 Timer/Counter 1. CLKSEL D7 Clock frequency selection for Timer/Counter 0 and Timer/Counter Timer/Counter 0 and Timer/Counter 1 can be programmed to work in 4 operating modes: Mode 0: 13-bit timer/counter Mode 1: 16-bit timer/counter Mode 2: 8-bit counter with auto-reload Mode 3: Two 8-bit counters (only available from Timer 0) Mode Selection Register, SFR TMOD ( at 89H of SFR space) MSB LSB Gate C M1 M0 Gate C M1 M0 Timer 1 Timer 0 Timer 0/1 Mode Selection Register TIMER 0/1 MODE REGISTER (TMOD), LOCATED AT 89H OF THE SFR SPACE Bit Address TMOD.7 TMOD.6 TMOD.5 TMOD.4 TMOD.3 TMOD.2 TMOD.1 TMOD.0 Mnemonics Gate (Timer1) C/T (Timer1) M1 (Timer1) M0 (Timer1) Gate (Timer0) C/T (Timer0) M1 (Timer0) M0 (Timer 0) Description of Timer 0/1 Mode Selection Register MNEMONIC GATE BIT POSITION TMOD.7 FUNCTION Gating control for Timer 1. When set, Timer 1 is enabled only while INT1 pin is high and TR1 control bit is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set. Data Sheet 32 / 122 STK60516

33 C/T TMOD.6 Timer or Counter selection of Timer 1. When set, counter operation is selected. When cleared, timer operation is selected. M1, M0 TMOD.5 TMOD.4 GATE C/T TMOD.3 TMOD.2 M1, M0 TMOD.1 TMOD.0 Mode selection of Timer 1 (M1, M0) = 00 selects Mode 0 operation. (M1, M0) = 01 selects Mode 1 operation. (M1, M0) = 10 selects Mode 2 operation. (M1, M0) = 11 selects Mode 3 operation. (In mode 3, Timer/Counter 1 is stopped.) Gating control for Timer 0. When set, Timer 0 is enabled only while INT0 pin is high and TR0 control bit is set. When cleared, Timer 0 is enabled whenever TR0 control bit is set. Timer or Counter selection of Timer 0. When set, counter operation is selected. When cleared, timer operation is selected. Mode selection of Timer 0 (M1, M0) = 00 selects Mode 0 operation. (M1, M0) = 01 selects Mode 1 operation. (M1, M0) = 10 selects Mode 2 operation. (M1, M0) = 11 selects Mode 3 operation. (In mode 3, Timer/Counter 1 is stopped.) Timer 0/1 Control Register (SFR TCON at 88 H of the SFR space) Timer 0/1 Control Register TIMER 0/1 CONTROL REGISTER ( TCON ), LOCATED AT 88H OF THE SFR SPACE Bit Address TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 Mnemonics TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Description of Timer 0/1 Control Register MNEMONIC TF1 BIT POSITION TCON.7 FUNCTION Timer 1 overflow flag. Set by hardware on Timer/Counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TR1 TCON.6 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. TF0 TCON.5 Timer 0 overflow flag. Set by hardware on Timer/Counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. TR0 TCON.4 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. IE1 IT1 TCON.3 TCON.2 External Interrupt 1 Flag. Set by hardware when external interrupt 1 is detected. This bit is cleared after the interrupt is processed. That is, when the Return from Interrupt instruction is executed. Interrupt 1 Type Control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. IE0 TCON.1 External Interrupt 0 Flag. Set by hardware when external interrupt 0 is detected. Data Sheet 33 / 122 STK60516

34 This bit is cleared after the interrupt is processed. That is, when the Return from Interrupt instruction is executed. IT0 TCON.0 Interrupt 0 Type Control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt Clock Control Register, SFR CKCON, at address 8E hex of the SFR map For a description of the Clock Control Register, please refer to Table of Clock Control register Operating Modes Mode 0 (13-Bit Timer/Counter) When in mode 0, either of Timer 0 and Timer 1 acts as a 13-bit counter. Figure listed below shows the operation of both Timer 0 and Timer 1 in mode 0 operation CPU CLK Divide-by-12 T0M=0 T1M=0 o o Divide-by-4 T0M=1 T1M=1 P35/T1 Pin C = 0 o C = 1 SFR TL1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Gate (TMOD 7) P3.3 /INT1 Pin TR1 (TCON.6) o Enable (TMOD5,TMOD4)=00 o (TMOD5,TMOD4)=01 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SFR TH1 Overflow flag TF1 (TCON 7) Interrupt P3.4/T0 Pin C = 0 o C = 1 SFR TL0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Gate (TMOD 3) P3.2 /INT0 Pin TR0 (TCON.4) o Enable (TMOD5,TMOD4)=00 o (TMOD5,TMOD4)=01 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SFR TH0 Overflow flag TF0 (TCON 5) Interrupt In this mode, the Timer 0/Timer 1 registers are configured as a 13-bit register, which is composed of all the 8 bits of the TH1 (TH0) and the lower 5 bits of TL1 (TL0). The upper 3 bits of the TL1 (TL0) are indeterminate. The Timer Interrupt flag TF1 (TF0) is set to HIGH when the 13-bit register, acting as a counter, rolls over from all 1s to all 0s. The 13-bit register (counter) is enabled only under the following conditions: 1. TR0 (TR1) =1, and 2. Either Gate=0 or INT1 (INT0) =1. Data Sheet 34 / 122 STK60516

35 Mode 1 (16-Bit Timer/Counter) The configuration and operation of Mode 1 is the same as that of Mode 0, except that the registers are now 16 bits, instead of 13 bits when in Mode Mode 2 (8-Bit Counter with Auto-Reload) Mode 2 configures the SFR TL0 and SFR TL1 as an 8-bit counter, respectively, with automatic reloading from SFR TH0 and SFR TH1, respectively. When the contents of TL1 (TL0) changes from all 1s to all 0, the corresponding flag TF1 (TF0) is set to HIGH and the content of TH1 (TH0) is reloaded into TL1 (TL0). The action of this reloading does not change the content TH1 (TH0). The content of TH1 (TH0) can only be changed via programming these two SFRs. Figure listed below shows the operation of Timer 0 and Timer 1 in mode 2. CPU CLK Divide-by-12 T0M=0 T1M=0 o o Divide-by-4 T0M=1 T1M=1 P3.5/T1 Pin Gate (TMOD 7) P3.2 /INT1 Pin TR1 (TCON.6) o C = 0 o C = 1 Enable SFR TL1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SFR TH1 Reload Overflow flag TF1 (TCON 7) Interrupt P3.4/T0 Pin C = 0 o C = 1 SFR TL0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Overflow flag TF0 Interrupt TR0 (TCON.4) Reload (TCON 5) Gate (TMOD 3) o Enable bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 P3.2 /INT0 Pin SFR TH Mode 3 (Two 8-Bit Counters from Timer 0) When in Mode 3, Timer 1 stops counting and holds it value, and Timer 0 is configured into two separate counters: TL0 and TH0. The logic of Timer 0 in Mode 3 is shown below. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is configured into a timer function (counting machines cycles) and takes over the use of TR1 and TF1 from Timer 1. Hence, TH0 now controls the Timer 1 interrupt. Data Sheet 35 / 122 STK60516

36 CPU CLK Divide-by-12 Divide-by-4 o T0M=0 T0M=1 SFR TH0 Overflow flag TR1 (TCON.6) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TF1 (TCON 7) Interrupt C = 0 P3.4/T0 Pin o C = 1 SFR TL0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Overflow flag TF0 Interrupt (TCON 5) Gate (TMOD 3) TR0 (TCON.4) o Enable P3.2 /INT0 Pin Data Sheet 36 / 122 STK60516

37 12. Timer/Counter General Description and operation modes Timer 2 is mainly composed of four SFRs, TH2, TL2, RCAP2L, RCAP2H, and their control logic. SFR TH2 and SFR TL2 are cascaded into a 16-bit timer or counter, called Timer 2, which can be driven by either XTAL1 clock or off-chip clock pulse. SFR RCAP2L and SFR RCAP2H are also cascaded into a 16-bit register. This register is used as a capture register or reload register. When used as a capture register, it can capture the content of Timer 2. When used as a reload register, it can reload its content into Timer 2. Timer 2 s clock source can be from on-chip XTAL1 clock or off-chip clock pulse, depending on the state of the C/T2 bit, bit 1 of SFR T2CON. Timer 2 can operate in four different modes, listed below: 16-bit timer/counter, 16-bit timer/counter with capture, 16-bit timer/counter with auto-reload, or Baud-rate generator for UART. Table listed below describes how to configure Timer T2 to operate in different operating modes. Configuring Timer 2 into various operating modes RCLK TCLK CP/RL2 TR2 OPERATING MODE (T2CON.5) (T2CON.4) (T2CON.0) (T2CON.2) bit timer/counter, or 16-bit timer/counter with capture capability bit timer/counter with auto-reload. 1 x x 1 x 1 x 1 Baud rate generator for UART. Either RCLK=1 or TCLK=1 will configure Timer 2 into Baud Rate Generator mode. When Timer 2 is in Baud Rate Generator Mode, bit CP/RL2 is ignored. x x x 0 When TR=1, clock pulses is blocked from entering into Timer 2. That is, Timer 2 is disabled. x=don t care Special Function Registers associated with Timer 2 Timer 2 is associated with the 7 SFRs, listed in Table listed below. Three SFRs, CKCON, T2CON, and T2MOD, must be properly programmed to have timer 2 work properly. Timer 2 SFRs ADDRESS R/W MNEMONICS DESCRIPTION VALUE AFTER RESET 8E R/W CKCON Select clock frequency for Timer 0, Timer 1, and Timer 2, and memory stretch cycle for the MOVX Data Sheet 37 / 122 STK60516

38 instruction. C8 R/W T2CON Timer 2 Control Register ( bit-addressable ) C9 R/W T2MOD Timer 2 Mode Control register xxxx xx 0x CA R/W RCAP2L Timer 2 Reload/Capture Register, Low byte CB R/W RCAP2H Timer 2 Reload/Capture Register, High byte CC R/W TL2 Timer 2, Low byte CD R/W TH2 Timer 2, High byte The T2M Bit of Clock Control Register (SFR CKCON) The T2M bit (bit 5) of the Clock Control Register (CKCON SFR), located at 8E (hex) of the SFR memory space, selects the frequency of the clock used to drive Timer 2. When the T2M bit is programmed to LOW (T2M=0), (XTAL1 12) clock is selected to drive Timer 2. When the T2M bit is programmed to HIGH (T2M=1), (XTAL1 4) clock is selected to drive Timer 2. This bit has no effect when Timer 2 is programmed to work as a baud rate generator. T2M bit of SFR CKCON Clock Control Register (SFR CKCON), located at 8E(hex) of the SFR map Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics T2M T1M T0M MD2 MD1 MD0 Reset value Description of the T2M bit of SFR CKCON MNEMONIC BIT FUNCTION POSITION T2M CKCON.5 Select Timer 2 clock frequency. When T2M=0, Timer 2 uses (XTAL1 / 12) as clock frequency. When T2M=1, Timer 2 uses (XTAL1 / 4) as clock frequency Timer 2 Control Register (SFR T2CON) Timer 2 Control Register (SFR T2CON, C8 hex) Bit Address Bit.7 Bit.6 Bit.5 Bit.4 Bit.3 Bit.2 Bit.1 Bit.0 Mnemonics TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Reset value MNEMONIC TF2 EXF2 BIT POSITION T2CON.7 T2CON.6 FUNCTION Timer 2 overflow flag. This bit is set to HIGH when Timer 2 overflows from FFFF (hex) to 0000(hex). It must be cleared by software. TF2 will not be set when either RCLK or TCLK is 1. That is, when Timer 2 is in Baud Rate Generator mode, TF2 will never be set. Writing a 1 to TF2 bit forces a Timer 2 interrupt, if this interrupt function is enabled. Timer 2 External flag. This bit is set to HIGH when a capture or reload action is triggered by a high-to-low transition on the T2EX input pin and when EXEN2=1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to jump to Data Sheet 38 / 122 STK60516

39 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2CON.5 T2CON.4 T2CON.3 T2CON.2 T2CON.1 T2CON.0 Timer 2 interrupt subroutine. It must be cleared by software. Writing a 1 to the EXF2 bit forces a Timer 2 interrupt, if it is enabled. UART Receiver clock selection. This bit is used to select the receiver clock of the UART. If this bit is programmed to 1 (RCLK=1), UART uses Timer 2 overflow pulses as its receiver clock in Modes 1 and 3. If this bit is programmed to 0 (RCLK=0), UART uses Timer 1 overflow pulses as its receiver clock UART Transmitter clock selection. This bit is used to select the transmitter clock of the UART. If this bit is programmed to 1 (TCLK=1), UART uses Timer 2 overflow pulses as its transmitter clock in Modes 1 and 3. If this bit is programmed to 1 (TCLK=0), UART uses Timer 1 overflow pulses as its transmitter clock. Timer 2 external enable. EXEN2=1 allows a capture or reload to occur as a result of a high-to-low transition on the T2EX input, if Timer 2 is not in baud rate generator mode. EXEN2=0 causes Timer 2 to ignore all events at T2EX input. Start/Stop control for Timer 2. TR2=1 allows clocks to be added to Timer 2. TR2=0 prevent clocks from being added to Timer 2. Select timer function or counter function of Timer 2. C/T2= 0 selects the timer function. When used as a timer, Timer 2 runs at four XTAL1 clocks per increment or twelve XTAL1 clocks per increment, as selected by the T2M bit (CKCON.5) of the SFR CKCON, in all modes except baud rate generator mode. When used in baud rate generator mode, Timer 2 runs at two XTAL1 per increment, independent of the state of the T2M bit. C/T2=1 selects the external event counter function; falling-edge-triggered on the T2 input. Selection of capture or reload function. When this bit is programmed to HIGH (CP/RL2 =1), Timer 2 is in capture mode and capture occurs on a high-to-low transitions (falling edge) at T2EX, if EXEN2=1. When this bit is programmed to LOW (CP/RL2 =0), Timer 2 is in auto-reload mode and auto-reload occurs either with Timer 2 overflows or a high-to-low transitions at T2EX when EXEN2=1. When RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on a Timer 2 overflow Timer 2 Mode Control Register Timer 2 Mode Control Register, located at C9 (hex) of the SFR memory space, is a one-bit SFR. It is used to turn on Timer 2 pulse output to the P1.0/PWM0/T2 pin, when Timer 2 overflows from FFFFH. Timer 2 Mode Control Register (SFR T2MOD) Timer 2 Control Register ( SFR T2CON ), located at C8(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics T2OE Reset value x x x x x x 0 x MNEMONIC BIT POSITION FUNCTION Data Sheet 39 / 122 STK60516

40 T2OE T2MOD.1 Timer 2 output enable bit. Programming this bit to HIGH (T2OE=1) enables Timer 2 overflow pulse to be sent to the P1.0/T2 pin, as illustrated in the following figure bit Timer/Counter Mode In this mode, SFR TL2 and SFR TH2 are cascaded into a 16-bit timer or counter. SFR RCAP2L and SFR RCAP2H are not used. This 16-bit timer can then be used to count pulses from on-chip XTAL1 clock or off-chip external pulses, by properly programming bits T2M and C/T2. The TR2 bit, Timer 2 enable bit, must always be HIGH. When Timer 2 overflows from FFFFH to 0000H, a clock pulse with the duration of one cycle of XTAL1 clock is sent out. This pulse then sets the Timer 2 overflow flag, which, if enabled, can generate an interrupt. The overflow pulse can also be sent to Pin1.0, if the T2OE bit is enabled. Figure listed below shows Timer 2 configuration when it works as a 16-bit Timer/Counter. XTAL1 Divide-by-12 T2M=0 (CKCON.5) o P1.0/PWM0/T2 Pin Divide-by-4 T2M=1 C / T2 =0 o C / T2 =1 TR (T2CON.2) Timer 2 clock To Pin 1.0 T2OE (T2MOD.1=1) SFR TL2 SFR TH2 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Overflow flag TF2 This portion of circuit is ignored capture bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SFR RCAP2L SFR RCAP2H (TCON 7) External flag EXF2 (TCON 6) Timer2 Interrupt P1.1/PWM1/T2EX Pin Falling-edge detection EXEN2 (T2CON.3) CP / RL2=0 (T2CON.0) Timer 2 configuration in 16-bit timer/counter mode Data Sheet 40 / 122 STK60516

41 bit Timer/Counter with Capture capability (Capture Mode) When Timer 2 works in this mode, the content of SFR TL2 and SFR T2H can be captured into SFR RCAP2L and SFR RCAP2H, respectively, by an external triggering on the T2EX pin. Therefore, this mode is called Capture Mode. Bit EXEN2 is used to enable external trigger. If EXEN2=0, external trigger is disabled and Timer 2 is a pure 16-bit timer/counter which, upon overflowing, sets the Timer 2 overflow flag bit TF2. This flag may then be used to generate an interrupt. If EXEN2=1, Timer 2 also operates as a 16-bit timer/counter, but with the additional capability that a High-to-Low transition at the T2EX input causes the current value in TL2 and TH2 to be captured into SFR RCAP2L and SFR RCAP2H. The falling transition at T2EX also causes the EXF2 flag bit in T2CON to be set; this flag may also be used to generate an interrupt. The triggering pulse is also conditioned by the CP/RL2 bit. To enable the capture action, The CP/RL2 bit must be set to HIGH. In addition, Timer2 overflow pulse, whose duration is one cycle of Timer 2 clock, can be sent out to Pin 1.0, if T2OE=1. Figure listed below shows Timer 2, working as a 16-bit Timer/Counter with Capture capability. XTAL1 Divide-by-12 T2M=0 (CKCON.5) o P1.0/PWM0/T2 Pin Divide-by-4 T2M=1 C / T2 =0 o C / T2 =1 TR (T2CON.2) Timer 2 clock To Pin 1.0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 capture SFR TL2 SFR TH2 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SFR RCAP2L SFR RCAP2H Overflow flag TF2 (TCON 7) External flag EXF2 (TCON 6) T2OE (T2MOD.1=1) Timer2 Interrupt P1.1/PWM1/T2EX Pin Falling-edge detection Capture/Reload Selection EXEN2 (T2CON.3) CP / RL2=0 (T2CON.0) Timer 2 in 16-bit timer/counter mode with capture capability Data Sheet 41 / 122 STK60516

42 bit Timer/Counter with Auto-Reload capability (Auto-Reload Mode) When CP/RL2=0, Timer 2 is configured into Auto-reload mode. In the Auto-Reload mode, the Timer 2 s starting value is reloaded from SFR RCAP2L and SFR RCAP2H. There are two options selected by the EXEN2 bit in T2CON. If EXEN2=0, then, when Timer 2 overflows from FFFFH, it sets the TF2 flag bit and also causes the Timer 2 registers to be reloaded with the 16-bit value held in SFR RCAP2L and SFR RCAP2H. The 16-bit value held in RCAP2L and RCAP2H should be pre-loaded by software. If EXEN2= 1, Timer 2 operates as described above, but with the additional feature that a High-to-Low transition at the external input pin T2EX will also trigger the16-bit reload and set the EXF2 flag bit. In this mode, Timer 2 overflow pulse can also be sent to the P1.0 pin by setting the T2OE bit. Figure listed below shows Timer 2 configuration in Auto-reload mode. XTAL1 Divide-by-12 T2M=0 (CKCON.5) o Divide-by-4 T2M=1 C / T2 =0 o To Pin 1.0 P1.0/PWM0/T2 Pin C / T2 =1 T2OE (T2MOD.1=1) TR2 (TCON.2) SFR TL2 SFR TH2 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Overflow flag (TCON 7) TF2 Reload Timer2 Interrupt bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 EXF2 SFR RCAP2L SFR RCAP2H External flag (TCON 6) P1.1/PWM1/T2EX Pin Falling-edge detection Capture/Reload Selection EXEN2 (T2CON.3) CP / RL2=0 (T2CON.0) Timer 2 in auto-reload mode Baud Rate Generator Mode When either RCLK=1 or TCLK=1, Timer 2 is a baud rate generator for UART, without regard to the setting of CP/RL2 bit. The overflow pulse from Timer 2, after being divided by a divided-by-16 counter, is used as the transmitting clock or receiving clock of the UART in Mode 1 or Mode 3. Data Sheet 42 / 122 STK60516

43 The Baud Rate Generator mode is similar to the Auto-Reload mode, in that an overflow of Timer 2 causes Timer 2 registers (SFR TH2 and SFR TL2) to be reloaded with the 16-bit value held in the registers SFR RCAP2H and SFR RCAP2L, which should be preloaded by software. As a baud rate generator, Timer 2 counts at a frequency of 1/2 fxtal1. Baud rates of the UART in Modes 1 and 3 are determined by the following equation. Baud Rate = Timer 2 overflow rate 16 = F (XTAL1) (32) x [ (RCAP2H ; RCAP2L) ] Equation (1) In the above equation, (RCAP2H; RCAP2L) is the content of registers RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The 32 in the denominator is the result of the XTAL1 clock being divided by 2 and the Timer 2 overflow rate being divided by 16. Setting TCLK=1 or RCLK=1 automatically causes the XTAL1 clock to be divided Calculating The Value of RCAP2H and RCAP2L for a Desired Baud Rate If a programmer has decided to use a certain baud rate, the required value of RCAP2H and RCAP2L and be derived from Equation (2), which is re-manipulated from the Equation (1). (RCAP2H,RCAP2L) = XTAL1 32 x Baudrate Equation (2) Table listed below gives calculated value of RCAP2H and RCAP2L for some desired baud rates. BAUD RATE C/T2 33 MHz XTAL1 25 MHz XTAL MHz XTAL1 RCAP2H RCAP2L RCAP2H RCAP2L RCAP2H RCAP2L 57.6 Kb/s 0 FF EE FF F2 FF FA 19.2 Kb/s 0 FF CA FF D7 FF EE 9.6 Kb/s 0 FF 95 FF AF FF DC 4.8 Kb/s 0 FF 29 FF 5D FF B8 2.4 Kb/s 0 FE 52 FE BB FF Kb/s 0 FC A5 FD 75 FE E More about Timer 2 When either RCLK or TCLK is set to logic high, Timer 2 overflow does not set the TF2 bit of SFR T2CON and therefore will not generate interrupt. Consequently, the Timer 2 interrupt does not need to be disabled when in the baud rate generator mode. If EXEN2 is set to HIGH, a HIGH-to-LOW transition on T2EX will set the EXF2 bit of T2CON, but will not cause a reload from (RCAP2H; RCAP2L) to (TH2; TL2). Therefore, in this mode T2EX may still be used as an additional external interrupt. When Timer 2 is operating in the baud rate generator mode, registers SFR Data Sheet 43 / 122 STK60516

44 TH2 and SFR TL2 should not be accessed. Because in this mode, the timer is being incremented every two XTAL1 clock and therefore the results of a read or write may not be accurate. The SFRs RCAP2H and RCAP2L, however, may be read out but not written to. A write might overlap a reload and cause write and/or reload errors. If a write operation is required, Timer 2 should first be turned off by clearing the TR2 bit Timer 2 in Baud Rate Generator Mode The configuration of Timer 2 in baud rate generator mode is shown in Section XTAL1 P1.0/PWM0/T2 Pin Divide-by-2 C / T2 =0 o C / T2 =1 TR2 (T2CON2) SFR TL2 SFR TH2 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Timer 2 overflow pulse Reload bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SFR RCAP2L SFR RCAP2H Timer 1 overflow 1/2 RCLK 1 0 o o 0 o 1 o SMOD0 PCON.7 TCLK 1 0 o o 1/16 RX CLOCK (baud rate) 1/16 TX CLOCK (baud rate) P1.1/PWM1/T2EX Pin Falling-edge detection EXF2 Timer 2 interrupt EXEN2 (T2CON.3) External flag (T2CON.6) Timer 2 in baud-rate generator mode Data Sheet 44 / 122 STK60516

45 13. Reset Sources of Reset There are 5 sources to reset the STK60516: A high pulse from external RESET pin, Power-on reset, when power is first added to the STK60516 Low-voltage detection reset, Watchdog timer overflow, and ISP programming is on-going. The functional diagram of the reset sources is shown in Figure listed below. Low-voltage detection and reset Power-on- reset RESET pin Internal resistor (50K) Delay and Control Reset to CPU Core Peripheral blocks Watchdog timer overflow ISP Programming mode Functional diagram of reset circuit Power-On- Reset (POR) with fast-rising power supply The STK60516 can be reset by the on-chip power-on-reset, whose switching level is 2.7volts. The sequence of the power-on-reset is as follows: 1. As soon as the power supply (VDD) reaches the POR switching level, the on-chip POR generates a pulse, called POR Pulse. 2. This POR pulse then triggers an internal reset, POC. Also, this POR pulse resets the internal reset counter. 3. When the oscillator is stable enough, the oscillator clocks starts triggering the internal reset counter to count. 4. When the internal reset counter counts up to 2048 and overflows, the internal reset (POC) is released and the CPU starts executing instruction. The above sequence is further illustrated in Figure listed below. Data Sheet 45 / 122 STK60516

46 Supply Voltage Switching level of POR =2.7 volt POR Pulse Internal Reset Oscillator Time = 0 CPU running Oscillator Start-up time CPU starts instruction fetch from Program ROM address 0000 H 2048 oscillator period delay The oscillator clock is stable enough to trigger the internal divided -by-2048 counter. Timing of Power -On-Reset with fast rising VDD Asynchronous reset by adding a HIGH pulse to the RESET pin The STK60516 can be reset by adding a HIGH pulse to the RESET pin. The RESET pin is an input with an internal Schmitt-trigger for noise reduction. The CPU checks if there is a reset at cycle 4 (C4) of every instruction cycle. A reset is accomplished by holding the RESET pin HIGH for at least two instruction cycles while the oscillator is running. The CPU responds by executing an internal reset Low-power detection and reset The STK60516 has the capability of low-power detection and reset, whose switching level is 2.3volts.. The reset due to low power can be enabled or disabled by use of the LVR bit (bit 0) of SFR CHIPCON, at SFR address BF (hex). Setting LVR=0 enables low-power reset and setting LVR=1 disables low-power reset Reset by the Watchdog Timer overflow The microcontroller can also be reset by the Watchdog Timer overflow. Data Sheet 46 / 122 STK60516

47 14. Oscillator Circuit The Oscillator Circuit Idle CLK stop XTAL1 XTAL2 R C1 C2 Note: 1. C1=C2=22P ceramic 2. R=1M ohm Oscillator Circuit XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the STK60516 externally, XTAL1 is driven from an external clock source and XTAL2 is left open The values for R, C1, and C2 The recommended values for R, C1, and C2 given are for the frequency range from 2 MHz to 32 MHz. Since the performance of the crystal oscillator is closely related to the characteristics of the crystal itself, the user should contact the crystal manufacturer for its characteristics. The crystal parameters we used for design is shown in Figure listed below. C0 The parameter for the crystal is : R1=10 ohm, C1=25fF, and C0=7pF R1 R1 C1 L1 X1 Crystal parameters Data Sheet 47 / 122 STK60516

48 15. Interrupts General Description The STK60516 support s 11-source, 2-level, and 11 vectored-address interrupt system. Interrupts come from the sources listed below: External interrupt 0 External interrupt 1 Timer 0 overflow Timer 1 overflow Timer 2 overflow or External event Transmission or reception of the UART0 Transmission or reception of the UART1 RTC Interrupt ADC Interrupt PCA Interrupt SPI Interrupt Each interrupt can be individually enabled or disabled and can be assigned a low-level or high-level priority. All interrupts can be globally disabled. When an interrupt event occurs, its corresponding interrupt flag is raised to HIGH. This flag should be cleared by the user interrupt service routine. Source number Interrupt sources External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Flags generated by the interrupt Interrupt enable bit Interrupt priority bit Priority within level IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) 1 1 Vector Address 0003H TF0 (TCON.5) ET0 (IE.1) PT0 (IP.1) 2 000BH IE1 (TCON.3) EX1 (IE.2) PX1 (IP.2) H TF1 (TCON.7) ET1 (IE.3) PT1 (IP.3) 4 001BH TI_0 (SCON0.1) 5 UART0 Interrupt RI_0 (SCON0.0) ES0 (IE.4) PS0 (IP.4) H RI_0 (SCON1.0) Timer 2 TF2 (T2CON.7) overflow ET2 (IE.5) PT2 (IP.5) 6 002BH UART1 Interrupt TI_0 (SCON1.1) ES1(IE.6) PS1(IP.6) 7 003BH RTC Interrupt EXIF.4 EX2(EIE.0) PX2(EIP.0) H Data Sheet 48 / 122 STK60516

49 ADC Interrupt PCA Interrupt SPI Interrupt EXIF.5 EX3(EIE.1) PX3(EIP.1) 9 004BH EXIF.6 EX4(EIE.2) PX4(EIP.2) H EXIF.7 EX5(EIE.3) PX5(EIP.3) BH Interrupt Enable Registers Each of the interrupt sources can be individually enabled or disabled by setting its enable/disable bit in the Interrupt Enable Registers (SFR IE), located at A8 (hex) of the SFR map. All interrupts can be globally disabled by clearing the EA bit of SFR IE. The Interrupt Enable Register is described in Table listed below. INTERRUPT ENABLE REGISTER ( SFR IE ), LOCATED AT A8H OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 Reset value MNEMONIC BIT FUNCTION POSITION EA IE.7 Global enable or disable of all interrupts. When IE.7 = 0, all interrupts are globally disabled. When IE.7 = 1, all interrupt sources are globally enabled. ES1 IE.6 Enable or disable UART1 interrupt. When IE.6 = 1, UART1 interrupt is enabled. When IE.6 = 0, UART1 interrupt is disabled. EX2 IE.5 Enable or disable interrupt due to Timer 2 overflow, or T2EX pin (shared with P1.1) interrupt. When IE.5 = 1, external interrupt 2 is enabled. When IE.5 = 0, external interrupt 2 is disabled. ES0 IE.4 Enable or disable UART0 interrupt. When IE.4 = 1, UART0 interrupt is enabled. When IE.4 = 0, UART0 interrupt is disabled. ET1 IE.3 Enable Timer 1 overflow interrupt. When IE.3 = 1, Timer 1 overflow interrupt is enabled. When IE.3 = 0, Timer 1 overflow interrupt is disabled. EX1 IE.2 Enable External Interrupt 1. When IE.2 = 1, External Interrupt 1 is enabled. When IE.2 = 0, External Interrupt 1 is disabled. ET0 IE.1 Enable Timer 0 overflow interrupt. When IE.1 = 1, Timer 0 overflow interrupt is enabled. When IE.1 = 0, Timer 0 overflow interrupt is disabled. EX0 IE.0 Enable External Interrupt 0. When IE.0 = 1, External Interrupt 0 is enabled. When IE.0 = 0, External Interrupt 0 is disabled Interrupt Priority Register SFR IP Each interrupt source can be assigned one of two priority levels: high and low. Interrupt priority is defined by the Interrupt Priority Register (SFR IP, at B8 hex of the SFR map). Interrupt priority levels are as follows: Data Sheet 49 / 122 STK60516

50 Logic 0 = low priority Logic 1 = high priority. A low priority interrupt may be interrupted by a high priority interrupt. A high priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority occur simultaneously, the high priority level request is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence Description of Interrupt Priority Register SFR IP MNEMONIC BIT FUNCTION POSITION IP.7 Not implemented, return a 1 when read. PS1 IP.6 Enable or disable UART1 interrupt. When IE.6 = 1, UART1 interrupt is enabled. When IE.6 = 0, UART1 interrupt is disabled. PT2 IP.5 Define the priority of Timer2 overflow interrupt, or T2EX-pin (shared with P1.1) interrupt. When IP.5 = 1, Timer 2 overflow is a high priority interrupt. When IP.5 = 0, Timer 2 overflow is a low priority interrupt. PS0 IP.4 Define the priority level of UART0 interrupt. When IP.4 = 1, UART0 interrupt is a high priority interrupt. When IP.4 = 0, UART0 interrupt is low priority interrupt. PT1 IP.3 Define the interrupt level of Timer 1 overflow interrupt. When IP.3 = 1, Timer 1 overflow interrupt is a high priority interrupt. When IP.3 = 0, Timer 1 overflow interrupt is a low priority interrupt. PX1 IP.2 Define the interrupt level of External Interrupt 1. When IP.2 = 1, External Interrupt 1 is a high priority interrupt. When IP.2 = 0, External Interrupt 1 is a low priority interrupt. PT0 IP.1 Define the interrupt level of Timer 0 overflow interrupt. When IP.1 = 1, Timer 0 overflow is a high priority interrupt. When IP.1 = 0, Timer 0 overflow is a low priority interrupt. PX0 IP.0 Define the interrupt level of External Interrupt 0. When IP.0 = 1, External Interrupt 0 is a high priority interrupt. When IP.1 = 0, External Interrupt 0 is a low priority level Interrupt Vectors The vector indicates the Program Memory location where the appropriate interrupt service routine starts. Please refer to Table listed below for interrupt vector addresses. Source number Interrupt sources Flags generated by the interrupt Interrupt enable bit Interrupt priority bit Priority within level Vector Address External Interrupt 0 IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) H Timer 0 Overflow TF0 (TCON.5) ET0 (IE.1) PT0 (IP.1) 2 000BH External Interrupt 1 IE1 (TCON.3) EX1 (IE.2) PX1 (IP.2) H Data Sheet 50 / 122 STK60516

51 4 5 Timer 1 Overflow UART0 Interrupt TF1 (TCON.7) ET1 (IE.3) PT1 (IP.3) 4 001BH TI_0 (SCON0.1) ES0 (IE.4) PS0 (IP.4) H RI_0 (SCON0.0) 6 Timer 2 overflow TF2 (T2CON.7) ET2 (IE.5) PT2 (IP.5) 6 002BH 7 UART1 Interrupt TI_1 (SCON1.1) RI_1 (SCON1.0) ES1(IE.6) PS1(IP.6) 7 003BH RTC Interrupt EXIF.4 EX2(EIE.0) PX2(EIP.0) H ADC Interrupt EXIF.5 EX3(EIE.1) PX3(EIP.1) 9 004BH PCA Interrupt EXIF.6 EX4(EIE.2) PX4(EIP.2) H 11 SPI Interrupt EXIF.7 EX5(EIE.3) PX5(EIP.3) BH Data Sheet 51 / 122 STK60516

52 16. Overall View of The Interrupt System Timer0 Overflow TF0 TCON.5 ET0 IE.1 PT0 IP.1 Timer1 Overflow Timer2 Overflow TF2 TF1 TCON.7 ET1 IE.3 PT1 IP.2 T2EX EXEN2 T2CON.3 T2CON.7 EXF2 T2CON.6 OR EX2 IE.5 PT1 IP.2 RI_0 UART0 SCON0.0 TI_0 SCON0.1 OR ES IE.4 PS0 IP.4 RI_1 UART1 SCON1.0 TI_1 SCON1.1 P3.2/INT0 OR IE0 TCON.1 ES IE.6 EX0 IE.1 PS1 PX0 High Priority Low Priority P3.3/INT1 IE1 TCON.3 EX1 IE.2 PX1 RTC overflow EX2 PX2 ADC transformation finish EX3 PX3 PCA EX4 PX4 SPI data transmit or receive EX5 PX5 IE.7 Data Sheet 52 / 122 STK60516

53 17. UART0 and UART General Description The STK60516 has two serial ports: UART1 and UART0. Both UART0 and UART1 are identical in operation to Industrial-standard 80C51 s serial port, with the exception that Timer 2 can not be used as the baud rate generator of UART1. Both UART0 and UART1 are full-duplex serial ports. The word full-duplex means that that can transmit and receive simultaneously. Each of them has one receiver data pin (RXD) and one transmitter data pin (TXD). The receiver data pins share with port pins P3.0 and P1.0. The transmitter data pins share with port pins P3.1 and P1.1. Four SFRs: SCON0, SBUF0, SCON1 and SBUF1, are associated with the UART0 and UART1. Their functions are given in Table listed below. SFRs associated with UART0 and UART1. Mnemonics Address (Hex) Function SFR SCON0 98 Control and status register of UART0. SFR SBUF0 99 Data buffer for both transmission and reception of UART0. SFR SCON1 C0 Control and status register of UART1. SFR SBUF1 C1 Data buffer for both transmission and reception of UART1. From software point of view, data transmission and reception are both through the SFR SBUF0 (SFR SBUF1). Writing to SFR SBUF0 (SFR SBUF1) loads data to be transmitted to SFR SBUF0 (SFR SBUF1). Reading SFR SBUF0 (SFR SBUF1) reads received data. But, physically, writing to SFR SBUF0 (SFR SBUF1) loads data to a physical Transmit Register and reading SFR SBUF0 (SFR SBUF1) reads a physical Receive Register. A programmer s model of UART0 is shown in Figure listed below. The model for UART1 is the same. P3.1 TXD0 P3.0 RXD0 Full-duplex UART0 SFR SCON0 SFR SBUF CPU Transmit Register Receive Register Programmer s model of the UART Summary of operation Modes of UART0 and UART1 Each of UART0 and UART1 has four operating modes. These modes are summarized in Table listed below: Operating modes of UART0 and UART1 Data Sheet 53 / 122 STK60516

54 Mode Operation Sync/ Baud clock Data Start/Stop 9th-bit Async bits function 0 8-bit shift register Sync clk/4 or clk/12 8 None None 1 10-bit data transmission and reception 2 11-bit data transmission and reception 3 11-bit data transmission and reception Async For UART0, Timer 8 1 start, 1 None 1 or Timer 2. stop For UART1, Timer 1 only. Async clk/32 or clk/clk start, 1 0, 1, parity stop Async For UART0, Timer 9 1 start, 1 0, 1, parity 1 or Timer 2. stop For UART1, Timer 1 only Control/Status Register and operation Mode of UART Control/Status Register (SFR SCON0) of UART0 The Serial Port Control/Status Register is SFR SCON0, located at address 98H of the SFR memory space. Serial Port Control and Status Register 0, SFR SCON0, AT 98 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics S M0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 Description of SFR SCON0 MNEMONIC BIT POSITION FUNCTION SM0_0 SM1_0 SCON0.7 SCON0.6 These two bits are used to select an operation mode. SM0_0 SM1_0 Modes 0 0 Mode0 0 1 Mode1 1 0 Mode2 1 1 Mode3 SM2_0 SCON0.5 Multiprocessor Communication Enable. In Mode 0, SM2_0 decides the baud rate. When SM2_0 = 0, the baud rate is CPUCLK*1/12. When SM2_0 = 1, the baud rate is CPU_CLK*1/4. In Mode 1: if SM2_0=1, then RI_0 will be set to high only when a HIGH stop bit has been received. if SM2_0=0, then RI_0 will always be set to high without regard to the state of the received stop bit. In modes 2 and 3, SM2_0 enables the multiprocessor communication feature. SM2_0 is used to disable interrupt to the un-addressed slave receivers, when data bytes are transmitted from the master. REN_0 SCON0.4 Reception Enable. When REN_0=1, UART0 is enabled for reception. When REN_0=0, UART0 is disabled from reception. TB8_0 SCON0.3 TB8_0 is the 9th data bit that will be transmitted in Mode 2 or Mode 3. Set or cleared by software as desired. RB8_0 SCON0.2 In Mode 2 and Mode 3, RB8_0 is the 9th data bit received. Data Sheet 54 / 122 STK60516

55 TI_0 RI_0 SCON0.1 SCON0.0 In Mode 1, RB8_0 indicates the state of the received stop bit. In Mode 0, RB8_0 is not used. The Transmit Interrupt Flag. This flag can only be cleared by software. In mode 0, this bit is set to logic 1 by hardware at the end of the 8th bit time. In mode 1, mode 2, and mode 3, this bit is set to logic 1 by hardware at the beginning of the stop bit time. The Receive Interrupt Flag. This flag can only be cleared by software. In mode 0, this bit is set to logic 1 by hardware at the end of the 8th bit time. In mode 1, this bit is set to logic 1 after the last sampling of the stop bit, subject to the state of SM2_0. In mode 2, and mode 3, this bit is set to logic 1 by hardware at the last sampling of the stop bit Operation mode of UART0 Table listed below gives detailed description of UART0 s operation modes. The selection of operation modes is decided by the setting of the SM0_0 bit and the SM1_0 bit of SFR SCON0. UART0 Operation Modes. Mode SM0_0 SM1_0 Description Mode bit serial transmission or reception. In this mode, 8 bits of data enters or exits through the P3.0/RXD0 pin. The P3.1/TXD0 pin always outputs the shift clock. The Least Significant Bit (LSB) is received or transmitted first. The baud rate is either 1/4 or 1/12 of the CPU frequency. Mode bit serial transmission or reception. In this mode, 10 binary bits are transmitted (through P3.1/TXD0) or received (through P3.0/RXD0). The 10 binary bits are composed of a start bit(1), 8 data bits (LSB first), and a stop bit(1). On reception, the stop bit goes into bit RB8 of the SFR SCON0. The baud rate comes from Timer 1 or Timer 2 overflow. Mode bit serial transmission or reception. In this mode, 11 binary bits are transmitted (through P3.1/TXD0) or received (through P3.0/RXD). The 11 binary bits are composed of a start bit(1), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit(1). On transmission, the 9th data bit (TB8 in SCON0) can be programmed to be 1 or 0. For example, in application, the parity bit P of SFR PSW can be moved into TB8 of SCON0. On reception, the 9th data bit goes into RB8 of SFR SCON0, while the stop bit is ignored. The baud rate is programmable to be 1/32 or 1/64 of CPU frequency. Mode bit serial transmission or reception. In this mode, 11 binary bits are transmitted (through P3.1/TXD0) or received (through P3.0/RXD0). The 11 binary bits are composed of a start bit(1), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit(1). Actually, Mode 3 is a combination of Mode 2 protocol and Mode 1 baud rate. The baud rate in Mode 3 comes from Timer 1 or Timer 2 overflow. Data Sheet 55 / 122 STK60516

56 Mode 0 Transmission and Reception of Mode 0 When operating in mode 0, the UART0 is an 8-bit data shift register. Eight bits of data can be shifted into or out from SFR SBUF0, via the P3.0/RXD0 pin. The shifting clock always comes out from the P3.1/TXD0 pin, without regard to if the data is shifted into or out from SFR SBUF0. Baud Rate of Mode 0 In mode 0, the UART0 s baud rate is either CPU_CLK*1/12 or CPU_CLK*1/4, depending on the value of the SM2 bit. If SM2 = 1, the baud rate (i.e., shifting clock frequency) is CPU_CLK*1/4. If SM2 = 0, then the baud rate is CPU_CLK*1/12. Transmission Timing of Mode 0 Data transmission begins when an instruction writes to SFR SBUF0. That is, whenever an instruction with SFR SBUF0 as its destination operand is executed, data transmission will be initiated. The UART0 shifts the data out, LSB first, at the selected baud rate, until all 8 bits of data have been shifted out. Write to SFR SBUF0 P3.1/TXD0 P3.0/RXD0 D0 D1 D2 D3 D4 D5 D6 D7 TI_0 RI_0 always low UART0 mode 0 transmission timing when baud rate is CPU_CLK 1/4 Reception Timing of Mode 0 To enable data reception, the REN_0 bit must first be set to logic HIGH. Data reception begins when the RI_0 bit is cleared. Shifting clock is then sent out from the P3.1/TXD0 pin to shift in data, LSB first, until all 8 bits of external data have been shifted in. Each bit of data is shifted in on the rising edge of the shifting clock. Four CPU clocks after the 8th data bit has been shifted in, the RI_0 bit is set to logic HIGH. The RI_0=1 indicates that 8 bits of data have been received. Data Sheet 56 / 122 STK60516

57 Write to SFR SBUF0 P3.1/TXD0 P3.0/RXD0 D0 D1 D2 D3 D4 D5 D6 D7 RI_0 TI_0 always low UART0 mode 0 reception timing when baud rate is CPU_CLK 1/4 Mode 1 Operation of Mode 1 Mode 1 provides 10-bits, asynchronous, full-duplex transmission or reception. One transmission or reception word is composed of the following bits: One start bit. Eight data bits (D0~D7). One stop bit. The 10-bits word format is shown below: STOP D0 D1 D2 D3 D4 D5 D6 D7 START The data bits are transmitted and received LSB first. For receive operations, the received stop bit is stored to the RB8_0 bit of SFR SCON0. Baud Rate of Mode1 Mode 1 baud rate can be from timer 1 overflow or timer 2 overflow. Data Transmission Timing in Mode1 A data transmission session in mode 1 involves two steps: 1. Application program issues a write to SFR SBUF0. 2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation circuit. 3. The UART0 transmits data out from the P3.1/TXD0 pin in the following order: START bit, data bits (D0~D7), and STOP bit. The START bit is transmitted out first. The TI_0 (SCON0.1) bit of SFR SCON0 is set to HIGH two CPU clocks after the stop bit has been transmitted. Data Sheet 57 / 122 STK60516

58 TX CLK Internal shift clock P3.1/TXD0 start D0 D1 D2 D3 D4 D5 D6 D7 stop P3.0/RXD0 always high TI_0 RI_0 always low UART0 mode 1 transmission timing Data Reception Timing in Mode 1 A data reception session in mode 1 is as follows: 1. First, the reception function of the UART0 must be enabled by setting REN_0=1 and then the UART0 starts detecting. If there is a falling edge on the P3.0/RXD0 input. For detecting this falling edge, UART0 samples the P3.0/RXD0 input pin sixteen times per bit time for any baud rate. 2. When a falling edge on the P3.0/RXD0 pin is detected, the divided-by-16 counter of the baud rate generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 or Timer 2 overflow to bit boundaries. 3. For noise rejection, the UART0 decides the value of each received bit by majority decision of three consecutive samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still regarded as HIGH. 4. If the first received bit is not LOW, then the reception session is aborted and the UART0 waits for another falling edge on the P3.0/RXD0 pin. 5. If the first received bit is LOW, then a reception session is initiated and the UART0 continues to receive the following data bits (D0~D7). The bit value is decided by use of majority decision. 6. At the middle of the stop bit time, the UART0 checks the following conditions: a) RI_0 must be LOW. b) If SM2 has been programmed to HIGH, then the received stop bit must also be HIGH. (If SM2 has been Data Sheet 58 / 122 STK60516

59 programmed to LOW, the received stop bit can be LOW or HIGH.) 7. If the above conditions are met, then the UART0 moves the received data byte from the temporary Receive Register to SFR SBUF0, moves the received stop bit to the RB8 bit of SFR SCON0, and set RI_0 bit to HIGH, triggering an UART0 data reception interrupt. If the above conditions are not met, the received data is ignored and the receive session is aborted. 8. After the middle of the stop bit time, the UART0 continues to wait for another high-to-low transition on the P3.0/RXD0 pin. RX CLK (baud rate) P3.0/RXD0 start D0 D1 D2 D3 D4 D5 D6 D7 stop Bit sampling Data shift in clk P3.1/TXD0 always high RI_0 TI_0 always low UART0 mode 1 reception timing Mode 2 Operation of Mode2 Mode 2 provides 11-bits, asynchronous, full-duplex transmission or reception. A transmission or reception word is composed of the following 11 bits: One start bit. Eight data bits. One programmable 9th bit. One stop bit. The word format is shown below: START D0 D1 D2 D3 D4 D5 D6 D7 TB8_0/RB8_0 STOP The data bits are transmitted and received LSB first. For transmission, the 9th bit is determined by the value in TB8. To use the 9th bit as a parity bit, move the value of the P bit of SFR PSW to TB8. Data Sheet 59 / 122 STK60516

60 Baud Rate of Mode 2 In Mode 2, the baud rate is decided by the value of the SMOD0 bit in the SFR PCON. If SMOD0=0, the default value of SMOD0 after reset, the baud rate is CPU_CLK*1/64. That is, the duration of a bit time is 64 CPU clocks. If SMOD0=1, the baud rate is CPU_CLK*1/32. That is, the duration of a bit time is 32 CPU clocks. Data Transmission Timing in Mode 2 A data transmission session in mode 2 involves the following steps: 1. Application program issues a write to SFR SBUF0. 2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation circuit. 3. The UART0 transmits data out from the P3.1/TXD0 pin in the following order: START bit, data bits (D0~D7), and STOP bit. The START bit is transmitted out first. 4. The TI_0 (SCON0.1) bit of SFR SCON0 is set to HIGH when the stop bit is placed on the P3.1/TXD0 pin. Write to SFR SBUF0 TX CLK Data shift out clk P3.1/TXD0 start D0 D1 D2 D3 D4 D5 D6 D7 TB8 stop P3.0/RXD0 always high TI_0 RI_0 always low UART0 mode 2 transmission timing Data Reception Timing in Mode 2 A data reception session in mode 2 is as follows: 1. First, the reception function of the UART0 must be enabled by setting REN_0=1 and then the UART0 starts detecting. If there is a falling edge on the P3.0/RXD0 input. For detecting this falling edge, UART0 samples the P3.0/RXD0 input pin sixteen times per bit time for any baud rate. Data Sheet 60 / 122 STK60516

61 2. When a falling edge on the P3.0/RXD0 pin is detected by UART0, the divided-by-16 counter of the baud rate generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 or Timer 2 overflow to bit boundaries. 3. For noise rejection, the UART0 decides the value of each received bit by majority decision of three consecutive samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still regarded as HIGH. 4. If the first received bit is not LOW, then the reception session is aborted and the UART0 waits for another falling edge on the P3.0/RXD0 pin. 5. If the first received bit is LOW, then a reception session is initiated and the UART0 continues to receive the following data bits (D0~D7). The bit value is decided by use of majority decision. 6. At the middle of the stop bit time, the UART0 checks the following conditions: a) RI_0 must be LOW, b) If SM2 has been programmed to HIGH, then the received 9th bit must also be HIGH. (If SM2 has been programmed to LOW, the received 9th bit can be LOW or HIGH.) 7. If the above conditions are met, then the UART0 moves the received data byte from the temporary Receive Register to SFR SBUF0, moves the received 9th bit to the RB8 bit of SFR SCON0, and set RI_0 bit to HIGH, triggering an UART0 data reception interrupt. If the above conditions are not met, the received data is ignored and the receive session is aborted. 8. After the middle of the stop bit time, the UART0 continues to wait for another high-to-low transition on the P3.0/RXD0 pin. Data Sheet 61 / 122 STK60516

62 RX CLK P3.0/RXD0 start D0 D1 D2 D3 D4 D5 D6 D7 RB8 stop Bit sampling Data shift in clk P3.1/TXD0 always high RI_0 TI_0 always low UART0 mode 2 reception timing Mode 3 1 Operation of Mode 3 Mode 3 provides 11-bits, asynchronous, full-duplex transmission or reception. Its transmission or reception word format is composed of: One start bit, Eight data bits, One programmable 9th bit, and One stop bit. The word format is shown below. It is actually identical to that of Mode 2. START D0 D1 D2 D3 D4 D5 D6 D7 TB8_0/RB8_0 STOP The data bits are transmitted and received LSB first. Mode 3 operation is actually identical to Mode 2 operation, except baud rate. The Mode 3 baud rate generation is identical to Mode 1. That is, Mode 3 is a combination of Mode 2 transmission/reception protocol and Mode 1 baud rate generation. Baud Rate of Mode 3 Mode 3 baud rate can be from timer 1 overflow or timer 2 overflow. Data Transmission in Mode 3 A data transmission session in mode 2 involves the following steps: 1. Application program issues a write to SFR SBUF0. Data Sheet 62 / 122 STK60516

63 2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation circuit. 3. The UART0 transmits data out from the P3.1/TXD0 pin in the following order: START bit, data bits (D0~D7), and STOP bit. The START bit is transmitted out first. 4. The TI_0 (SCON0.1) bit of SFR SCON0 is set to HIGH when the stop bit is placed on the P3.1/TXD0 pin. Write to SFR SBUF0 TX CLK Data shift out clk P3.1/TXD0 start D0 D1 D2 D3 D4 D5 D6 D7 TB8 stop P3.0/RXD0 always high TI_0 RI_0 always low UART0 mode 2 transmission timing Data Reception in Mode 3 A data reception session in mode 2 is as follows: 1. First, the reception function of the UART0 must be enabled by setting REN_0=1 and then the UART0 starts detecting. If there is a falling edge on the P3.0/RXD0 input. For detecting this falling edge, UART0 samples the P3.0/RXD0 input pin sixteen times per bit time for any baud rate. 2. When a falling edge on the P3.0/RXD0 pin is detected by UART0, the divided-by-16 counter of the baud rate generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 or Timer 2 overflow to bit boundaries. 3. For noise rejection, the UART0 decides the value of each received bit by majority decision of three consecutive samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still regarded as HIGH. Data Sheet 63 / 122 STK60516

64 4. If the first received bit is not LOW, then the reception session is aborted and the UART0 waits for another falling edge on the P3.0/RXD0 pin. 5. If the first received bit is LOW, then a reception session is initiated and the UART0 continues to receive the following data bits (D0~D7). The bit value is decided by use of majority decision. 6. At the middle of the stop bit time, the UART0 checks the following conditions: a) RI_0 must be LOW, b) If SM2 has been programmed to HIGH, then the received 9th bit must also be HIGH. (If SM2 has been programmed to LOW, the received 9th bit can be LOW or HIGH.) 7. If the above conditions are met, then the UART0 moves the received data byte from the temporary Receive Register to SFR SBUF0, moves the received 9th bit to the RB8 bit of SFR SCON0, and set RI_0 bit to HIGH, triggering an UART0 data reception interrupt. If the above conditions are not met, the received data is ignored and the receive session is aborted. 8. After the middle of the stop bit time, the UART0 continues to wait for another high-to-low transition on the P3.0/RXD0 pin. RX CLK P3.0/RXD0 start D0 D1 D2 D3 D4 D5 D6 D7 RB8 stop Bit sampling Data shift in clk P3.1/TXD0 always high RI_0 TI_0 always low UART0 mode 2 reception timing Baud Rate Generation for Mode 1 and Mode 3 In both Mode 1 and Mode 3, baud rate is derived from Timer 1 or Timer 2 overflow. Figure listed below gives the divider circuit used to derive receiver baud rate and transmitter baud rate from Timer 1 overflow or Timer 2 overflow. Data Sheet 64 / 122 STK60516

65 Timer 1 overflow pulse 1/2 Note: * RCLK = T2CON 5 * TCLK = T2CON 4 Timer 2 overflow pulse RCLK 1 o 0 o 0 1 o o SMD0 (PCON 7) TCLK 1 o 0 o 1/16 RX CLOCK (baud rate) 1/16 TX CLOCK (baud rate) Baud rate generation from Timer 1 or Timer 2 overflow Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of the SMOD0 bit of the SFR PCON, as follows: SMOD Baud rate = 2 32 x Timer 1 overflow rate The Timer 1 interrupt should be disabled in this application. The Timer 1 itself can be programmed for either timer or counter operation in any of its 3 running modes. In most typical applications, it is programmed for timer operation, in the Auto-Reload mode (high nibble of TMOD=0010B). In this case the baud rate is given by the formula: SMOD Baud rate = 2 32 x CPU_CLK x 1 12 x TH1 Timer 1 reload value for UART0 Mode 1 and Mode 3 baud rate. Desired Baud rate SMOD0 (PCON.7) C/T2 (TMOD.6) Timer 1 Mode 33 MHz XTAL1 25 MHz XTAL MHz XTAL Kb/s FDH FEh FFh 19.2 Kb/s F7h F9h FDh 9.6 Kb/s EEh F2h FAh 4.8 Kb/s DCh E5h F4h 2.4 Kb/s B8h CAh E8h 1.2 Kb/s h 93h D0h Data Sheet 65 / 122 STK60516

66 Using Timer 2 to Generate Baud Rates Please refer to Section Baud Rate Generator Mode for detailed description of using Timer 2 to generate baud rate for the UART Multiprocessor communications Mode 2 supports multiprocessor communication, in which a master transmitter can send data to one or more slave receivers. The 9th data bit is used to indicate an address byte or data byte. When the 9th data bit is HIGH, the transmitted byte is an address byte. When the 9th data bit is LOW, the transmitted byte is a data byte START D0 D1 D2 D3 D4 D5 D6 D7 address /data STOP Master Transmitter Slave Receiver Slave Receiver Slave Receiver TX RX TX RX TX RX TX RX UART0 multiprocessor communication A typical session of multiprocessor communication is as follows: 1. Enable all slave receivers for reception by setting REN_0=1 and clearing RI_0=0. 2. Setting SM2=1 for all slave receivers. SM=1 indicates that only an address byte, which has its 9th data bit set to HIGH, can be received by all slave receivers. 3. The master transmitter broadcasts an address byte out. Data Sheet 66 / 122 STK60516

67 4. All the UART0s of all slave receivers receive this address byte and interrupt their respective CPU. 5. All slave receivers execute their UART0 interrupt subroutine. 6. In the interrupt subroutine, the received address is compared with the slave s pre-assigned address. If the two addresses match, then the SM2_0 bit is cleared to LOW. SM2_0=LOW indicates that the 9th bit data bit can be LOW or HIGH. That is, the addressed slave can always receive next transmitted data bytes from the master transmitter. 7. If the received address does not match with the slave s own pre-assigned address, the slave keeps its SM2_0 bit set to HIGH, indicating that the slave will not be able to receive the next transmitted data bytes. 8. A communication channel is therefore established between the master transmitter and the addressed slave receiver. The master can continue to send data bytes to the addressed slave receiver. All other un-addressed slave receivers can not receive the following data bytes, because their SM2_0 bits remain at HIGH. 9. Once the entire message has been received, the addressed slave sets its SM2_0 bit to HIGH to block further interrupt and waits for the next address byte Control/status Register and operation mode of UART Operation Modes of UART1 Table listed below gives detailed description for each of the four operation modes of UART1. The selection of operation modes depends on the setting of the SM0_1 bit and the SM1 1 bit of SFR SCON1. UART1 Operation Modes. Mode SM0_1 SM1_1 Description Mode bit serial transmission or reception. In this mode, 8 bits of data enters or exits through the P2.6/RXD1 pin. The P2.7/TXD1 pin always outputs the shift clock. The Least Significant Bit (LSB) is received or transmitted first. The baud rate can be either 1/4 or 1/12 of the CPU clock frequency, selected by the setting of the SM2_1 bit of SFR SCON1. Mode bit serial transmission or reception. In this mode, 10 binary bits are transmitted (through P2.7/TXD1) or received (through P2.6/RXD1). The 10 binary bits are composed of a start bit (1), 8 data bits (LSB first), and a stop bit(1). On reception, the stop bit goes into bit RB8_1 of SFR SCON1. The baud rate only comes from Timer 1 overflow. Timer 2 overflow can not be used as baud rate for UART1. Data Sheet 67 / 122 STK60516

68 The two UARTs can run at the same baud rate, using Timer 1 only. If Timer 2 is used for UART0 and Timer 1 is used for UART1, then the two UARTs can run at the same baud rate. Mode bit serial transmission or reception. In this mode, 11 binary bits are transmitted (through P2.7/TXD1) or received (through P2.6/RXD1)). The 11 binary bits are composed of a start bit(1), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit(1). On transmission, the 9th data bit (TB8_1 in SCON1) can be programmed to be 1 or 0. For example, in application, the parity bit P of SFR PSW can be moved into TB8_1 of SCON1. On reception, the 9th data bit goes into RB8_1 of SFR SCON1, while the stop bit is ignored. The baud rate is programmable to be 1/32 or 1/64 of CPU clock frequency, controlled by the setting of SMOD0 bit of SFR PCON or SMOD1 bit of SFR EICON. Mode bit serial transmission or reception. In this mode, 11 binary bits are transmitted (through P2.7/TXD1) or received (through P2.6/RXD1). The 11 binary bits are composed of a start bit (1), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). Actually, Mode 3 is a combination of Mode 2 protocol and Mode 1 baud rate. The baud rate in Mode 3 only comes from Timer 1 overflow Control/Status Register (SFR SCON1) of UART1 The Serial Port Control/Status Register is SFR SCON1, located at address C0H of the SFR memory space. Serial Port Control and Status Register 0, SFR SCON0, AT C0 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Description of SFR SCON1 MNEMONIC BIT POSITION SM0_1 SCON1.7 FUNCTION These two bits are used to select an operation mode. SM1_1 SCON1.6 SM0_1 SM1_1 Modes 0 0 Mode0 0 1 Mode1 1 0 Mode2 1 1 Mode3 SM2_1 SCON1.5 Multiprocessor Communication Enable. In Mode 0, SM2_1 decides the baud rate. When SM2_1 = 0, the baud rate is CPU_CLK*1/12. When SM2_1 = 1, the baud rate is CPU_CLK*1/4. In Mode 1: if SM2_1=1, then RI_1 will be set to high only when a HIGH stop bit has been received. if SM2_1=0, then RI_1 will always be set to high without regard to the state of the received stop bit. In modes 2 and 3, SM2_1 enables the multiprocessor communication feature. SM2_1 is used to disable interrupt to the un-addressed slave receivers, when data bytes are transmitted from the master. Reception Enable. REN_1 SCON1.4 When REN_1=1, UART1 is enabled for reception. When REN_1=0, UART1 is disabled from reception. Data Sheet 68 / 122 STK60516

69 TB8_1 SCON1.3 TB8 is the 9th data bit that will be transmitted in Mode 2 or Mode 3. Set or cleared by software as desired. RB8_1 SCON1.2 In Mode 2 and Mode 3, RB8_1 is the 9th data bit received. In Mode 1, RB8_1 indicates the state of the received stop bit. In Mode 0, RB8_1 is not used. TI_1 SCON1.1 The Transmit Interrupt Flag. This flag can only be cleared by software. In mode 0, this bit is set to logic 1 by hardware at the end of the 8th bit time. In mode 1, mode 2, and mode 3, this bit is set to logic 1 by hardware at the beginning of the stop bit time. RI_1 SCON1.0 The Receive Interrupt Flag. This flag can only be cleared by software. In mode 0, this bit is set to logic 1 by hardware at the end of the 8th bit time. In mode 1, this bit is set to logic 1 after the last sampling of the stop bit, subject to the state of SM2_1. In mode 2, and mode 3, this bit is set to logic 1 by hardware at the last sampling of the stop bit Mode 0 Transmission and Reception of Mode 0 When operating in mode 0, the UART1 is an 8-bit data shift register. Eight bits of data can be shifted into or out from SFR SBUF1, via the P2.6/RXD1 pin. The shifting clock always comes out from the P2.7/TXD1 pin, without regard to if the data is shifted into or out from SFR SBUF1. Baud Rate of Mode 0 In mode 0, the UART1 s baud rate is either CPU_CLK*1/12 or CPU_CLK*1/4, depending on the value of the SM2_1 bit. If SM2_1 = 1, the baud rate (i.e., shifting clock frequency) is CPU_CLK*1/4. If SM2_1 = 0, then the baud rate is CPU_CLK*1/12. Transmission Timing of Mode 0 Data transmission begins when an instruction writes to SFR SBUF1. That is, whenever an instruction with SFR SBUF1 as its destination operand is executed, data transmission will be initiated. The UART1 shifts the data out, LSB first, at the selected baud rate, until all 8 bits of data have been shifted out. Data Sheet 69 / 122 STK60516

70 Write to SFR SBUF1 P2.7/TXD1 P2.6/RXD1 D0 D1 D2 D3 D4 D5 D6 D7 TI_1 RI_1 always low UART1 mode 0 transmission timing when baud rate is CPU_CLK 1/4 Reception Timing of Mode 0 To enable data reception, the REN_1 bit must first be set to logic HIGH. Data reception begins when the RI_1 bit is cleared. Shifting clock is then sent out from the P2.7/TXD1 pin to shift in data, LSB first, until all 8 bits of external data have been shifted in. Each bit of data is shifted in on the rising edge of the shifting clock. Four CPU clocks after the 8th data bit has been shifted in, the RI_1 bit is set to logic HIGH. The RI_1=1 indicates that 8 bits of data have been received. Write to SFR SBUF1 P2.7/TXD1 P2.6/RXD1 D0 D1 D2 D3 D4 D5 D6 D7 RI_1 TI_1 always low UART1 mode 0 reception timing when baud rate is CPU_CLK 1/4 Mode 1 Operation of Mode 1 Mode 1 provides 10-bits, asynchronous, full-duplex transmission or reception. One transmission or reception word is composed of the following bits: One start bit. Eight data bits (D0~D7). One stop bit. Data Sheet 70 / 122 STK60516

71 The 10-bits word format is shown below: START D0 D1 D2 D3 D4 D5 D6 D7 STOP The data bits are transmitted and received LSB first. For receive operations, the received stop bit is stored to the RB8_1 bit of SFR SCON1. Baud Rate of Mode1 Mode 1 baud rate can only be from timer 1 overflow. Data Transmission Timing in Mode1 A data transmission session in mode 1 involves two steps: 1. Application program issues a write to SFR SBUF1. 2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation circuit. 3. The UART1 transmits data out from the P1.1/TXD1 pin in the following order: START bit, data bits (D0~D7), and STOP bit. The START bit is transmitted out first. The TI_1 (SCON1.1) bit of SFR SCON1 is set to HIGH two CPU clocks after the stop bit has been transmitted. TX CLK Internal shift clock P2.7/TXD1 start D0 D1 D2 D3 D4 D5 D6 D7 stop P2.6/RXD1 always high TI_1 RI_1 always low UART1 mode 1 transmission timing Data Reception Timing in Mode 1 A data reception session in mode 1 is as follows: 1. First, the reception function of the UART1 must be enabled by setting REN_1=1 and then the UART1 starts detecting. If there is a falling edge on the P2.6/RXD1 input. For detecting this falling edge, UART1 Data Sheet 71 / 122 STK60516

72 samples the P2.6/RXD1 input pin sixteen times per bit time for any baud rate. 2. When a falling edge on the P2.6/RXD1 pin is detected, the divided-by-16 counter of the baud rate generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 to bit boundaries. 3. For noise rejection, the UART1 decides the value of each received bit by majority decision of three consecutive samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still regarded as HIGH. 4. If the first received bit is not LOW, then the reception session is aborted and the UART1 waits for another falling edge on the P2.6/RXD1 pin. 5. If the first received bit is LOW, then a reception session is initiated and the UART1 continues to receive the following data bits (D0~D7). The bit value is decided by use of majority decision. 6. At the middle of the stop bit time, the UART1 checks the following conditions: a) RI_1 must be LOW. b) If SM2_1 has been programmed to HIGH, then the received stop bit must also be HIGH. (If SM2_1 has been programmed to LOW, the received stop bit can be LOW or HIGH.) 7. If the above conditions are met, then the UART1 moves the received data byte from the temporary Receive Register to SFR SBUF1, moves the received stop bit to the RB8_1 bit of SFR SCON1, and set RI_1 bit to HIGH, triggering an UART1 data reception interrupt. If the above conditions are not met, the received data is ignored and the receive session is aborted. 8. After the middle of the stop bit time, the UART1 continues to wait for another high-to-low transition on the P2.6/RXD1 pin. Data Sheet 72 / 122 STK60516

73 RX CLK (baud rate) P2.6/RXD1 start D0 D1 D2 D3 D4 D5 D6 D7 stop Bit sampling Data shift in clk P2.7/TXD1 always high RI_1 TI_1 always low UART mode 1 reception timing Mode 2 Operation of Mode2 Mode 2 provides 11-bits, asynchronous, full-duplex transmission or reception. A transmission or reception word is composed of the following 11 bits: One start bit. Eight data bits. One programmable 9th bit. One stop bit. The word format is shown below: START D0 D1 D2 D3 D4 D5 D6 D7 TB8_1/RB8_1 STOP The data bits are transmitted and received LSB first. For transmission, the 9th bit is determined by the value in TB8_1. To use the 9th bit as a parity bit, move the value of the P bit of SFR PSW to TB8_1. Baud Rate of Mode 2 In Mode 2, the baud rate is decided by the value of the SMOD0 bit in the SFR PCON. If SMOD0=0, the default value of SMOD0 after reset, the baud rate is CPU_CLK*1/64. That is, the duration of a bit time is 64 CPU clocks. If SMOD0=1, the baud rate is CPU_CLK*1/32. That is, the duration of a bit time is 32 CPU clocks. Data Transmission Timing in Mode 2 A data transmission session in mode 2 involves the following steps: Data Sheet 73 / 122 STK60516

74 1. Application program issues a write to SFR SBUF1. 2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation circuit. 3. The UART1 transmits data out from the P2.7/TXD1 pin in the following order: START bit, data bits (D0~D7), and STOP bit. The START bit is transmitted out first. 4. The TI_1 (SCON1.1) bit of SFR SCON1 is set to HIGH when the stop bit is placed on the P2.7/TXD1 pin. Write to SFR SBUF1 TX CLK Data shift out clk P1.1/TXD1 start D0 D1 D2 D3 D4 D5 D6 D7 TB8 stop P1.0/RXD1 always high TI_1 RI_1 always low UART1 mode 2 transmission timing Data Reception Timing in Mode 2 A data reception session in mode 2 is as follows: 1. First, the reception function of the UART1 must be enabled by setting REN_1=1 and then the UART1 starts detecting. if there is a falling edge on the P2.6/RXD1 input. For detecting this falling edge, UART1 samples the P2.6/RXD1 input pin sixteen times per bit time for any baud rate. 2. When a falling edge on the P2.6/RXD1 pin is detected by UART1, the divided-by-16 counter of the baud rate generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 overflow to bit boundaries. 3. For noise rejection, the UART1 decides the value of each received bit by majority decision of three consecutive samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still regarded as HIGH. Data Sheet 74 / 122 STK60516

75 4. If the first received bit is not LOW, then the reception session is aborted and the UART0 waits for another falling edge on the P2.6/RXD1 pin. 5. If the first received bit is LOW, then a reception session is initiated and the UART1 continues to receive the following data bits (D0~D7). The bit value is decided by use of majority decision. 6. At the middle of the stop bit time, the UART1 checks the following conditions: a) RI_1 must be LOW, b) If SM2_1 has been programmed to HIGH, then the received 9th bit must also be HIGH. (If SM2_1 has been programmed to LOW, the received 9th bit can be LOW or HIGH.) 7. If the above conditions are met, then the UART1 moves the received data byte from the temporary Receive Register to SFR SBUF1, moves the received 9th bit to the RB8_1 bit of SFR SCON1, and set RI_1 bit to HIGH, triggering an UART1 data reception interrupt. If the above conditions are not met, the received data is ignored and the receive session is aborted. 8. After the middle of the stop bit time, the UART1 continues to wait for another high-to-low transition on the P2.6/RXD1 pin. RX CLK P1.0/RXD1 start D0 D1 D2 D3 D4 D5 D6 D7 RB8 stop Bit sampling Data shift in clk P1.1/TXD1 always high RI_1 TI_1 always low UART1 mode 2 reception timing Mode 3 Operation of Mode 3 Mode 3 provides 11-bits, asynchronous, full-duplex transmission or reception. Its transmission or reception word format is composed of: Data Sheet 75 / 122 STK60516

76 One start bit. Eight data bits. One programmable 9th bit. One stop bit. The word format is shown below. It is actually identical to that of Mode 2. START D0 D1 D2 D3 D4 D5 D6 D7 TB8_1/RB8_1 STOP The data bits are transmitted and received LSB first. Mode 3 operation is actually identical to Mode 2 operation, except baud rate. The Mode 3 baud rate generation is identical to Mode 1. That is, Mode 3 is a combination of Mode 2 transmission/reception protocol and Mode 1 baud rate generation. Baud Rate of Mode 3 Mode 3 baud rate can only be from timer 1 overflow. Data Transmission in Mode 3 A data transmission session in mode 3 involves the following steps: 1. Application program issues a write to SFR SBUF1. 2. Transmission begins immediately after the first overflow of the divided-by-16 counter of the Baud Rate Generation circuit. 3. The UART1 transmits data out from the P2.7/TXD1 pin in the following order: START bit, data bits (D0~D7), and STOP bit. The START bit is transmitted out first. 4. The TI_1 (SCON1.1) bit of SFR SCON1 is set to HIGH when the stop bit is placed on the P2.6/TXD1 pin. Write to SFR SBUF1 TX CLK Data shift out clk P2.7/TXD1 start D0 D1 D2 D3 D4 D5 D6 D7 TB8 stop P2.6/RXD1 always high TI_1 RI_1 always low UART1 mode 3 transmission timing Data Sheet 76 / 122 STK60516

77 Data Reception in Mode 3 A data reception session in mode 3 is as follows: 1. First, the reception function of the UART1 must be enabled by setting REN_1=1 and then the UART1 starts detecting. If there is a falling edge on the P2.6/RXD1 input. For detecting this falling edge, UART1 samples the P2.6/RXD1 input pin sixteen times per bit time for any baud rate. 2. When a falling edge on the P2.6/RXD1 pin is detected by UART1, the divided-by-16 counter of the baud rate generation circuit is reset. The output of the divided-by-16 counter is the receiver clock, RX CLK. This action is for aligning Timer 1 to bit boundaries. 3. For noise rejection, the UART1 decides the value of each received bit by majority decision of three consecutive samples in the middle of each bit time. That is, if three consecutive sampled values are 110, then the received bit value is regarded as HIGH. Similarly, if three consecutive sampled values are 101, then the received bit value is still regarded as HIGH. 4. If the first received bit is not LOW, then the reception session is aborted and the UART1 waits for another falling edge on the P2.6/RXD1 pin. 5. If the first received bit is LOW, then a reception session is initiated and the UART1 continues to receive the following data bits (D0~D7). The bit value is decided by use of majority decision. 6. At the middle of the stop bit time, the UART1 checks the following conditions: a) RI_1 must be LOW, b) If SM2_1 has been programmed to HIGH, then the received 9th bit must also be HIGH. (If SM2_1 has been programmed to LOW, the received 9th bit can be LOW or HIGH.) 7. If the above conditions are met, then the UART1 moves the received data byte from the temporary Receive Register to SFR SBUF1, moves the received 9th bit to the RB8_1 bit of SFR SCON1, and set RI_1 bit to HIGH, triggering an UART1 data reception interrupt. If the above conditions are not met, the received data is ignored and the receive session is aborted. 8. After the middle of the stop bit time, the UART1 continues to wait for another high-to-low transition on the P2.6/RXD1 pin. Data Sheet 77 / 122 STK60516

78 RX CLK P2.6/RXD1 start D0 D1 D2 D3 D4 D5 D6 D7 RB8 stop Bit sampling Data shift in clk P2.7/TXD1 always high RI_1 TI_1 always low UART0 mode 3 reception timing Baud Rate Generation for Mode 1 and Mode 3 In both Mode 1 and Mode 3, baud rate is only derived from Timer 1. Figure listed below gives the divider circuit used to derive receiver baud rate and transmitter baud rate from Timer 1 overflow. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of the SMOD0 bit of the SFR PCON, as follows: SMOD Baud rate = 2 32 x Timer 1 overflow rate The Timer 1 interrupt should be disabled in this application. The Timer 1 itself can be programmed for either timer or counter operation in any of its 3 running modes. In most typical applications, it is programmed for timer operation, in the Auto-Reload mode (high nibble of TMOD=0010B). In this case the baud rate is given by the formula: SMOD Baud rate = 2 32 x CPU_CLK x 1 12 x TH1 Timer 1 reload value for UART1 Mode 1 and Mode 3 baud rate. Desired Baud rate SMOD0 (PCON.7) C/T2 (TMOD.6) Timer 1 Mode 33 MHz XTAL1 25 MHz XTAL MHz XTAL Kb/s FDH FEh FFh 19.2 Kb/s F7h F9h FDh Data Sheet 78 / 122 STK60516

79 9.6 Kb/s EEh F2h FAh 4.8 Kb/s DCh E5h F4h 2.4 Kb/s B8h CAh E8h 1.2 Kb/s h 93h D0h Multiprocessor communications Mode 2 supports multiprocessor communication, in which a master transmitter can send data to one or more slave receivers. The 9th data bit is used to indicate an address byte or data byte. When the 9th data bit is HIGH, the transmitted byte is an address byte. When the 9th data bit is LOW, the transmitted byte is a data byte START D0 D1 D2 D3 D4 D5 D6 D7 address /data STOP Master Transmitter Slave Receiver Slave Receiver Slave Receiver TX RX TX RX TX RX TX RX UART1 multiprocessor communication A typical session of multiprocessor communication is as follows: 1. Enable all slave receivers for reception by setting REN_1=1 and clearing RI_1=0. 2. Setting SM2_1=1 for all slave receivers. SM=1 indicates that only an address byte, which has its 9th data bit set to HIGH, can be received by all slave receivers. 3. The master transmitter broadcasts an address byte out. 4. All the UART1s of all slave receivers receive this address byte and interrupt their respective CPU. Data Sheet 79 / 122 STK60516

80 5. All slave receivers execute their UART1 interrupt subroutine. 6. In the interrupt subroutine, the received address is compared with the slave s pre-assigned address. If the two addresses match, then the SM2_1 bit is cleared to LOW. SM2_1=LOW indicates that the 9th bit data bit can be LOW or HIGH. That is, the addressed slave can always receive next transmitted data bytes from the master transmitter. 7. If the received address does not match with the slave s own pre-assigned address, the slave keeps its SM2 bit set to HIGH, indicating that the slave will not be able to receive the next transmitted data bytes. 8. A communication channel is therefore established between the master transmitter and the addressed slave receiver. The master can continue to send data bytes to the addressed slave receiver. All other un-addressed slave receivers can not receive the following data bytes, because their SM2_1 bits remain at HIGH. 9. Once the entire message has been received, the addressed slave sets its SM2_1 bit to HIGH to block further interrupt and waits for the next address byte. Data Sheet 80 / 122 STK60516

81 18. Power-Saving Modes The STK60516 provides two power-saving modes: Idle mode and Stop mode. The bits that control entry into Idle mode and Stop modes are bits 0 (Idle mode) and bit 1 (Stop mode) of the Power Control Register (SFR PCON) at SFR address 87(hex). Table listed below gives a description of the Power Control Register (SFR PCON). Power Control Register (SFR PCON) Bit Mnemonics Function PCON. 7 SMOD0 UART baud-rate double enable. When SMOD0= 1, the baud rate for the UART is doubled. PCON.6~4 Reserved. PCON.3 GF1 General purpose flag 1. Bit-addressable, general-purpose flag for software control. PCON.2 GF0 General purpose flag 0. Bit-addressable, general-purpose flag for software control. PCON.1 STOP STOP mode select. Setting the STOP= 1 places the STK60516 in STOP mode:. PCON.0 IDLE IDLE mode select. Setting the IDLE =1 places the STK60516 in IDLE mode. If the STOP Mode and the Idle Mode are selected at the same time, the STOP Mode has higher priority, as can be obviously seen in Figure listed below. XTAL2 XTAL1 OSC Clock Generator Interrupts, serial port, timers STOP CPU Power-saving modes IDLE Data Sheet 81 / 122 STK60516

82 18.1. Idle Mode Idle mode operation permits the interrupt, serial ports and timers to function while the CPU is halted. The functions that are switched off when the microcontroller enters the Idle mode are: CPU (halted) The functions that remain active during Idle mode are: Timer 0, Timer 1, Timer 2, Watchdog Timer, and RTC UART External/Internal interrupts External reset or power-on-reset. The instruction that sets PCON.0 (=1) is the last instruction executed in the normal operating mode before Idle mode is activated. Once in the Idle mode, the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their current data during Idle mode. There are four ways to terminate the Idle mode: Activation of any enabled interrupt from interrupt sources will cause PCON.0 to be cleared by hardware, terminating Idle mode, but only if there is no interrupt in service with the same or higher priority. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote logic 1 to PCON.0. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. The second way of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for two instruction cycles to complete the reset operation. The third way of terminating the Idle mode is by internal watchdog reset. The fourth way of terminating the Idle mode is by Real Timer Clock. On the other hand, we can switch CPU clock to different clock sources for saving power. The table listed below shows idle current in different situations. XTAL1: 12MHz CHIPCON = 0x1A Voltage: 5V Situation A Situation B Situation C Situation D CPU clock source RC_CLK LDO_CLK RTC_CLK XTAL1 (RC_CLK OFF) (RC_CLK OFF) Idle current 1.624mA 1.12mA 0.813mA 1.925mA Data Sheet 82 / 122 STK60516

83 18.2. Stop mode The instruction that sets PCON.1 is the last executed, prior to going into the Stop mode. Once in Stop mode, the crystal oscillator is stopped. The contents of the on-chip RAM (AUX Memory and Main Data Memory) and the SFRs are preserved. Note that the Stop mode can not be entered when the Watchdog Timer has been enabled. The Stop mode can be terminated only by an external reset (RAM is saved, but SFRs are cleared due to reset). The status of the external pins during Stop mode is shown in Table listed below. In the Stop mode, Vdd supplies to the CPU can be reduced to minimize power consumption. It must be ensured, however, that Vdd is not reduced before the Stop mode is activated, and that the Vdd is restored to its normal operating level before the Stop mode is terminated by hardware reset. The reset signal that terminates the Stop mode also restarts the oscillator. The reset signal should not be activated before Vdd is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset) Status of external pins during power-saving modes Status of external pins during Idle and Stop modes. Mode Memory ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3, PORT 4. internal 1 1 port data port data port data port data port data Idle external 1 1 high-z port data address port data port data internal 0 0 port data port data port data port data port data Stop external 0 0 high-z high-z port data port data port data Summary of Power-saving Modes Summary of power-saving modes Mode Example for enabling the mode Idle ORL PCON, #01H Terminated by Enabled interrupt External hardware reset Watchdog Timer overflow Stop ORL PCON, # 02 H External hardware reset Remarks CPU is gated off CPU status registers maintain their data. Peripherals are active Crystal oscillator is stopped. Contents of on-chip RAM and SFRs are maintained However, leaving Power-Down mode Means redefinition of SFR contents.. Data Sheet 83 / 122 STK60516

84 19. Watchdog Timer Functional Block Diagram The Watchdog Timer is used to reset the STK60516 when it enters into an erroneous state, possibly due to disturbance from external world. Only one SFR (SFR WDT), at SFR map address E1hex) is associated with the Watchdog Timer. Figure listed below gives the functional block diagram of the Watchdog Timer. CPUCLK /256 / bit Programmable Counter RESET EWDT Assuming that XTAL1=24 MHz and CPU CLK is programmed to be equal to XTAL1, then the Watchdog Timer overflow period t can be calculated from the following equation: t 1 = N x x 256 x M Watchdog Timer Control Register The Watchdog Timer Control Register (SFR WDT) is the only SFR associated with the Watchdog Timer. It can be written to or read from, and is described in Table listed below. Watchdog Timer Register WATCHDOG TIMER REGISTER, SFR WDT, AT E1 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics EWDT WDTCLR not implemented WDT2 WDT1 WDT0 Reset value 0 0 x Description of SFR WDT MNEMONIC EWDT (bit 7) WDTCLR (bit 6) FUNCTION Enable Watchdog Timer. Setting EWDT=1 enables the Watchdog Timer. Setting EWDT=0 disables the Watchdog Timer. Setting WDTCLR= 1 clears the Watchdog Timer Programmable Counter and the divided-by prescaler. The Watchdog Timer must be regularly cleared before it overflows. Data Sheet 84 / 122 STK60516

85 WDT2, WDT1, WDT0 (bits 2, 1, 0) These 3 bits decides the overflow period of the Watchdog Timer. The following table gives the overflow period versus the values of these 3 bits, assuming that XTAL1=24 MHz and CPU CLK is programmed to be equal to XTAL1. WDT2 WDT2 WDT2 Overflow interval Notes x seconds x seconds x seconds x seconds x seconds x seconds x seconds x seconds Assuming XTAL1=24MHZ and CPU CLK is programmed to be equal to XTAL1 Data Sheet 85 / 122 STK60516

86 bit Analog-to-Digital Converter (10-bit ADC) ADC functional description The STK60516 has a 10-bit successive approximation ADC with 6 multiplexed analog input channels. ADC channel inputs share with Port 4 pins. Analog input voltage range can be from 0 V to Vdd V. Five SFRs (P4_OPT, ADCSEL, ADCVALH, ADCCLKSEL, and ADCVALL) perform the user software interface to the ADC; see Table listed below for an overview of the ADC SFRs. Figure listed below shows the relation between SFRs and the ADC. Enable ADC P4.5 / ADC5 P4.4 / ADC4 P4.3 / ADC3 P4.2 / ADC2 P4.1 / ADC1 P4.0 / ADC0 SFR P4 OPT SFR ADCSEL 10-bit ADC (SAR type) SFR ADCVALL SFR ADCVALH Bit 9~ Bit 2 Converted binary code are stored in these two registers. Bit 1 ~ Bit 0 Input multiplexer (1) For the LQFP48 package, all the 6 multiplexed input channels are available. (2) For the QFP44 and the PLCC44 packages, ADC4 and ADC5 are not available. (3) SFRs P4_OPT and ADCSEL must be properly programmed to have proper operation of the 10-bit ADC system. (4) Program SFR P4_OPT to configure Port4 pins as either a port pin or an analog input pin. Each pin can be individually programmed. (5) Program SFR ADCSEL to select one channel of the multiplexed 6-channel input. ADC SFRs Data Sheet 86 / 122 STK60516

87 ADC Clock Control Register (SFR ADCCLKSEL), located at B7 (hex) of the SFR memory space. Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value ADCCLKSEL [1:0] ADC Clock select 0 select cpu clock 1 select cpu clock/2 2 select cpu clock/3.. ADC Special Function Registers overview ADDRESS NAME R/W DESCRIPTION D9[hex) P4_OPT R/W Selection of Port 4 pin function. DA(hex) ADCSEL R/W Channel selection. DB(hex) ADCVALH R/W The upper 8 bits of the converted ADC value. DC(hex) ADCVALL R/W The lower 2 bits of tile converted ADC value. B7(hex) ADCCLKSEL R/W Selection of ADC clock. P4_OPT register P4 Option REGISTER, SFR P4_OPT, AT D9 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics ADC5E ADC4E ADC3E ADC2E ADC1E ADC0E Rest Value x x Description of P4_OPT Register BIT SYMBOL DESCRIPTION 5 ADC5E ADC5E= 1 configures pin P4.5/ADC5 as an analog input pin. ADC5E= 0 configures pin P4.5/ADC5 as a port pin (P4.5) 4 ADC4E ADC4E=1 configures pin P4.4/ADC4 as all analog input pin. ADC4E=0 configures pin P4.4/ADC4 as a port pin (P4.4) 3 ADC3E ADC3E=1 configures pin P4.3/ADC3 as an analog input pin. ADC3E=0 configures pin P4.3/ADC3 as a port pin (P4.3) 2 ADC2E ADC2E=1 configures pin P4.2/ADC2 as an analog input pin. ADC2E=0 configures pin P4.2/ADC2 as a port pin (P4.2) 1 ADC1E ADC1E= 1 configures pin P4.1/ADC1 as an analog input pin. ADC1E= 0 configures pin P4.1/ADC1 as a port pin (P4.1) 0 ADC0E ADC0E=1 configures pin P4.0/ADC0 as an analog input pin. ADO0E=0 configures pin P4.0/ADC0 as a port pin (P4.0) ADCSEL register ADC Select REGISTER, SFR ADCSEL, AT DA (HEX) OF THE SFR MAP Data Sheet 87 / 122 STK60516

88 Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics EADC ADCF SADC5 SADC4 SADC3 SADC2 SADC1 SADC0 Rest Value Description of ADCSEL Register Bit SYMBOL DESCRIPTION 7 EADC Enable the ADC. EADC=1 enables ADC. EADC=0 disables ADC. 6 ADCF ADC flag. ADCF=1 conversion is finished. ADCF=0 conversion is not finished. 5 SADC5 SADC5=1 selects analog signal from P4.5/ADC5 pin for conversion. SADC5=0 un-selects this pin. 4 SADC4 SADC4=1 selects analog signal from P4.4/ADC4 pin for conversion. SADC4=0 un-selects this pin for conversion. 3 SADC3 SADC3=1 selects analog signal from P4.3/ADC3 pin for conversion. SADC3=0 un-selects this pin. 2 SADC2 SADC2=1 selects analog signal from P4.2/ADC2 pin for conversion. SADC2=0 un-selects this pin for conversion. 1 SADC1 SADC1=1 selects analog signal from P4.1/ADC1 pin for conversion. SADC1=0 un-selects this pin for conversion. 0 SADC0 SADC0=1 selects analog signal from P4.0/ADC0 pin for conversion. SADC0=0 un-selects this pin for conversion. ADCVALH Register (address DB hex) Bit Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name Upper 8 bits (Bit 9~Bit 2) of the converted binary code. Reset Value ADCVALL Register (address DC hex) Bit Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Name x x x x x x Reset Value Bit 2 Bit 1 Bit 0 Lower 2 bits (Bit 1~Bit 0) of the converted binary code. x x x x x x ADC resolution and characteristics The analog input voltage should be stable when the ADC is enabled to perform conversion. An RC low pass filter may be added to the analog input pins to filter out high frequency noises. The capacitor between an analog input pin and the ground pin should be placed as close to the pins as possible, in order to have maximum effect in minimizing input noise coupling. Figure listed below gives the converted digital value (given in decimal unit) versus input analog voltages. Data Sheet 88 / 122 STK60516

89 Linear curve ADC0_ STEP ADC Timing diagram Because of the STK60516 s ADC architecture, initially we enable the ADC, we have to wait a ADC clock to let the ADC flag (ADCSEL [6]) go down. So the engineer has to add the delay sub routine to your program to wait the ADC flag goes down. Figure listed below shows the ADC Timing diagram. ADC_CLK ADCSEL[7] Have to add delay sub routine in your program to wait the flag goes down. ADCSEL[6] Data Sheet 89 / 122 STK60516

90 21. Programmable Counter Array (PCA) The Programmable Counter Array is composed of five modules. Each module can be programmed to one of six modes except PCA module 0.PCA module has another timer mode. The six modes are as follows: Positive edge capture mode Negative edge capture mode Both positive and negative edge capture mode High Speed Output mode 8-bit PWM 16-bit PWM PCAn_CON[2:0] Function 000 Disable PCA channel Positive edge capture mode 010 Negative edge capture mode 011 Both positive and negative edge capture mode 100 Timer mode(pca 0 only) 101 High Speed Output mode bit PWM bit PWM PCA input clock can be programmed to four modes: CPUCLK CPUCLK /4 CPUCLK /12 External Clock(P1.5) PCA clock select CPUCLK CPUCLK / 4 CPUCLK /12 Mux PCA_EN_REG[7] 16-bit counter (SFR PCA_CNTH + PCA_CNTL) To PCA module 0~4 External Clock PCA_FG_REG[7:6] Data Sheet 90 / 122 STK60516

91 21.2. PCA module 0 Timer mode Only PCA module can be programmed to be Timer mode. In this Timer mode, the PCA0 data register (PCA_DH, PCA_DL) is used for re-reload data. When 16-bit counter (PCA_CNTH, PCA_CNTL) overflows, then PCA will set the flag to 1.If the interrupt enable is set, and then the PCA will inform the STK60516 CPU. The STL60516 CPU will jump to interrupt vector to execute interrupt routine. The Figure listed below explains the procedure. CPUCLK CPUCLK / 4 CPUCLK /12 Mux PCA_EN_REG[7] 16-bit counter (SFR PCA_CNTH + PCA_CNTL) overflow Interrupt to CPU External Clock PCA_FG_REG[7:6] Reload (SFR PCA_DH + PCA_DL) PCA positive edge capture mode The STK60516 will sample GPIO pin from P1.0 through P1.4.If a positive edge transition is detected, the PCA will load 16-bit counter(pca_cnth, PCA,CNTL) to PCA data register(pcan_dh, PCAn_DL).The data in data register reflects the 16-bit counter(pca_cnth, PCA,CNTL) value when transition occurs. Then the PCA will set flag to inform the STK60516 CPU.If Interrupt enable bit is enabled, the STK60516 will jump to interrupt vector to execute interrupt routine. The figure listed below explains the procedure. Data Sheet 91 / 122 STK60516

92 PCAnF Interrupt PCAnE 16-bit counter (SFR PCA_CNTH + PCA_CNTL) P1.0 P1.1 P1.2 P1.3 P1.4 EN PCAn_CON[2:0]=001 PCAn_DH + PCAn_DL PCA negative edge capture mode The STK60516 will sample GPIO pin from P1.0 through P1.4.If a negative edge transition is detected, the PCA will load 16-bit counter(pca_cnth,pca,cntl) to PCA data register(pcan_dh, PCAn_DL).The data in data register reflects the 16-bit counter(pca_cnth,pca,cntl) value when transition occurs. Then the PCA will set flag to inform the STK60516 CPU.If Interrupt enable bit is enabled, the STK60516 will jump to interrupt vector to execute interrupt routine. The figure listed below explains the procedure. PCAnF Interrupt PCAnE 16-bit counter (SFR PCA_CNTH + PCA_CNTL) P1.0 P1.1 P1.2 P1.3 P1.4 EN PCAn_CON[2:0]=010 PCAn_DH + PCAn_DL Both PCA positive edge and negative edge capture mode The STK60516 will sample GPIO pin from P1.0 through P1.4.If a positive edge transition or a negative edge transition is detected, the PCA will load 16-bit counter(pca_cnth,pca,cntl) to PCA data register(pcan_dh, PCAn_DL).The data in data register reflects the 16-bit counter(pca_cnth,pca,cntl) value when transition occurs. Then the PCA will set flag to inform the STK60516 CPU.If Interrupt enable bit Data Sheet 92 / 122 STK60516

93 is enabled, the STK60516 will jump to interrupt vector to execute interrupt routine. The figure listed below explains the procedure. PCAnF Interrupt PCAnE 16-bit counter (SFR PCA_CNTH + PCA_CNTL) P1.0 P1.1 P1.2 P1.3 P1.4 EN PCAn_CON[2:0] = 011 PCAn_DH + PCAn_DL High speed output mode The STK60516 has contains 5 channel PCA. Each PCA can be programmed to High speed output mode. When a match of the PCA counter (PCA_CNTH, PCA_CNTL) and a data register(pcan_dh, PCAnDL)occurs, PCA toggles P1.n. The figure listed below shows the procedure. PCA_D [15:0] (PCA_DH,PCA_DL) PCAnF o o Interrput 16 bit comparator o o PCAnE TOGn register o PCA 16 bit counter (PCA_CNTH,PCA_CNTL) PCAn_CON[2:0] = 101 Update PCA 8-bit PWM mode The STK60516 has contains 5 channel PCA. Each PCA can be programmed to PCA 8-bit PWM mode. These PWMs generate pulses of programmable length within an interval of 256 CPU clocks. When a PWM register (PCAn_DH ~ PCAn_DL) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. All PWMn output pins are driven by push-pull output Data Sheet 93 / 122 STK60516

94 drivers. The figure listed below shows the function diagram of PCA 8-bit PWM mode. Pulse Width Register (SFR PCA0_DL) 8-bit comparator OUTPUT PORT P1.0 8-bit counter (SFR PCA_CNTL) PCA Channel 0 CPU_CLK Pulse Width Register (SFR PCA0_DL) CPU_CLK / 4 CPU_CLK / 8 EXT_CLK 8-bit comparator OUTPUT PORT P1.1 PCA_FG_REG [7:6] 8-bit counter (SFR PCA_CNTL) PCA Channel 1 Pulse Width Register (SFR PCA0_DL) 8-bit comparator OUTPUT PORT P1.2 8-bit counter (SFR PCA_CNTL) PCA Channel 2 Pulse Width Register (SFR PCA0_DL) 8-bit comparator OUTPUT PORT P1.3 8-bit counter (SFR PCA_CNTL) PCA Channel 3 Pulse Width Register (SFR PCA0_DL) 8-bit comparator OUTPUT PORT P1.4 8-bit counter (SFR PCA_CNTL) PCA Channel 4 Data Sheet 94 / 122 STK60516

95 21.8. PCA 16-bit PWM mode The STK60516 has contains 5 channel PCA. Each PCA can be programmed to PCA 16-bit PWM mode. These PWMs generate pulses of programmable length within an interval of CPU clocks. When a PWM register (PCAn_DH ~ PCAn_DL) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. All PWMn output pins are driven by push-pull output drivers. The figure listed below shows the function diagram of PCA 8-bit PWM mode. Data Sheet 95 / 122 STK60516

96 Pulse Width Register (SFR PCA0_DH+PCA0_DL 16-bit comparator OUTPUT PORT P bit counter (SFR PCA_CNTH+PCA_CNTL) PCA Channel 0 CPU_CLK Pulse Width Register (SFR PCA1_DH+PCA1_DL) CPU_CLK / 4 CPU_CLK / 8 EXT_CLK 16-bit comparator OUTPUT PORT P1.1 PCA_FG_REG [7:6] 16-bit counter (SFR PCA_CNTH+PCA_CNTL) PCA Channel 1 Pulse Width Register (SFR PCA2_DH+PCA2_DL) 16-bit comparator OUTPUT PORT P bit counter (SFR PCA_CNTH+PCA_CNTL) PCA Channel 2 Pulse Width Register (SFR PCA3_DH+PCA3_DL) 16-bit comparator OUTPUT PORT P bit counter (SFR PCA_CNTH+PCA_CNTL PCA Channel 3 Pulse Width Register (SFR PCA4_DH+PCA4_DL) 16-bit comparator OUTPUT PORT P bit counter (SFR PCA_CNTH+PCA_CNTL) PCA Channel 4 Data Sheet 96 / 122 STK60516

97 21.9. PCA Control Register PCA_EN_REG Register PCA Enable REGISTER, SFR PCA_EN_REG, AT A1 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA_EN_REG Register Bit SYMBOL DESCRIPTION 7 D7 PCA Counter Enable Control. Set D7 = 0, Disable PCA Counter. Set D7 = 1, Enable PCA Counter. 6 D6 Control the behavior of PCA under Idle Mode Condition. Set D6= 0, enable counting of PCA counter when CPU is under idle mode. Set D6= 1, disable counting of PCA counter when CPU is under idle mode. 5 D5 Unused bit, read as 0. 4 D4 PCA Channel 4 Interrupt Control. Set D4 = 0, Disable PCA4 Interrupt. Set D4 = 1, Enable PCA4 Interrupt. 3 D3 PCA Channel 4 Interrupt Control. Set D3 = 0, Disable PCA3 Interrupt. Set D3 = 1, Enable PCA3 Interrupt. 2 D2 PCA Channel 4 Interrupt Control. Set D2 = 0, Disable PCA2 Interrupt. Set D2 = 1, Enable PCA2 Interrupt. 1 D1 PCA Channel 4 Interrupt Control. Set D1 = 0, Disable PCA1 Interrupt. Set D1 = 1, Enable PCA1 Interrupt. 0 D0 PCA Channel 4 Interrupt Control. Set D0 = 0, Disable PCA0 Interrupt. Set D0 = 1, Enable PCA0 Interrupt. PCA_FG_REG Register PCA Flag REGISTER, SFR PCA_FG_REG, AT A2 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA_EN_REG Register Bit SYMBOL DESCRIPTION 7 D7:D6 PCA clock select. Set D7:D6 = 0 System clock Set D7:D6 = 1 System clock /4 Set D7:D6 = 2 System clock /12 Set D7:D6 = 3 External clock input (P1.5) 5 D5 Unused bit, read as 0. 4 D4 PCA4 Interrupt Flag D4 = 0, represents no Interrupt happen. D4 = 1, represents Interrupt happen. Data Sheet 97 / 122 STK60516

98 3 D3 2 D2 1 D1 0 D0 PCA3 Interrupt Flag D3 = 0, represents no Interrupt happen. D3 = 1, represents Interrupt happen. PCA2 Interrupt Flag D2 = 0, represents no Interrupt happen. D2 = 1, represents Interrupt happen. PCA1 Interrupt Flag D1 = 0, represents no Interrupt happen. D1 = 1, represents Interrupt happen. PCA0 Interrupt Flag. D0 = 0, represents no Interrupt happen. D0 = 1, represents Interrupt happen. PCA_CNTH Register PCA Counter High Byte REGISTER, SFR PCA_CNTH AT A3 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics PCA Counter High Byte Register Rest Value Description of PCA_CNTH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The high byte data of PCA 16-bit counter. The high byte of PCA 16-bit counter. PCA_CNTL Register PCA Counter Low Byte REGISTER, SFR PCA_CNTL AT A4 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA_CNTL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The low byte data of PCA 16-bit counter. PCA0_CON Register PCA channel 0 Control REGISTER, SFR PCA0_CON AT A5 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA0_CON Register Bit SYMBOL DESCRIPTION 7:3 D7:D3 Unused bit, read as 0 Data Sheet 98 / 122 STK60516

99 2:0 D2:D0 PCA0_CON [2:0] mode select PCA0_CON[2:0] Function 000 Disable PCA channel Positive edge capture mode 010 Negative edge capture mode 011 Both positive and negative edge capture mode 100 Timer mode 101 High Speed Output mode bit PWM bit PWM PCA0_DH Register The high byte data of PCA channel 0 Data REGISTER, SFR PCA0_DH AT A6 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA0_DH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The high byte data of PCA0 Data Register. The low byte data of PCA channel 0 Data REGISTER, SFR PCA0_DL AT A7 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA0_DL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The low byte data of PCA0 Data Register. PCA1_CON Register PCA channel 1 Control REGISTER, SFR PCA1_CON AT A9 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA1_CON Register Bit SYMBOL DESCRIPTION 7:3 D7:D3 Unused bit, read as 0 Data Sheet 99 / 122 STK60516

100 2:0 D2:D0 PCA1_CON [2:0] mode select PCA1_CON[2:0] Function 000 Disable PCA channel Positive edge capture mode 010 Negative edge capture mode 011 Both positive and negative edge capture mode 101 High Speed Output mode bit PWM bit PWM PCA1_DH Register The high byte data of PCA channel 1 Data REGISTER, SFR PCA1_DH AT AA (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA1_DH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The high byte data of PCA1 Data Register. PCA1_DL Register The low byte data of PCA channel 1 Data REGISTER, SFR PCA1_DL AT AB (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA1_DL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The low byte data of PCA1 Data Register. PCA2_CON Register PCA channel 2 Control REGISTER, SFR PCA2_CON AT AC (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA2_CON Register Bit SYMBOL DESCRIPTION 7:3 D7:D3 Unused bit, read as 0 Data Sheet 100 / 122 STK60516

101 PCA2_CON [2:0] mode select 2:0 D2:D0 PCA2_CON[2:0] Function 000 Disable PCA channel Positive edge capture mode 010 Negative edge capture mode 011 Both positive and negative edge capture mode 101 High Speed Output mode bit PWM bit PWM PCA2_DH Register The high byte data of PCA channel 2 Data REGISTER, SFR PCA2_DH AT AD (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA2_DH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The high byte data PCA2 Data Register. PCA2_DL Register The low byte data of PCA channel 2 Data REGISTER, SFR PCA2_DL AT AE (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA2_DL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The low byte data of PCA2 Data Register. PCA3_CON Register PCA channel 3 Control REGISTER, SFR PCA3_CON AT AF (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA3_CON Register Bit SYMBOL DESCRIPTION 7:3 D7:D3 Unused bit, read as 0 Data Sheet 101 / 122 STK60516

102 PCA3_CON [2:0] mode select 2:0 D2:D0 PCA3_CON[2:0] Function 000 Disable PCA channel Positive edge capture mode 010 Negative edge capture mode 011 Both positive and negative edge capture mode 101 High Speed Output mode bit PWM bit PWM PCA3_DH Register The high byte data of PCA channel 3 Data REGISTER, SFR PCA3_DH AT B1 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA3_DH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The high byte data of PCA3 Data Register. PCA3_DL Register The low byte data of PCA channel 3 Data REGISTER, SFR PCA3_DL AT B2 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA3_DL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The low byte of PCA3 Data Register. PCA4_CON Register PCA channel4 Control REGISTER, SFR PCA4_CON AT B3 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA4_CON Register Bit SYMBOL DESCRIPTION 7:3 D7:D3 Unused bit, read as 0 Data Sheet 102 / 122 STK60516

103 PCA4_CON [2:0] mode select 2:0 D2:D0 PCA4_CON[2:0] Function 000 Disable PCA channel Positive edge capture mode 010 Negative edge capture mode 011 Both positive and negative edge capture mode 101 High Speed Output mode bit PWM bit PWM PCA4_DH Register The high byte data of PCA channel 4 Data REGISTER, SFR PCA4_DH AT B4 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA4_DH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The high byte of PCA4 Data Register. PCA4_DL Register The low byte data of PCA channel 4 Data REGISTER, SFR PCA4_DL AT B5 (HEX) OF THE SFR MAP Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Rest Value Description of PCA4_DL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 The low byte of PCA4 Data Register. Data Sheet 103 / 122 STK60516

104 22. Serial Peripheral interface (SPI) The STK60516 has one high speed Serial communication interface: The SPI interface. The SPI interface has four features: high speed, full-duplex, synchronous and easy to use. The SPI interface can be programmed to two modes: Master modes and slave modes. There are four pins using in SPI. MOSI (P2.1): In master mode, this pin is spi data output. In slave Mode this pin is spi data input. MISO (P2.0): In master mode, this pin is spi data input.in slave Mode this pin is spi data output. SPICLK (P2.2): In master mode, this pin is spi clock output. In slave Mode this pin is spi clock input. SS (P2.3): In slave mode, this pin is used for chip selection.(slave mode only) Control Registers of SPI SPI Control Register. SPI Control Register ( SFR SPICTL), located at E9(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of SPICTL Register Bit SYMBOL DESCRIPTION 7 SPIEN Enable SPI Function Set SPIEN = 0, Disable SPI Function. Set SPIEN = 1, Enable SPI Function. 6 SPITXD SPI Data start transfer bit Set SPITXD = 0, SPI does not start to transfer. Set SPITXD = 1, SPI does start to transfer. 5 SPIDOR SPI Data Order Set SPIDOR = 0, transmit/receive the MSB of data first. Set SPIDOR = 1, transmit/receive the LSB of data first. 4 SPICPOL SPI clock polarity Set SPICPOL = 0, SPICLK is low when transfer finishes. That means the first transition of clock is the rising edge. It is the leading edge of the clock, and the trailing edge of the clock is the falling edge. Set SPICPOL = 1, SPICLK is high when transfer finishes. That means the first transition of clock is the falling edge. It is the leading edge of the clock, and the trailing edge of the clock is the rising edge. 3 SPICPHA SPI clock phase.(master only) Set SPICPHA = 0, data latch in leading edge, and data changes in trailing edge. Set SPICPHA = 1, data latch in trailing edge, and data changes in leading edge. SPI clock divider. SPICTL[2:0] Baud Rate 000 System clock/8 2:0 D2:D0 001 System clock/ System clock/ System clock/64 Data Sheet 104 / 122 STK60516

105 100 System clock/ System clock/ System clock/ System clock/1024 SPITXDATA Register SPI Transfer Data Register ( SFR SPITXDATA), located at EA(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics SPI Transfer Data Register Reset value Description of SPITXDATA Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 SPI Transfer Data SPIMASTER Register SPI Transfer Data Register ( SFR SPITXDATA), located at EB(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of SPITXDATA Register Bit SYMBOL DESCRIPTION 7:1 D7:D1 Unused bit, read as 0 0 D0 Select Master or Slave mode. Set D0 = 0, Select Slave mode. Set D0 = 1, Select Master mode SPI connection Master Mode STK60516 Master Mode S-25C020A EEPROM MOSI SI MISC SO SPICLK SCK P2.3 / SS /CS GPIO Data Sheet 105 / 122 STK60516

106 Slave Mode STK60516 Master Mode STK60516 Slave Mode MOSI MOSI MISC MISO SPICLK SPICLK P2.3 / SS SS GPIO Master with multiple slaves Master MOSI MISO SPICLK GPIO0 MOSI MISO Slave1 SPICLK SS GPIO1 MOSI MISO Slave2 SPICLK SS SPI Communication The STK60516 s SPI transfer is always initiated by Master. Initially, if SPIEN is set be enabled, and SPIMASTER is set be enabled, the device is selected to Master mode. Then we need to write the data want to be transferred to SPITXDATA register and enable SPITXD bit. The STK60516 s SPI will start to transfer. At the same time,the data in Slave side will be shifted out from MISO and the data in Master side will be shifted in to MOSI. After the transfer finishes, the data on both sides will be interchanged. The Figure of timing diagram listed below will explain the procedure. Data Sheet 106 / 122 STK60516

107 22.4. Timing diagram SPI slave mode with SPICPHA=0 SPI Clock Cycle SPICLK (SPICPOL=1) Driven from Master SPICLK (SPICPOL=0) Driven from Master MOSI (input) Driven from Master SPIDOR =1 SPIDOR =0 LSB MSB 1 6 MOSI turns to output MSB LSB MISO (output) To the master SPIDOR=1 SPIDOR=0 LSB MSB 1 1 MISO turns to output MSB LSB SS pin Driven from Master SPI slave transfer format with CPHA= slave mode with SPICPHA=1 SPI Clock Cycle SPICLK (SPICPOL=1) Driven from Master SPICLK (SPICPOL=0) Driven from Master MOSI (input) Driven from Master MISO (output) To the Master SS pin Driven from Master SPIDOR=1 SPIDOR=0 SPIDOR =1 SPIDOR =0 LSB MSB 1 6 MOSI turns to output MSB LSB LSB MSB MSB LSB MISO turns to output SPI slave mode with CPHA=1 Data Sheet 107 / 122 STK60516

108 SPI master mode with SPICPHA=0 SPI Clock Cycle SPICLK (SPICPOL=1) SPICLK (SPICPOL=0) SPIEN =1 and SPIMASTER =1, MOSI becomes to output data MISO becomes to input data MOSI (output) SPIDOR =1 SPIDOR =0 LSB MSB MSB LSB MISO (input) Driven from the target slave SPIDOR=1 SPIDOR=0 MSB LSB LSB MSB slave SS pin Control GPIO pin by software SPI master mode with CPHA= SPI master mode with SPICPHA=1 SPI Clock Cycle SPICLK (SPICPOL=1) SPICLK (SPICPOL=0) SPEN =1 and MSTR =1, MOSI becomes to output data MISO becomess to input data MOSI (output) SPIDOR =1 SPIDOR =0 LSB MSB MOV SPDAT, #data in software MSB LSB MISO (input) Driven from the target slave SPIDOR =0 SPIDOR =1 LSB MSB MSB LSB slave SS pin Control GPIO pin by software SPI master mode with CPHA=1 Data Sheet 108 / 122 STK60516

109 23. IAP IAP Programming The STK60516 has a total of bytes (64K) of flash memory for user program, but not all user programs completely use up these memory. Un-used flash program memory can be used to stored user data. After power-off, the data remain stored in the flash memory for future use at the next power-on. This function is called In-Application Programming (IAP).The starting address for the flash memory IAP is a cascade of the content of the SFR IAP_ADRH and SFR IAP_ADRL. The overall concept of IAP is illustrated in Figure listed below. The starting address of the flash memory for IAP is a cascade of SFR IAP_ADRH and SFR IAP ADRL.Precautions should be taken to avoid overlap the user program. FFFF(hex) IAP_ADRH IAP_ADRL IAPDATA(E7 Hex) Ocupied by user application program Flash program memory SFRs MAP Data in this register can be programmed to the flash memory. Similarly, data in the flash memory can be read back to this register. 0000(hex) Flash Program Memory IAP function SFRs associated with IAP Four SFRs are associated with the IAP function. They are: SFR IAPEN (E4 hex) SFR IAP_ADRL (E5 hex) SFR IAP_ADRH (E6 hex) SFR IAP_DATA (E7 hex) IAP Enable Control Register ( SFR IAPEN), located at E4(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics IAPEN APROG AREAD AERASE D3 D2 D1 D0 Reset value Data Sheet 109 / 122 STK60516

110 Description of IAPEN Register Bit SYMBOL DESCRIPTION 7 IAPEN Enable IAP Function Set IAPEN = 0, Disable IAP Function. Set IAPEN = 1, Enable IAP Function. 6 APROG Enable Program function Set APROG = 0, Program Procedure does not start. Set APROG = 1, Start to Program the Flash. If this SFR is programmed with , IAPDATA SFR is programmed to the 64K flash memory, starting from the address pointed to by SFR IAP_ADRL and SFR IAP_ADRH. After programming, the address (IAP_ADRH, IAP_ADRL) increases one automatically. 5 AREAD Enable Read function Set AREAD = 0, Read Procedure does not start Set AREAD = 1, Start to Read the Flash. If this SFR is programmed with , the data stored in the flash memory, pointed to by SFR IAP_ADRL and SFR IAP_ADRH, is read back to IAPDATA SFR. After reading, the address (IAP_ADRH, IAP_ADRL) increases one automatically. 4 AERASE Enable Erase function Set AERASE = 0, Erase Procedure does not start Set AERASE = 1, Start to ERASE the Flash. If this SFR is programmed with , 512 bytes of the 64K flash memory is erased, starting from the address pointed to by SFR IAP_ADRL and SFR IAP_ADRH. 3:0 D3:D0 Unused bit, read as 0. IAP Address Low Byte Register ( SFR IAP_ADRL), located at E5(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics Initial low byte address of flash memory for Erase, Programming, and Read. Reset value Description of IAP_ADRL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 IAP Function Low Byte Address IAP Address High Byte Register ( SFR IAP_ADRH), located at E6(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics Initial high byte address of flash memory for Erase, Programming, and Read. Reset value Description of IAP_ADRH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 IAP Function High Byte Address IAP DATA Register ( SFR IAP_DATA), located at E7(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics IAP DATA Reset value Data Sheet 110 / 122 STK60516

111 Description of IAP_DATA Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 This register is used for IAP program and IAP read. Under Programming Condition, the register is stored the data you want to write the flash. Under Reading Condition, this register is stored the data you read from the flash. Data Sheet 111 / 122 STK60516

112 24. Real Time Clock(RTC) Description of Real Time Clock(RTC) The STK60516 has one RTC function. Many applications need Real Time Clock (RTC) and the STK60516 provides this function. RTC can implement in cooperation of software and hardware. If one need low power function, you can switch clock to RTC clock and then turn off other clocks. In this way, the system can maintain basic function and draw very low current SFRs associated with RTC Three SFRs are associated with the IAP function. They are: SFR RTCCTL (F6 hex) SFR RTCSEC (F1 hex) SFR RTCMIN (F2 hex) SFR RTCHOUR (F3 hex) SFR RTCDAYH (F4 hex) SFR RTCDAYL (F5 hex) SFR PRSEC (F9 hex) SFR PRMIN (FA hex) SFR PRHOUR (FB hex) SFR PRDAYH (FC hex) SFR PRDAYL (FD hex) SFR AL_MIN (FE hex) SFR AL_HOUR (FF hex) The procedure of setting RTC At first, we need to know when we will let CPU alarm. For example, if we want to let CPU alarm at 1.00 AM. Initially, we should write 00(hex) to PRSEC (F9 hex) and PRMIN (FA hex) SFR. At the second step we should write 01(Hex) to PRHOUR (FB hex).at the third step, we should enable AL_EN and RTC Interrupt. If RTCSEC (F1 hex) equals PRSEC, RTCSMIN equals PRMIN (FA hex), and RTCHOUR (F3 hex) equals PRHOUR (FB hex), RTC will send interrupt to inform CPU. Then CPU will go to interrupt vector (005B hex) to execute interrupt routine. Data Sheet 112 / 122 STK60516

113 24.4. Control Register Descriptions of RTC RTC Control Register ( SFR RTCCTL), located at F6(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics rtc_out_enable PR_LOAD_CLK_M AL_EN D4 D3 D2 D1 D0 Reset value x x x x x Description of RTCTL Register Bit SYMBOL DESCRIPTION 7 rtc_out_enable rtc_out_enable: control the present second, minute, hour and day registers if can be read out. Set rtc_out_enable = 0, register can t be read out. Set rtc_out_enable = 1, register can be read out. 6 PR_LOAD_CLK_M Software clear bit. Set PR_LOAD_CLK_M = 0, no action. Set PR_LOAD_CLK_M = 1, setting RTC day/hour/min/sec. 5 AL_EN RTC-alarm Function Enable Bit. Set AL_EN = 0, disable RTC-alarm function. Set AL_EN = 1, enable RTC-alarm function. RTC SECOND Register ( SFR RTCSEC), located at F1(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D5 D4 D3 D2 D1 D0 Reset value x x Description of RTCSEC Register Bit SYMBOL DESCRIPTION 5:0 D5:D0 RTCSEC register [5:0] The Register used to show The Present Seconds. RTC MINUTE Register ( SFR RTCMIN), located at F2(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D5 D4 D3 D2 D1 D0 Reset value x x Description of RTCMIN Register Bit SYMBOL DESCRIPTION 5:0 D5:D0 RTCMIN register [5:0] The Register used to show The Present Minutes. RTC HOUR Register ( SFR RTCHOUR), located at F3(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D4 D3 D2 D1 D0 Reset value x x x Description of RTCHOUR Register Bit SYMBOL DESCRIPTION 4:0 D4:D0 RTCHOUR register [4:0] The Register used to show The Present Hours. Data Sheet 113 / 122 STK60516

114 RTC DAY High Byte Register ( SFR RTCDAYH), located at F4(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of RTCDAYH Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 RTC DAY register [15:8] The Register used to show High Byte of The Present DAY. RTC DAY Low Byte Register ( SFR RTCDAYL), located at F5(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of RTCDAYL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 RTC DAY register [7:0] The Register used to show Low Byte of The Present DAY. Alarm Minute Register ( SFR AL_MIN), located at FE(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D5 D4 D3 D2 D1 D0 Reset value x x Description of AL_MIN Register Bit SYMBOL DESCRIPTION 5:0 D5:D0 Alarm_MIN setting register [5:0] The Register used to program The minutes you want to set alarm. Alarm Hour Register ( SFR AL_HOUR), located at FF(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D4 D3 D2 D1 D0 Reset value x x x Description of AL_HOUR Register Bit SYMBOL DESCRIPTION 4:0 D4:D0 Alarm_HOUR setting register [4:0] The Register used to program The Hours you want to set alarm. Program Second Register ( SFR PRSEC), located at F9(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D5 D4 D3 D2 D1 D0 Reset value x x Data Sheet 114 / 122 STK60516

115 Description of AL_HOUR Register Bit SYMBOL DESCRIPTION 5:0 D5:D0 PR-setting SEC time register [5:0] The register used to program RTC seconds. Program Minute Register ( SFR PRMIN), located at FA(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D5 D4 D3 D2 D1 D0 Reset value x x Description of PRMIN Register Bit SYMBOL DESCRIPTION 5:0 D5:D0 PR-setting MIN time register [5:0] The register used to program RTC Minutes. Program Hour Register ( SFR PRHOUR), located at FB(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D4 D3 D2 D1 D0 Reset value x x x Description of PRHOUR Register Bit SYMBOL DESCRIPTION 4:0 D4:D0 PR-setting HOUR time register [4:0] The register used to program RTC hours. Program DAY High Byte Register ( SFR PRDAYH), located at FC(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of PRDAYH Register Bit SYMBOL DESCRIPTION 4:0 D4:D0 PR-setting DAY time high-byte register [15:8] The register used to program RTC High Byte of days. Program DAY Low Byte Register ( SFR PRDAYL), located at FD(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of PRDAYL Register Bit SYMBOL DESCRIPTION 7:0 D7:D0 PR-setting DAY time high-byte register [7:0] The register used to program RTC Low Byte of days. Data Sheet 115 / 122 STK60516

116 25. 6MHz RC Oscillator The STK60516 has a built-in 6MHz RC oscillator. It can be programmed by using the register to control output clock. Initially, 6MHz oscillator can be roughly tuned to get the coarse-wanted clock frequency quickly, and then turn on fine-tune register bit to get accurate clock frequency. For example, if you want to get 3MHz frequency, you should write 38(Hex) to RC_CON0. If you want to get more precise frequency, you can set the RC_CON1 SFR further according to setting table. First, the frequency of 6MHz RC oscillator is designed as 6MHz, 25 degree. But it will vary with temperature. So 6MHz oscillator is not suitable for the application of needing precise frequency Control Registers of 6MHz RC Oscillator RC Control Register ( SFR RC_CON0), located at CE(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D5 D4 D3 D2 D1 D0 Reset value x x Description of RC_CON0 Register Bit SYMBOL DESCRIPTION 5:1 D5:D1 Coarse Frequency adjustment RC_CON0[5:1] is small, the frequency is faster. RC_CON0[5:1] is large, the frequency is slower. 0 D0 Coarse fine tuned Frequency adjustment RC Control Register ( SFR RC_CON1), located at CF(hex) of the SFR memory space Bit Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonics D7 D6 D5 D4 D3 D2 D1 D0 Reset value Description of RC_CON1 Register Bit SYMBOL DESCRIPTION 4 D4 Power-down register. Set D4 =1 Power down the 6MHz RC Oscillator. Set D4 =0 The 6MHz RC Oscillator works. 3 D3 Frequency fine tuning enable register. Set EN_FC =1 Enable the fine-tune function. Set EN_FC =0 Disable the fine-tune function. 2:0 D2:D0 Fine-tuned Frequency adjustment Data Sheet 116 / 122 STK60516

117 25.2. Setting table of 6MHz Oscillator coarse frequency adjustment RCCON0[5:1],D5:D1 Item D0=0 Frequency Item D0=1 Frequency 1 0x00 6.2MHz 1 0x01 6.1MHz 2 0x02 6.1MHz 2 0x MHz 3 0x04 6MHz 3 0x05 6MHz 4 0x06 5.9MHz 4 0x07 5.8MHz 5 0x08 5.8MHz 5 0x09 5.7MHz 6 0x0a 5.6MHz 6 0x0b 5.6MHz 7 0x0c 5.5MHz 7 0x0d 5.4MHz 8 0x0e 5.3MHz 8 0x0f 5.16MHz 9 0x10 5MHz 9 0x MHz 10 0x12 4.7MHz 10 0x13 4.5MHz 11 0x14 4.2MHz 11 0x15 3.9MHz 12 0x16 3.7MHz 12 0x MHz 13 0x18 3MHz 13 0x19 2.7MHz 14 0x1a 2.36MHz 14 0x1b 2MHz 15 0x1c 1.44MHz 15 0x1d 1MHz 16 0x1e 532KHz 16 0x1f 10.5KHz 17 0x20 6MHz 17 0x21 6.1MHz 18 0x22 6.1MHz 18 0x23 6MHz 19 0x24 6MHz 19 0x25 6MHz 20 0x26 5.9MHz 20 0x27 5.8MHz 21 0x28 5.8MHz 21 0x29 5.7MHz 22 0x2a 5.6MHz 22 0x2b 5.6MHz 23 0x2c 5.5MHz 23 0x2d 5.4MHz 24 0x2e 5.3MHz 24 0x2f 5.15MHz 25 0x30 5MHz 25 0x MHz 26 0x32 4.7MHz 26 0x33 4.5MHz 27 0x34 4.2MHz 27 0x35 3.9MHz 28 0x36 3.7MHz 28 0x37 3.4MHz 29 0x38 3MHz 29 0x39 2.7MHz 30 0x3a 2.35MHz 30 0x3b 2MHz 31 0x3c 1.43MHz 31 0x3d 1MHz 32 0x3e 525KHz 32 0x3f 2.6Hz Fine tuning adjustment RC_CLK = 525 KHz Item RC_CON1(D2:D0) RC_CLK KHz KHz KHz KHz KHz KHz KHz KHz Data Sheet 117 / 122 STK60516

118 RC_CLK = 1 MHz Item RC_CON1(D2:D0) RC_CLK MHz KHz KHz KHz KHz KHz KHz KHz RC_CLK = 3 MHz Item RC_CON1(D2:D0) RC_CLK MHz MHz MHz MHz MHz MHz MHz MHz RC_CLK = 6 MHz Item RC_CON1(D2:D0) RC_CLK MHz MHz MHz MHz MHz MHz MHz MHz Data Sheet 118 / 122 STK60516

119 26. Electrical Parameters DC Characteristics Test Condition: Vdd = 5.0V, X1/X2=24MHZ Parameter Symbol Specification Min. Typ. Max. Unit Operating Voltage Vdd V Test Condition Output High Voltage (8051 Std) P1, P2, P3, P4 VIH 4.5 V Vdd = 5.0V Output Low Voltage P0, P1, P2, P3, P4, VIL 0.4 V Vdd = 5.0V Output High Current(strong pull-high for 2 clock cycle) IOH1 4 4 ma Vdd = 5.0V Output High Current(weak pull high) IOH2 160 ua Vdd = 5.0V Output Low Current IOL1 19 ma Vdd=5.0V Input High Voltage VIH 2.7 V 4.5V<Vdd<5.5V Input Low Voltage VIL 1.8 V 4.5V<Vdd<5.5V Operating Current IOP 12 ma Vdd = 5.0V FOSC=24MHz Idle Current IIDLE 1 ma Vdd = 5.0V High speed crystal off, RC off and RTC on Power Down Current IPD 10 ua Vdd = 5.0V Absolute Maximum Ratings Conditions at: Ta= -40 ~ 85 o C, V SS =0V Name Symbol Range Unit Operating Temperature Topg -40 ~ +85 o C Storage Temperature Tstg -25 ~ +125 o C Output Voltage Vout -0.5 ~ V DD +0.5 V Input Voltage Vin -0.5 ~ V DD +0.5 V Operating Conditions Allowable Conditions at: Ta= -40 ~ 85 o C, V SS =0V.(For 5V version) Name Symbol Conditions Min. Max. Unit Supply Voltage V DD 5V system V Operating Freq. Fopg - 32 MHz Data Sheet 119 / 122 STK60516

120 27. Package Outline Drawing PLCC Package Outline Drawing Data Sheet 120 / 122 STK60516

121 27.2. QFP44 Package Outline Drawing Data Sheet 121 / 122 STK60516

122 27.3. LQFP48 Package Outline Drawing Data Sheet 122 / 122 STK60516