Backplane Test Bus Applications For IEEE STD by Clayton Gibbs

Transcription

1 Backplane Test Bus Applications For IEEE STD by Clayton Gibbs Texas Instruments, Inc. Sherman, Texas Abstract Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Providing accessibility and controllability for board testing was simply a matter of probing the board. With the advent of surface mount packaging, the accessibility for probing printed circuit boards began to diminish. Logic cores being integrated onto chips made them inaccessible as well. One of the solutions to address this problem eventually became standardized and is defined in IEEE STD On the printed circuit board level, this standard has become widely used. The classic method of probing boards at accessible test points is still widely used as well, and there are often hybrid test solutions that leverage both bed-of-nails testing and the IEEE STD standard test bus. Decisions for whether or not to use one versus the other are predicated on cost and familiarity with the techniques and architecture. The scope of this paper addresses the application of the IEEE STD test bus standard for system-level applications, which are considered to be systems with multiple printed circuit boards in a backplane configuration. This paper will deal specifically with implementations of IEEE STD in a backplane architecture and compare them with some of the other common methods of backplane testing. 1. Introduction Late in the 1980s, the electronics industry was seeing a need to find alternate solutions to the methods of test being used at the time. The first 1-million transistor processor had just been designed and the time to accomplish a comprehensive functional test proved to be an expensive and time-consuming task. This same complexity was being seen in other chips, as ASICs and programmable logic began to integrate entire sections of glue logic and memory into a single device. Circuit boards necessarily saw quantum steps in complexity as these larger devices were used. In an effort to keep from compromising board space, smaller pitch packaging began to emerge to accommodate these complex devices. Prior to this, the dominance of through-hole packaging of ICs provided easy access to nearly every pin of every chip on a printed circuit board. Providing accessibility and controllability for board testing was simply a matter of probing the board. With the advent of surface mount packaging, the accessibility for probing printed circuit boards began to diminish. Logic cores being integrated onto chips made them inaccessible as well. One of the solutions to address this problem eventually became standardized and is defined in IEEE STD This test bus solution has now become a part of nearly every large-scale integrated device including microprocessors, digital signal processors, and ASICs, enabling them to reap the benefits that the standard provides in testing sections of the chips that would otherwise be inaccessible. Other similar solutions such as BIST are also being used. On the printed circuit board level, this standard has also become widely used. The classic method of probing boards at accessible test points is still widely used as well, and there are often hybrid test solutions that leverage both bed-of-nails testing and the IEEE STD standard test bus. Decisions for whether or not to use one versus the other are predicated on cost and familiarity with the techniques and architecture. The scope of this paper addresses the application of the IEEE STD test bus standard for system-level applications, which are considered to be systems with multiple printed circuit boards in a Backplane configuration. See Figure 1. This paper will deal specifically with implementations of IEEE STD in a backplane architecture and compare them with some of the other common methods of backplane testing. ITC INTERNATIONAL TEST CONFERENCE /03 $17.00 Copyright 2003 IEEE 1115

2 Complete self-test by the system itself is often used in a system that has already been deployed in the field and is usually executed upon power-up of the system. A familiar example would be the power-up test sequence witnessed when a computer is booted up. The system tests its memory, determines its configuration and reports any problems to the user. Figure 1 System Backplane 2. Backplane Test Bus Solution Comparisons Multiple techniques are used in backplanes to accomplish interconnect tests, functional tests, perform field service, and program memories or programmable logic. The method of testing a system is necessarily dependent on the methods used on the sub-systems, PCBs, and the individual ICs and components. For example, if a subsystem made up of mother boards and daughter boards uses an ad hoc test method with rack-and-stack equipment, then a similar type of testing methodology will have to be employed at the system level. The obvious point here is that testing at the system level will need to be part of the plan when designing at the board level. A point in case is that if one desires to execute a built-in self test at the system level, then enabling hardware and software must necessarily be a part of board level design for test (DFT). The common testing methods used at the board level are seldom used for system-level testing. In fact, system-level testing has many parallels to the methods used for testing packaged integrated circuits. The circuit is no longer observable optically and the only access points are external. Dedicated test points have to be brought out to an external access point if they are needed. There are essentially three choices of system-level architecture for test: a complete self-test by the system; injection of test vectors and acquisition of test results using the external connections for the application environment; injection of test vectors and acquisition of test results using a separate test access port. Obviously a fourth method is to use a hybrid of one or more of the three architectures. An example of injecting external test vectors and observing the results using the external system connections for the application environment is the testing of a system that does not have all the peripheral hardware attached. IC manufacturers use this method on simpler devices that do not have any dedicated test access pins. In the case of some programmable logic devices, the application environment pins can be put in a special test mode that permits them to function as test or programming access points. Another example of this would be the testing of an automotive electronic control module. The peripheral hardware is not attached but the module can be tested using the same pins that are used in the application environment. There are multiple examples of the third method, which is injection of test vectors and acquisition of test results using a separate test access port. A separate connection dedicated to test is provided with internal connections to the system to provide accessibility and controllability of the system during test. It is common to see fairly large bundles of wires associated with this method along with multiple connectors. An example of this would be the test access port found on most automobiles manufactured today. The applications fall into three main categories: a) determination of the physical integrity of the assembly process, b) troubleshooting and debug of anomalies during the system assembly process, and c) reconfiguration and upgrading of the system following assembly. 2.1 Determination of Physical Integrity For systems in a backplane architecture, it is assumed that chip-level and board-level tests have already been performed. So the determination of physical integrity focuses on the performance of the system after all boards and modules have been attached to the backplane. It also assumes that the backplane board itself has been similarly tested. This would include connections of PCBs to the backplane, connections of cables to PCBs, applications of jumpers for system configuration, download of firmware to PLDs or memories, etc. See Figure

3 Figure 2 System Components With respect to physical integrity, it is the goal of each of these test architectures to determine whether or not the preceding assembly process was completed successfully. Everything from ohmic resistance of connections to functionality of the system is checked to make sure that the intended configuration was accomplished and that no damage was done in the process. 2.2 Troubleshooting And Debug Of Anomalies Once the physical integrity of the system has been determined, then a choice is made. If the system passes the test, it is ready for use in the application environment or is ready for the next level of assembly. If it does not pass the test, then the system is rejected and must either be scrapped or reworked. If rework is desired, then it is advantageous to know with some degree of certainty what part of the system failed. Each of the test architectures can provide this information. The real challenge is to be able to do this economically and accurately. Some test architectures are less cost effective when troubleshooting and debug are needed. 2.3 Reconfiguration And Upgrade Field failures exact the most significant economic impact on system manufacturers. Upgrades to systems and the ability to reconfigure them almost always lowers the cost of ownership. Life cycles of systems can be extended beyond the debut of the next leap in processor speed and data processing power. New functionality can be added to an existing system, negating the need for redesigns. Workarounds to design flaws can be uploaded to avoid respinning an existing system or to provide a bridge of working product during a new design cycle. 3. IEEE Architectures in Backplane Test Solutions Use of IEEE STD in the system backplane is a natural fit for the last category of system test architecture - injection of test vectors and acquisition of test results using a separate test access port. The test bus consists of a 4-wire, or optional 5-wire access port to inject test vectors and acquire test results. The IEEE STD test bus can be implemented in several different architectures. They include, a) Single Ring Architecture, b) Ring-For-Each Architecture, and c) Multi-drop Architecture. These have evolved with the acceptance of the standard as a test bus solution. The single ring architecture is the simplest to implement. The entire system is linked together into one long daisy chain. See Figure 3. Figure 3 Single-Ring Architecture This architecture is good for fairly small systems, but presents some issues for larger systems. For example, the entire system cannot be tested if even one board is removed from the backplane. Another problem arises when a fault occurs on the first boundary scan test. If one of the scan chains is broken, no information is available about the fault location. The second architecture available is the ring-for-each or star configuration. In this layout, each board would have a separate JTAG ring. This is a definite improvement over the single-ring architecture. It provides access to the rest of the system even when a slot in the backplane is empty. During the testing, it is easier to isolate faults and provides much better troubleshooting ability. The requirement is that the test controller must support multiple rings, or must have an enabling device to map multiple rings to a single primary ring. See Figure

4 Resistance is not expressly measured as with an ohmmeter or voltage versus current test, but instead depends on the resistance of the connections to be acceptable in order for the digital values to propagate through the IR or selected DR (Bypass or Identification) register. Figure 4 Multiple-Ring Architecture The third architecture is the most ideal for the system in a backplane. The multi-drop architecture allows a slot on the backplane to have its own address. Each board on the backplane will need to have an addressable scan port or other multi-drop device to handle the connection to the primary test bus. See Figure 5. At the system backplane level, the scan path integrity test will determine the integrity of the contact between the boards and the physical connectors. The test method is the same, but the vectors injected will be new. This is because no test bus connections between boards have been possible until they are installed in the backplane. So instead of testing connections between devices on a board, the test vectors will target the connections between devices from one board to another. Then the integrity of the physical connections can be determined. The process of performing the scan path integrity test proceeds as follows. Each of the multi-drop scan ports is addressed and data is scanned into and out of the device. A simple scan consists of either an instruction register (IR) scan or a data register (DR) scan. If the expected values are acquired after the scan then the integrity of the test bus interconnects is known to be good. See Figure 6. Figure 5 Multi-Drop Architecture The advantages of the architecture are that each board can be addressed and tested separately, and there is still only one test access port for the entire system driving the primary test bus. If one board is missing, or a fault occurs on the connection to a board, it is fairly easy to identify the location of the fault and even identify the type of fault. 4. IEEE Implementation of Board Interconnect Test in a Backplane 4.1 Scan Path Integrity Test Testing the Tester The first and most important test to implement is the interconnect test for the test bus, sometimes referred to as testing the tester. In the board environment, this checks that all Test Access Port (TAP) pins of all devices are connected to the board with acceptable low resistance and that the configuration is correct. Figure 6 IR/DR Scan Path Integrity Test Some of the problems with the single-ring JTAG architecture begin to be noticed even with this most simple of tests. For example, if we perform testing the tester checkout on a single ring architecture, then if a connection is open or shorted between TDO of one board and TDI of the next board, there is no way to tell which board connection is bad between the two. See Figure

5 Figure 7 Singe-Ring Architecture Fault Troubleshooting the problem will necessitate checking for damage on both boards and ringing out the backplane connectors for both boards. The multiple ring architecture will not have this problem, but only if there is one ring for each board in the backplane. If there is more than one board in one of the scan rings, then the same problem will be encountered as with single ring architecture. The multi-drop architecture can remedy this problem provided there is one multi-drop device such as an Addressable Scan Port (ASP) or Scanbridge for each board in the backplane. If an open or short occurs in the scan chain, then there is only one board to check and one connector to ring out on the backplane. The method of doing this test with an addressable scan port device on the board is different than without one. The Addressable Scan Port (ASP) or Linking Addressable Scan Port (LASP) multi-drop devices incorporate a builtin solution for testing the tester. After test reset (TRST) the test bus state machine is moved to one of several stable states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, or Pause-IR. Then a select protocol followed by an acknowledge protocol is executed on the test bus. Following the receipt of a complete select-protocol sequence, the protocol result in the ASP or LASP is provisionally set to NO MATCH and the connect status of the multi-drop device is set to OFF. The received address and position then are compared to that at the ASP/LASP address (A9 A0) inputs and position (P2 P0) inputs (if it is an LASP), respectively. If these values match, the ASP/LASP immediately (with no delay) responds with an acknowledge protocol transmitted from PTDO. A 10-bit address value, 3-bit position value (if it is an LASP), and 3-bit configuration (if it is an LASP) are encoded into data-one and/or data-zero bit pairs and transmitted. These are, by definition, the same as received in the select protocol. If either the received address or position do not match that at the A9 A0 or P2 P0 inputs, respectively, no acknowledge protocol is transmitted and the linking shadow protocol is considered complete. If the select protocol sent is not acknowledged, then the targeted board or its connection to the backplane has a problem and can be checked out. If the protocol is acknowledged, then a lot of information about the integrity of the connection and the test bus has been acquired. For example, the address pin configuration is correct, the position and configuration bits are correct, and all the JTAG test bus connections to the board are correct. See Figures 8 & 9. Figure 8 ASP/LASP Scan Path Integrity Test 1119

6 Figure 9 This test can be run either as a first test in the system backplane suite of tests or as a diagnostic after a failure occurs in a more global scan path integrity test. In other words, if the first interconnect test does a complete IR or DR scan on the targeted chain, then a first diagnostic after a failure is to run the select and acknowledge protocol as just described. Other multi-drop devices will have to run a short test as described earlier after connection to the test bus has been established. A simple scan consists of either an instruction register (IR) scan or a data register (DR) scan. If the expected values are acquired after the scan then the integrity of the test bus interconnects for that board is known to be good. Now that the primary test bus connections to each board on the backplane are known to be good, further testing of interconnects between boards can continue. 4.2 Backplane Board-to-Board Interconnect Testing Backplane interconnect testing using the IEEE STD test bus is similar to interconnect testing between devices on a board. The difference is that two or more boards must be accessed in order to accomplish the test. Again the multi-drop architecture provides a more elegant solution than the single ring configuration. To begin, all boards are accessed simultaneously using multi-cast addressing and are initialized to the Test-Logic- Reset state by setting TMS high and toggling TCK 5 times. Then the first board (A) that is part of the interconnect test is selected using the multi-drop addressing protocol. A PRELOAD is executed and the first test vector is shifted into the board using a data register scan (DR-Scan). The board is then returned to the Run-Test/Idle state and then deselected. See Figure 10. ASP Select/Acknowledge Protocol Figure 10 Preload Test Vector The second board (B) is then selected and the same procedure followed on it. This continues until all boards that are part of the interconnect test being performed have had the correct vectors shifted into the boundary scan cells and returned to the Run-Test/Idle state. See Figure 11. Figure 11 Preload Test Vector 1120

7 Now, return to the first board (A) and select it. Move it from the Run-Test/Idle state to IR-Scan and load and execute the EXTEST instruction. Stimulus vectors from the board will be output on the BSCs and vectors from other boards will be input on BSCs. Obviously it is important that safe values be input from boards not being addressed at the time. This is taken care of when generating the vectors for the test. Now return the first board (A) to the Run-Test/Idle state and deselect. See Figure 12. Figure 12 EXTEST Select the second board (B) and move it from Run- Test/Idle to IR-Scan. Load and execute the EXTEST instruction followed by a DR-Scan to capture the response to the vectors from the first board. The response is shifted out while in Shift-DR state. The board (B) should then be left in Pause-DR to avoid over-writing the safe values that were simultaneously output during the EXTEST instruction. See Figure 13. All other boards that are part of the interconnect test need to be selected and the response to the vectors from the first board shifted out just as with the second board. The preceding sequence is repeated for every vector in the interconnect test for the first board. The next board is then loaded with vectors to test remaining interconnects not tested by the first board and so on until all interconnect testing of the system is complete. This flow is not the only implementation that will work. Other schemes may be used as well depending on the IEEE STD multi-drop devices being used and the test bus controller. 5. Hardware Support for Implementing IEEE in a Backplane Several devices are available across the industry for enabling system backplane testing using IEEE STD They include test bus controllers, IEEE STD compliant devices, scan path linkers, and multidrop gateway devices. IEEE STD compliant devices are quite prevalent, especially in larger ICs such as microprocessors, DSPs, FPGAs, larger PLDs, and ASICs. In addition there are a host of enabling logic devices with Boundary Scan on board. Test bus controllers are available in many architectures ranging from software to dedicated integrated circuits. The most important enabling device for systems in a backplane is probably a multi-drop device. These are available from Texas Instruments, National Semiconductor, Firecron, and IP modules from Intellitech. Each of these function in a similar fashion but are certainly not drop-in replacements for each other. They include the following devices in Table 1. Figure 13 Scan Out Results 1121

8 Device Vendor Nickname Description SN74ABT8996 SN74LVT8996 Texas Instruments Addressable Scan Port - ASP Multi-Drop Device for linking a secondary scan path to the primary scan path SN74LVT8986 Texas Instruments Linking Addressable Scan Port -- LASP Multi-Drop Device that merges the functionality of the SPL and the ASP for linking 1-24 scan paths to the primary scan path SCANSTA111 National STA111 Multi-Drop Device for linking 1-3 SCANSTA112 Semiconductor National Semiconductor STA112 secondary paths to the primary scan path Multi-Drop Device that merges the functionality of the STA110 and STA111 for linking 1 7 secondary paths to the primary scan path JTS03 Firecron LTD JTS03 Multi-Drop Device that selects 0 3 scan paths to the primary scan path JTS06 Firecron LTD JTS06 Multi-Drop Device that selects 0 6 scan paths to the primary scan path Table 1 Multi-Drop Devices 5.1 Test Bus Control Control of the test bus can be accomplished either within the system itself or remotely. If it is to be controlled within the system, then the test bus controller can either reside on one of the boards on the backplane or on the backplane itself. In a passive backplane architecture the test bus controller resides on one of the boards in the backplane. It is also possible for all boards in the backplane to have a test bus controller resident on each of them. See Figures 14 & 15. Figure 15 Passive Backplane With Per Board Test Control In an active backplane, the test bus controller resides either remotely or on the backplane itself. This configuration is more robust for implementing a multidrop architecture. See Figure 16. Figure 14 Passive Backplane With One Test Control Board Figure 16 Active Backplane 1122

9 5.2 Multi-Drop Devices The multi-drop devices evolved from the older scan path linkers that allowed secondary scan paths to be included with or excluded from the primary scan path. These devices provided great flexibility for programming flash memory, accessing daughter boards, etc. The scan path linkers themselves, however, could not be removed from the primary scan path. So if a board with a scan path linker is removed from the backplane, the primary scan path is broken and no testing can be done using the IEEE STD test bus. The multi-drop devices overcame this limitation using addressing protocol schemes and making them reside in a parallel architecture on the test bus. The ASP hybrids such as the NSC STA112 and Texas Instruments SN74LVT8986 (LASP) combine the functionality of the scan path linkers and the multi-drop functionality into a highly configurable and flexible test bus architecture. Their applications in the system backplane architecture are supersets of their use during board test. It allows reuse of tests already done at the board level, reducing the amount of test design time, and the size and complexity of the test hardware needed for system level test, debug, and system updating or reconfiguring Overcoming Long Scan Chains One of the primary advantages of the multi-drop architecture in the system backplane is the reduction in the length of scan chains and the resulting length of a single test. For example, a scan chain can only be clocked at the speed of the slowest JTAG enabled part in the scan path. A high-density board with multiple high-pin-count devices will have a scan chain that is quite long. The vectors can only be scanned through the chain at the speed of the slowest device. It is advantageous to break it up into sections that will optimize the amount of time required to complete the tests. A multi-drop device that can selectively link secondary scan paths to the chain will provide this flexibility without adding more devices. See Figure 17 Figure Programming Flash Memory and CPLDs The IEEE STD test bus, initially the domain of board test, has seen increasing popularity among programmers of CPLDs and Flash Memories. This trend is further enabled by the advantages of a multi-drop device on a printed circuit board. Use of an LASP or STA112 multi-drop device allows access and control of the scan chains with fewer partitioning devices. Without the use of an LASP or similar device to partition a board, all other devices in the chain are placed in BYPASS or CLAMP mode in order to shorten the chain and to allow safe values to be held on their outputs. The programming ASIC is moved to EXTEST mode to prepare for the flash programming process. LASP Function Example Without a partitioning device, the speed of the programming is tied to the slowest TCK frequency of the slowest device in the scan chain. This constraint may violate the specifications for programming time on the flash memory. A multi-drop device on the board allows two solutions. First of all, it allows addressing of only one board on the backplane for application of the programming vectors. In addition a hybrid multi-drop device like the LASP enables further partitioning of the same board to select only the scan chain with the flash memory. This scan chain can be designed to include JTAG devices that have acceptable TCK timing, eliminating the constraints introduced by slower devices. See Figure

10 The advantages for board level programming of flash memory and PLDs is at once extended to the system in a backplane. Tremendous advantages and cost savings are realized here, since it is possible to reconfigure the functionality of firmware in the field to address problems not identified prior to deployment of the entire system. This ability also extends the life of systems by providing feature upgrades to the system in situ. No replacing boards or swapping components is needed for many upgrades or new system configurations Accessing Daughter Boards When a daughter board is attached to a motherboard, it is necessary to have some way to access it if one wishes to test its connections during system-level test. Without a partitioning device of some kind, the motherboard cannot be tested unless the daughter board is connected to it. A scan path linker could be added to the motherboard to facilitate this. The SPL must be resident on the motherboard, not on the daughter board, or the same conditions will exist as if there were no partitioning device, i.e., no daughter board, no JTAG test capability. A multi-drop device on the motherboard provides a more elegant solution. See Figure 17. Here the daughter board scan chain can be connected to the primary scan chain via the multi-drop device, with no other partitioning devices needed. It should be noted that this configuration provides much finer resolution of diagnostics during system backplane testing. A short or open in the connection between the motherboard and daughter board can be detected and the proximity of the fault determined before removing the boards from the system Diagnostics Perhaps the most valuable advantage of using multi-drop devices on boards in a backplane is the ability that it provides for diagnostics either at system level test or when the system is deployed in the field. It provides a number of advantages that are more difficult to obtain with other methods of system test and the associated diagnostics. First of all it enables a system to be partitioned into manageable blocks so that a fault can be found more quickly and with greater accuracy. All tests may not have to be run to determine a properly functioning system. Should a test fail, however, the full suite of tests can be leveraged to bound the fault. Secondly, multi-drop devices allow test cost reduction by eliminating tests with very low failure rates. For example, if a particular connection on a board has never failed and the defective parts per million (DPPM) is below an acceptable level, the test may be eliminated if the functionality of the system would detect it otherwise. Conversely, if a connection on the backplane has proven to be chronically problematic, it may be necessary to add a test on the scan chain that supports the test of that connection. A third advantage of multi-drop devices is the ability to reuse JTAG tests that were already being used at the board level, or even the chip level. This reusability is especially valuable because many tests that are run in the factory using JTAG testing can also be run in the field to diagnose failures. There will then be apples-to-apples correlation when comparing field failures to factory failures using the same test. 6. Design Support for Implementing IEEE in a Backplane Devices with a boundary scan register and the associated state machine are almost always provided with a description of the boundary scan functionality. Known as BSDL (Boundary Scan Description Language) files, these are provided for use in design of printed circuit boards and systems when IEEE test is designed in. Most test bus controllers and scan support devices do not have a boundary scan register, so no BSDL file is appropriate for these devices. Instead the functionality is written into a file similar to an HDL file that provides designers with functional descriptions of the device. The boundary-scan tools used for test generation and application must support the devices used to select a specific scan path configuration. The tools must know the scan path configuration to generate the tests, and must make sure the scan path is properly configured before applying the tests. Firms such as ASSET InterTech, JTAG Technologies, Corelis, and Goepel generate these files and provide design support. Support for each device type must be created individually. A file is created that describes all the boundary-scan characteristics of the device as well as the methods used to control scan path selection. This file is then provided the test development tools. The file is used as part of the scan path description created for the board or backplane. Based on this file, the tools know how to communicate with the device to configure the scan path. Before a test can be generated, the tools must know the exact number of bits in the scan path. The test development tool manages this by using preconditioning to establish the scan path configuration during test generation. All test and programming operations are encapsulated and includes all the information necessary to apply the action, including the preconditioning that sets up the scan path configuration. In this way, the development tool ensures that the same scan path configuration is used 1124

11 to apply the test as was used to generate the vectors. The actions can be run individually during prototype debug or as part of a test sequence during manufacturing tests. Actions that do nothing but control the scan path configuration can also be created to set the board or backplane in a static configuration while tests without preconditioning are run. Support for the devices being used by the boundary-scan tool must be a primary consideration during the board or system design stages. Although these functions can be designed into PLDs or ASICs in-house, it is not usually possible to find commercially available tools to support them. Using off-the-shelf devices, or commercially available IP to design them into ASICs will save a lot of trouble and expense in the long run. 7. Case Study A multi-function display unit designed and manufactured by BAE Systems, Edinburgh, was designed with the IEEE test bus architecture. The block diagram for this system is shown in Figure 18. The system incorporated a power supply and three printed circuit boards (PCBs): a control board, a video board and an interface board. Figure 18 Multi-Function Display System The video board contained multiple CPLDs, an FPGA, and Flash Memory. Its function was to receive digital video and control data, buffer and process it, and drive the LCD display. The control board contained a microcontroller, CPLDs, FPGAs, Flash Memories, SRAM, EEPROM, a UART, a power supply, and various integrated and discrete analog devices including ADCs. This board also provided status indicators such as LEDs, and received inputs from switches, potentiometers, keyboards, and sensors. Its function was to receive and process input from the external links and the interface PCB. It also processed panel inputs from its own physical interface. The interface board contained an FPGA, a CPLD, and EEPROM. Its function was to provide an interface to the video display card and an analog video screen. It processed digital video data and output various video formats for display. To implement IEEE STD , each of the boards was constrained to use the same pin-out for test during the 1125

12 design. The adapter for each board provided power for the board and contained the IEEE STD Test Access Port (TAP) pins. Board test included both roving probe (sometimes called flying probe ) and scan testing. The scan tests were matched with the roving probe tests so that there was no duplication of the tested nets. Each board also had a multi-drop device, in this case, the Addressable Scan Port (ASP) from Texas Instruments. The use of this device allowed the extension of scan access and testing from the board level to the system level. An added cost saving was realized by reusing the board level tests at the system level. The addressing scheme for the ASP used a 10-bit address that identified a specific board during system-level test, allowing a direct connection of the secondary scan chain to the primary scan chain. In addition, the optional Bypass addressing scheme provided the capability to force a primary to secondary connection without the need for addressing. The ~CON pin, indicating the status of the primary to secondary connection, can also be used for local control on the board. The ASP devices also have a high output drive that supported the backplane interface well and provided high fan-out on the secondary scan chain. 7.1 Success Stories in this Case Study The advantages in field diagnostics and testing have already been highlighted in this paper. One of these advantages played out well in a field failure with the BAE Systems multi-function display system. The system identified a programming error in the firmware while in the field. Forty of these systems were already deployed and all of them had the same problem. If the board were removed from the system and reprogrammed to reconfigure the system, then a full factory test would have to be executed taking over six hours. The use of the system level IEEE STD test bus provided a quick solution for reconfiguring the system without removal of a single board. Another success story where the system level IEEE STD test bus proved valuable happened when it became necessary to modify the contents of the flash memory on one of the cards. The goal was to modify the contents of the flash memory without removing the covers on the box around the system. The solution was quite simple and involved the connection of the system test bus to a laptop computer. The initial attempt was successful, but was taking an inordinate amount of time to complete (greater than 80 minutes for only part of the flash memory) because the parallel port on the computer was being used and it ran at only 1 MHz. So a PC with a PC-AT card was used, cutting the programming time down to something more manageable, around 6 1/2 minutes. 7.2 Lessons Learned External Clock Disable Signal BAE Systems engineering found it advantageous to also bring out a master oscillator disable signal along with the TAP. The purpose of this signal line was to kill all the CPU clocks on the board under test in order to prevent the unit under test (UUT) from powering up into an operational mode. In many cases a signal named 'Ground Test' was also brought out to ensure that any test mode would only be available on the bench and not in the application environment mode. See Figure

13 Figure 19 Multi-Function Display System Test Bus TAP Signal Buffering Buffering of the TAP signals, both inputs and outputs, on a board is advantageous. Backplanes tend to be noisier due to the longer signal traces. The buffers keep the signal noise from affecting the devices on the board. The ASP device from Texas Instruments did not require buffering because the drive capability was high enough to provide adequate fan-out and to drive the signals onto the backplane Addressable Scan Port Address Usage In systems where more than one instance of a particular PCB is to be installed and it is necessary to have the ability to address one of these boards, the ASP address needs to be related, at the system level, to its position in the system. For this BAE Systems has now assigned the top 5 bits (of 10) of the ASP addresses to be locked to the card position on the backplane. These bits are hardwired on the backplane board. The actual card address, for module test, will use the lower 5 address bits for individual cards. These bits are hardwired on the card. Backplane Position Table 2 Board Address System ASP Address Card Type A A B BAE Systems Addressing Scheme This example shows three PCBs of two different types, inserted into the same backplane. At module/factory level there are two tests, but when in the system there are three tests. Here the ASP address is the only difference between system-level test and the factory test. This concept can also apply to daughter boards, as BAE Systems has also implemented the ASP on daughter boards. In addition this can also be used as a simple system configuration test to verify the position of PCBs. This is done by using the ASP 'scan' feature and returns a list of all ASP addresses that are found ASP on the Backplane Board In retrospect, the BAE Systems engineer felt that locating the ASP on the backplane might be a good idea although 1127

14 the idea met with some resistance. The advantage would be the ability to plug a board with a different configuration into the same socket, leaving the board address the same in the ASP addressing scheme. 8. Summary and Conclusions The introduction of multi-drop devices has enabled the extension of the IEEE STD test bus to the system level. There are many advantages to this test solution versus others. They include reusability of tests, in situ reconfiguration of firmware, identical test correlation from the factory to the field, significant reduction in the size of test hardware and software, and significant reduction in test time. Perhaps one of the most significant advantages, however, is the ability to debug and diagnose a failure. The test bus provides accessibility that cannot be obtained with the same cost model in other system test methodologies, and the multi-drop architecture provides the flexibility to partition the system during test and debug, simplifying the process of identifying and defining a failure. 9. Acknowledgements Information for this paper was provided by the following people: Ken Williams, Texas Instruments Rakesh Joshi, Texas Instruments Jim Webster, BAE Systems R.G. Bennetts, Bennetts Associates Dave Bonnett, ASSET InterTech 10. References [1] J.Doe & M.Jones, Measuring Interesting Waveforms with Novel Techniques, Proceedings IEEE International Test Conference, 1999, pp [1] Rick Nelson, PCB Test: Nails or TAP?, Test & Measurement World, 9/1/2002 [2] Dan Romanchik, A Board Test Tutorial, Test & Measurement World, 7/1/1994 [3] David Bonnett, IEEE STD Yields New Standards, Test & Measurement World, 4/1/2002 [4] T. Marosvolgyi, H. Tietze, & T. Wenzel, Flying Probe and Boundary Scan Testers Unite, Test & Measurement Europe, 8/1/1999 [5] David Rolince, Extend The Frontiers Of Boundary- Scan Test, Test & Measurement World, 2/1/2001 [6] Structural System Test via IEEE Std with Hierarchical and Multi-drop Addressable JTAG Port, SCANPSC110F, AN-1023, [7] SN74ACT8990 Data Sheet, Texas Instruments; [8] SN74LVT8980A Data Sheet, Texas Instruments; [9] SN74LVT8996 Data Sheet, Texas Instruments; [10] SN74LVT8986 Data Sheet, Texas Instruments; [11] Cascading Multiple-Linking Addressable-Scan-Port Devices, Application Report SCTA056 - November 2002, [12] SN74ABT8996 Data Sheet, Texas Instruments; [13] SCANSTA111 Data Sheet, National Semiconductor; [14] JTS03 Data Sheet, Firecron; pdf [15] JTS06 Data Sheet, Firecron; pdf [16] SN74ACT8997 (Scan Path Linker) Data Sheet, Texas Instruments; [17] Intellitech JTAG IP,