Testing And Testable Design of Digital Systems

Transcription

1 بسم الله الرحمان الرحیم Testing And Testable Design of Digital Systems College of Electrical Engineering Iran University of Science and Technology Karim Mohammadi Faut-Tolerant Digital System Design week-1 ۱

2 Course Outline Part I: Introduction Basic concepts and definitions (Chapter 1) Test process and ATE (Chapter 2) Test economics and product quality (Chapter 3) Fault modeling (Chapter 4) VLSI Test: Lecture 1 ۲

3 Course Outline (Cont.) Part II: Test Methods Logic and fault simulation (Chapter 5) Testability measures (Chapter 6) Combinational circuit ATPG (Chapter 7) Sequential circuit ATPG (Chapter 8) Memory test (Chapter 9) Analog test (Chapters 10 and 11) Delay test and IDDQ test (Chapters 12 and 13) VLSI Test: Lecture 1 ۳

4 Course Outline (Cont.) Part III: DFT Scan design (Chapter 14) BIST (Chapter 15) Boundary scan and analog test bus (Chapters 16 and 17) System test and core-based design (Chapter 18) VLSI Test: Lecture 1 ٤

5 References: 1 - Digital Systems Testing and Testable Design Miron Abramovici Melvin A. Breuer Arthur D. Friedman IEEE PRESS ISBN Fault-Tolerant Computer System Design Dhiraj K. Pradhan Prentice Hall ٥

6 3 - Essentials of Electronic Testing For Digital, Memory and Mixed- Signal VLSI Circuits Michael L. Bushnell Vishwani D. Agrawal Kluwer Academic Publisher Boston/ Dordrecht/London 4- Appendix C : Books On Testng Faut-Tolerant Digital System Design week-1 ٦

7 Lecture 1 Introduction VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device - system-on-a-chip Course outline Part I: Introduction to testing Part II: Test methods Part III: Design for testability VLSI Test: Lecture 1 ۷

8 VLSI Realization Process Customer s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer VLSI Test: Lecture 1 ۸

9 Faults, Errors, Failure VLSI Test: Lecture 1 ۹

10 Definitions Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. VLSI Test: Lecture 1 ۱۰

11 Testing During VLSI Development Design verification targets design errors Corrections made prior to fabrication Remaining tests target manufacturing defects 11 A defect is a flaw or physical imperfection that can lead to a fault Design Specification Design Fabrication Packaging Quality Assurance Design Verification Wafer Test Package Test Final Testing

12 Design Verification Different levels of abstraction during design CAD tools used to synthesize design from RTL to physical level Simulation used at various level to test for Design errors in behavioral or RTL Design meeting system timing requirements after synthesis Design Specification Behavioral (Architecture) Level Register-Transfer Level Logical (Gate) Level Physical (Transistor) Level 12

13 Electronic System Manufacturing A system consists of PCBs that consist of VLSI devices PCB fabrication similar to VLSI fabrication Susceptible to defects Assembly steps also susceptible to defects Testing performed at all stages of manufacturing PCB Fabrication PCB Assembly Unit Assembly System Assembly Bare Board Test Board Test Unit Test System Test 13

14 Verification vs. Test Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design. Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices. VLSI Test: Lecture 1 ۱٤

15 Problems of Ideal Tests Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open problem. VLSI Test: Lecture 1 ۱٥

16 Real Tests Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. VLSI Test: Lecture 1 ۱٦

17 Testing as Filter Process Good chips Prob(good) = y Prob(pass test) = high Mostly good chips Fabricated chips Defective chips Prob(bad) = 1- y Prob(fail test) = high Mostly bad chips VLSI Test: Lecture 1 ۱۷

18 Yield= Number of acceptable parts Total number of parts fabricated Defect Level= Number of faulty parts passing final test Total number of parts passing final test Fault coverage= Number of detected faults Total number of faults Fault detection effeciency= Number of detected faults Total number of faults number of undetectable faults ۱۸

19 Costs of Testing Design for testability (DFT) Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost VLSI Test: Lecture 1 ۱۹

20 Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. bus PI Logic block A Logic block B PO Test input Test output VLSI Test: Lecture 1 ۲۰

21 Purpose of Manufacture Testing Verify Manufacture of Circuit Improve System Reliability Diminish System Cost Cost of repair goes up by an order of magnitude each step away from fab line 1000 ost Rule of 10 It costs 10 times more to test a device as we move to higher levels in the product manufacturing process Cost per fault (Dollars) IC Test Board Test System Test Warranty Repair VLSI Test: Lecture 1 ۲۱

22 Testing and Quality ASIC Fabrication Yield: Fraction of good parts Testing Rejects Shipped Parts Quality: Defective parts per million (DPM) * Quality of shipped part is a function of yield Y and the test (fault) coverage T. VLSI Test: Lecture 1 ۲۲

23 Fault Coverage * Fault coverage T is the measure of the ability of a set of tests to detect a given class of faults that may occur on the device under test. T = # of detected faults # of possible faults VLSI Test: Lecture 1 ۲۳

24 Defect Level * Defect Level, DL is the fraction of the shipped parts that are defective. DL = 1 - Y (1-T) Y: yield T: fault coverage VLSI Test: Lecture 1 ۲٤

25 Relating Defect Level to Fault Coverage Y=.01 Y=.10 Y=.25 DL = 1 - Y (1-T) Y = Yield Y=.50 Y=.75 Y=.90 Y= Fault Coverage, T (%) VLSI Test: Lecture 1 ۲٥

26 Defect Level, Yield and Fault Coverage Yield Fault Coverage DPM 50% 90% 67,000 75% 90% 28,000 90% 90% 10,000 95% 90% 5,000 99% 90% 1,000 90% 90% 10,000 90% 95% 5,000 90% 99% 1,000 90% 99.9% 100 VLSI Test: Lecture 1 ۲٦

27 Scan Flip-Flop (SFF) D TC Logic overhead Master latch Slave latch Q SD MUX Q CK D flip-flop VLSI Test: Lecture 23 ۲۷

28 Adding Scan Structure PI PO Combinational logic SFF SFF SCANOUT SFF TC or TCK SCANIN Not shown: CK or MCK/SCK feed all SFFs. VLSI Test: Lecture 23 ۲۸

29 System Test Logic Teat data Input Serial Input to boundry register Test Clock For boundry Scan Test Data Otput Test Mode Selet signal Asyncronous Reset For Boundry Scan Test acess port : finite state machine that recognizes the boundry scan communication protocol and controls the operation through internal signals Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28 29

30 DFT Standards IEEE Std IEEE Std b IEEE Std IEEE Std MIL-HDBK-XX47 VLSI Test: Lecture 1 ۳۰

31 IEEE Std Test Access Port and Boundary- Scan Architecture Defines the architecture of the TAP and Boundary Scan cells IEEE b - defines the Boundary-Scan Description Language (BSDL) IEEE Std. P Extended Serial-Digital Interface Standard Defines a scheme that supports board-level interconnect testing and internal-scan testing of components IEEE Std. P Real Time Test Bus Standard Proposed to define standards for real-time testability bus (work discontinued) VLSI Test: Lecture 1 ۳۱

32 IEEE Std. P Mixed-Signal Test Bus Standard Proposed to extend the concept of boundary-scan to analog and mixed signal devices IEEE Std. P Module Test and Maintenance Bus Standard Defines specifications for a serial test and maintenance bus for systems with two or more modules plugged into a backplane IEEE Std Waveform and Vector Exchange Specification (WAVES) Defines standard for VHDL description of stimulus vectors and responses MIL-HDBK-XX47 Testability Analysis Handbook VLSI Test: Lecture 1 ۳۲

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34 Cost of Manufacturing Testing in GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second VLSI Test: Lecture 1 ۳٤

35 Roles of Testing Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT. VLSI Test: Lecture 1 ۳٥

36 A Modern VLSI Device System-on-a-chip (SOC) Data terminal DSP cor e Interface logic RAM ROM Mixedsignal Codec Transmission medium Figure 18.5 (page 605) VLSI Test: Lecture 1 ۳٦

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38 چالشهاي آزمون SOC ها گستردگي و تنوع در طراحي و تحقق فرآیند آزمون كنترل پذیري رویت پذیري و دسترسي آزمون حجم اطلاعات آزمون ظرفیت كانال آزمونگر مدت زمان آزمون بلوك ھاي بنیادي نامتجانس انجام آزمون در سرعت كاري اتلاف توان در فرآیند آزمون