BTeV at C0. p p. Tevatron CDF. BTeV - a hadron collider B-physics experiment. Fermi National Accelerator Laboratory. Michael Wang

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1 BTeV Trigger BEAUTY th International Conference on B-Physics at Hadron Machines Oct , 2003, Carnegie Mellon University, Fermilab (for the BTeV collaboration)

2 Fermi National Accelerator Laboratory BTeV - a hadron collider B-physics experiment Tevatron BTeV at C0 CDF D0 p p

3 BTeV detector in the C0 collision hall

4 BTeV detector RICH SM3 Magnet Straws & Si Strips Muon EM Cal 30 Station Pixel Detector

5 Si pixel detector 50 µm 14,080 pixels (128 rows x 110 cols) Multichip module sensor module 1 cm 400 µm Si pixel sensors 10 cm 5 cm Wire bonds 128 rows x 22 columns 5 FPIX ROC s HDI flex circuit Sensor module 6 cm 380,160 pixels per half-station total of 23Million pixels in the full pixel detector Pixel detector half-station Readout module Bump bonds

6 Simulated B event

7 Simulated B event

8 Primary interaction vertex

9 Primary interaction vertex

10 B decay vertex K B s K π K D s

11 L1 vertex trigger algorithm Two stage trigger algorithm: 1. Segment finding 2. Track/vertex finding 1) Segment finding stage: Use pixel hits from 3 neighboring stations to find the beginning and ending segments of tracks. These segments are referred to as triplets

12 Segment finding: inner triplets 1a) Segment finding stage: phase 1 Start with inner triplets close to the interaction region. An inner triplet represents the start of a track.

13 Segment finding: Track/vertex outer triplets finding 1b) Segment finding stage: phase 2 Next, find the outer triplets close to the boundaries of the pixel detector volume. An outer triplet represents the end of a track.

14 Track/vertex finding 2a) Track finding phase: Finally, match the inner triplets with the outer triplets to find complete tracks. 2b) Vertex finding phase: Use reconstructed tracks to locate interaction vertices Search for tracks detached from interaction vertices

15 Trigger decision Execute Trigger Generate Level-1 accept if 2 detached tracks going into the instrumented arm of the BTeV detector with: 2 p T b 6σ b cm (GeV/c) 2 B-meson p p b

16 BTeV trigger overview BTeV detector Front-end electronics 7 > 2 x 10 channels 7.6 MHz 800 GB/s PIX µ Level-1 L1 muon Global Level-1 L1 vertex Level-1 Buffers L1 rate reduction: ~100x Information Transfer Control Hardware GL1 accept Level 2/3 Crossing Switch Req. data for crossing #N Crossing #N ITCH RDY L2/3 rate reduction: ~20x Level-2/3 Buffers #1 Level-2/3 Processor Farm #2 #m-1 #m Data Logging Level-3 accept 4 KHz

17 Level 1 vertex trigger architecture 30 station pixel detector FPGA segment finders Switch: sort by crossing number track/vertex farm (~2500 processors) Merge Trigger decision to Global Level 1

18 Pixel stations Collision Hall Data combiners Counting Room Pixel data readout to neighboring FPGA segment finder DCB DCB DCB Optical links Pixel processor Pixel processor Pixel processor FPGA segment finder Pixel sync (1bit) processor Row (7bits) Column (5bits) BCO (8bits) ADC (3bits) Chi pid (13bits) time-stamp expansion time ordering clustering algorithm to neighboring FPGA segment finder xy table lookup FPIX2 Read-out chip

19 L1 segment finder hardware N - 2 Within beam hole? Use only hits in Project inner region to non-bend of N-1 plane Project upstream N - 1 Pixel Stations Matching Project hit? to non-bend plane N Now Start look with at non-bend view hits plane on N-1 N-1and N N N + 1 Is there a hit? Matching hit? Matching hit? Look Project at non-bend to non-bend plane plane N N+1 beam axis Look at non-bend Project downstream plane N+1 FIFO FIFO Long Doublet Finder FIFO FIFO Triplet Finder FIFO FIFO Short Doublet Finder FPGA Segment Finder FIFO FIFO Short Doublet Finder FIFO FIFO Short Doublet Finder to switch

20 L1 segment finder on PTA card Uses Altera APEX EPC20K1000 instead of EP20K200 on regular PTA Modified version of PCI Test Adapter card developed at Fermilab for testing hardware implementation of 3-station segment finder (a.k.a. Super PTA )

21 L1 track/vertex farm hardware ROM RAM Data from segment finder 64 KB FIFO Buffer Manager (BM) RAM DSP DSP DSP ROM Processed results to L1 buffers ROM RAM RAM Hitachi H8S DSP To GL1 ArcNet Controller RAM Hitachi H8S Trigger Results Manager (TM) RAM DSP ROM To external host computer ArcNet Controller Compact Flash On-board Peripherals Glue Logic (OPGL) Host Port Glue Logic (HPGL) McBSP lines (SPI mode) HPI bus LCD Display JTAG Block diagram of pre-prototype L1 track/vertex farm hardware

22 L1 trigger pre-prototype board CMC connectors Buffer Manager FPGA FIFO 32-bit output 32-bit input

23 L1 pre-prototype with DSP mezzanine cards Hitachi serial consoles Hitachi programming CF/LCD FPGA ArcNet ArcNet GL1/HPI FPGA Hitachi H8S Hitachi H8S FPGA boot device McBSP TI C6711 McBSP

24 L1 trigger pre-prototype test stand Hitachi programming serial console Xilinx programming cable ArcNet PCI test adapter TI DSP JTAG emulator

25 Level 2/3 trigger R&D 24-port fanout switch Processing nodes from retired Fermilab farm High-density blade server under evaluation

26 BTeV trigger architecture Pixel Processors Data Combiners + Optical Transmitters FPGA Segment Finder Level-1 Buffers Gigabit Ethernet Switch Track/Vertex Farm Front End Boards Optical Receivers Global Level-1 GL1 Information Transfer Control Hardware ITCH Level 2/3 Processor Farm 12 x 24-port Fast Ethernet Switches BTeV Detector 8 Data Highways Cross Connect Switch Data Logger

27 Real Time Embedded Systems (RTES) RTES: NSF ITR (Information Technology Research) funded project Collaboration of computer scientists, physicists & engineers from: Univ. of Illinois, Pittsburgh, Syracuse, Vanderbilt & Fermilab Working to address problem of reliability in large-scale clusters with real time constraints BTeV trigger provides concrete problem for RTES on which to conduct their research and apply their solutions Database Operators Analysis Generic Modeling Environment (GME) Vendor APIs Global Manager Regional Level-1 Regional Level-2/3 Adaptive Reconfigurable Mobile 1 1 Objects of Reliability(ARMOR) Farmlet Worker PC 1 Very Light Weight Agent (VLA) 4 Worker DSP

28 End End

29 Backup slides Backup slides

30 L1 trigger efficiencies Process Efficiency Minimum bias 1% B s D + sk - 80% B 0 J/ψΚ s B - K s π - B - B 0 φk s 2-body modes (π + π,κ + π,κ + Κ ) 65% 45% 74% 80% L1 vertex trigger efficiencies

31 L2 trigger efficiencies Process Efficiency Light quark 7% B s D + sk - 85% B 0 J/ψΚ s B - K s π - B - π + π - 78% 72% 87% L2/L1 trigger efficiencies