Introducing Protel DXP

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3 Introducing Protel DXP The complete multi-dimensional design capture system for Windows 2000 and XP Protel DXP breaks new ground by bringing a host of new and enhanced features to the design desktop and provides you with a complete, fully-integrated and intuitive board-level design system. Features in Protel DXP include project integration, integrated component libraries, project variant support, true multi-channel project design, a powerful design compiler, project-level design synchronization, version control, mixed text and schematic-based VHDL design entry, integrated SPICE 3f5 simulation with enhanced waveform viewer, the Situs Topological Autorouter and direct signal integrity analysis.

4 Introducing Protel DXP Software, documentation and related materials: Copyright 2003 Altium Limited. All rights reserved. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Protel, DXP, Design Explorer, nvisage, P-CAD, TASKING, Accolade, CircuitMaker, CAMtastic!, Situs and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited. Orcad, Orcad Capture, Orcad Layout and Specctra are registered trademarks of Cadence Design Systems, Inc. All other registered or unregistered trademarks referenced herein are the property of their respective owners, and no trademark rights to the same are claimed.

5 Introducing Protel DXP Table of Contents Introducing Protel DXP is a collection of tutorials and articles written to assist you as you explore the features and concepts available in DXP. 1. Introduction Altium s Protel DXP is a versatile multi-dimensional design system that can be used to capture, simulate and verify electronic designs targeted for both PCB and FPGA implementations. 2. Feature highlights of Protel DXP Protel DXP is a true, multiple capture, multiple analysis and multiple implementation design environment. This article looks at the feature highlights of Protel DXP. 3. Design capture, simulation & layout tutorial This tutorial is designed to give you an overview of how to create a schematic, update the design information to a PCB and generate manufacturing output files. It also investigates the concept of projects, integrated libraries and circuit simulation. 4. Customizing DXP Resources tutorial This tutorial looks at customizing your DXP, such as rearranging menus and toolbars to meet your design requirements. 5. Creating components tutorial Learn how to create schematic components in the Schematic Library Editor and footprints in the PCB Library Editor. This tutorial covers the creation process through to the production of an integrated library containing the new components. 6 Integrated Libraries tutorial This tutorial looks at using, creating and modifying integrated libraries in DXP. 7. Customizing component reports tutorial In this tutorial, learn how to customize your BOMs and Component Cross Reference reports using the Report Manager. 8. Multi-channel design tutorial This tutorial shows how to create a multi-channel design using DXP. 9. Board Shape & Sheet tutorial This tutorial covers board shapes, sheets, templates and keepouts used in DXP s PCB Editor. i

6 Introducing Protel DXP 10. Editing multiple objects tutorial This tutorial demonstrates how to perform filtering, selecting and editing of multiple objects in the workspace. 11. Version Control System tutorial This tutorial looks at adding projects and documents to your Version Control System and then checking them out for use and checking them back in again to the VCS using the DXP menus. 12. Signal Integrity tutorial This tutorial shows you how to analyze the Signal Integrity performance of a PCB from either the Schematic or the PCB Editors, evaluate net screening results against predefined tests, perform reflection and crosstalk analysis on selected nets and display the waveforms within the Design Explorer. 13. Getting started with FPGA tutorial This tutorial is designed to give you an overview of how to create an FPGA design using DXP. It will outline how to create a schematic and generate an EDIF-FPGA netlist that can be used with the third party vendor place and route tools. 14. VHDL & schematic capture tutorial This tutorial shows how to create and simulate a mixed schematic and VHDL design using DXP. 15. Attributes for FPGA tutorial FPGA attributes are special directives that are used during the placement and routing of a FPGA design. 16. Protel DXP & Altera Interface tutorial This tutorial will guide you with the necessary steps needed to start creating FPGA designs for programming Altera FPGA devices. 17. Protel DXP & Xilinx Interface tutorial This tutorial explains the Xilinx FPGA schematic library and other important information that will enable you to start using DXP for programming Xilinx FPGA device with placement and routing tools. 18. Making Electronics Design Easier This article describes an entire design from the Engineer s perspective: dividing the job between PCB and FPGA design, then using DXP tools to complete both. 19. Tips for Design Capture This article summarizes the basic concepts of design editing in DXP, emphasizing concepts that are consistent between the schematic and PCB editors. ii

7 Introducing Protel DXP 20. Project Essentials This article describes projects, which embody the most powerful features of DXP. 21. Component, Model and Library Concepts This article defines components, models and libraries, then explains their relationships. 22. Enhanced Library Management using Integrated Libraries This article introduces integrated libraries, describing how they are created, what they contain and how they can be used Multi-channel design concepts This article introduces the true multi-channel design functionality introduced with DXP. 24. Net Connectivity & Navigation This article explains the different ways of establishing multi-sheet connectivity, and the different browsing tools that let you verify net connectivity within DXP. 25. Working with Simulation Waveforms This article describes how simulation charts and plots may be arranged and manipulated in DXP. 26. Design Updates & ECOs This article describes the Engineering Change Order (ECO) process in DXP. 27. Introduction to the Query Language This article introduces the query language, and points readers to the resources within DXP for understanding it. 28. An Insider s Guide to the Query Language This article has been provided to de-mystify what queries are, how and why they are used, and to provide insights into how these can be specified to accomplish particular objectives. 29. Understanding & managing DXP panels This article introduces panels, which offer alternative views and tools for manipulating design documents besides the standard graphical environment. 30. Specifying PCB design rules & resolving errors This article describes how rules are defined, edited, and checked through online or batch DRC tools. It discusses preventing errors and navigating and resolving violations. 31. Impedance Controlled Routing This article discusses the new layer-specific controls that have been added to PCB routing width rules. iii

8 Introducing Protel DXP 32. Transferring a design from Protel 99 SE This article outlines the steps by which Protel 99 SE designs may be converted into PCB projects in DXP. 33. Shortcut keys List of shortcut keys for use in Design Explorer, Schematic Editor and PCB Editor. 34. Glossary Index iv

9 Introducing Protel DXP 1 Introducing Protel DXP Welcome to a new approach to board-level design. Altium s Protel DXP is a complete end-to-end system that can be used to capture, simulate, verify and implement electronic designs targeted for both PCB and FPGA platforms. Protel DXP s design capabilities include: Full nvisage multidimensional design capture capabilities Schematic capture for both PCB and FPGA designs Hierarchical multi-channel design support Highly automated, rules-driven PCB layout and editing Situs topological autorouting SPICE 3f5/XSpice-compliant simulation Pre-layout signal integrity analysis VHDL development and compilation VHDL simulation with timing back annotation RTL-level VHDL synthesis for multiple target FPGA architectures Bidirectional translation for Orcad schematics and libraries, and import of Orcad PCB files Full CAMtastic CAM file editing and verification. Traditionally board-level design has required a collection of point tools, each targeting a particular part of the design process. Protel DXP changes this by providing you with all the capabilities you need to take a design from concept through to manufacture within a single application. Protel DXP virtually eliminates data translation issues that can occur when moving designs between separate point tools, and avoids the additional work needed to recapture parts of your design within different applications. For example, rather than recreate your design in a separate application for simulation, Protel allows you to run SPICE simulations directly on your production data from within the schematic editor. Similarly, the full power of Altium s Situs topological autorouter is at your disposal at any time during the design of your PCB. Because Situs is fully integrated into the PCB editing environment, there is no need to export your design data to a separate application for autorouting. Simply select the appropriate menu item to autoroute a net, a component, a selected set of objects, or the whole board. Signal integrity analysis in Protel DXP is not a separate process that needs to be run after the board design is finished. After all, changes made at this late stage in the design cycle can be time consuming and expensive! Instead Protel DXP gives you access to signal integrity analysis both during design capture and throughout the PCB design process. You can check impedances and signal reflections from your schematics, and insert appropriate termination networks before beginning board layout and routing, saving time-consuming board redesigns. You can then check the signal integrity on the final board to confirm that your finished design is free from reflection and crosstalk problems. 1-1

10 Introducing Protel DXP This focus on the design process as a whole, rather than segmenting the design flow into separate discrete segments, is what makes Protel DXP a unique and productive design environment. Take for example the way in which Protel DXP ensures the synchronization of all the documents in your design. Rather than a simple back annotation process, Protel DXP employs a sophisticated synchronization engine that compares the source schematics with the PCB. Any differences are displayed along with an option to push individual changes either back to the schematics or forward to the PCB, with full ECO support. In this way, multiple changes made within multiple documents at different design stages can be easily reconciled, and the entire design project brought into synchronization. Design verification and rule compliance are at the core of Protel DXP. Its versatile rules-based PCB design environment lets you fully specify all aspects of your design, and enforces compliance to rules such as track width and separation as you work to ensure your board conforms to specifications. Using a powerful query-based scoping system, design rules can be set up and targeted to virtually any object or set of objects in your design, giving you full control over your design specifications. Protel DXP s front end capture capabilities are provided by Altium s revolutionary nvisage multidimensional design capture technology. This includes a powerful and versatile schematic editing environment that supports hierarchical design using either a top down or bottom up approach. There are no limits to the number of sheets or the depth of hierarchy, making Protel suitable for designs of any complexity. The schematic editor supports multi-channels design by allowing you to easily define blocks of repeated circuitry. Unlike many systems that simply copy and paste repeated blocks, Protel DXP maintains channel hierarchy at all times, even through to the PCB design. You can edit channel circuitry or even change the number of channels at any time. Channel instantiation is handled automatically by the system without the need to flatten the design. Once you make a change to one channel, you can easily propagate the change to all channels on the PCB. Programmable logic, particularly in the form of high-density FPGAs, is becoming an increasingly important part of modern designs. Protel DXP recognizes this by providing all the capabilities you need to target your design for FPGA implementation. Using the supplied pre-synthesized FPGA macro and primitive libraries, you can use Protel s schematic editor to create designs for all Xilinx and Altera FPGA families without the need for any VHDL coding. Protel DXP also includes a full VHDL development environment that allows you to write, compile, simulate, debug and synthesize industry-standard VHDL code. Protel DXP supports the back-annotation of pin assignment information from FPGA place and route tools, allowing you to easily propagate FPGA pin changes to both the FPGA design and any related PCB projects. When it comes to board-level electronics design, Protel DXP is the only application to provide all the capabilities you need within one single, customizable and intuitive design environment. Protel DXP breaks down the barriers to design innovation and lets you work the way you want. Protel DXP the complete board-level design system from Altium. 1-2

11 Feature Highlights of Protel DXP 2 Feature Highlights of Protel DXP Introduction A Multi-dimensional Approach to Design Multiple Capture Modes Powerful Compilation and Validation Comprehensive Design Analysis Circuit Simulation VHDL Simulation Signal Integrity Analysis Working with Analysis Results VHDL Synthesis for FPGA Implementation True Multi-channel Design Design Navigation The DXP Data Editing Paradigm Controlling What is Displayed Filtering the Data Controlling How it is Displayed Highlighting the Data DXP Data Views the Object Inspector DXP Data Views the List Panel Editing Essentials Selection Memory Components the Core of the Design Integrating all the Component Information into a Single Package Component Parameter Management Linking from Components to a Company Database Complete Management of Component Updates Defining PCB Design Rules in the Schematic Interfacing to a Version Control System Design Synchronization linking the Schematic to the PCB How the Schematic Components Link to their PCB Footprint Passing Design Changes Between the Schematic and PCB Designing Assembly Variants Generating Project Outputs Output Job Setup and Management Flexible Report Generation Situs Topological Autorouter Design Rule Compliance Sophisticated BGA and Surface Mount Component Fanout Strategies Multiple Routing Strategies User definable Routing Strategies

12 Feature Highlights of Protel DXP Impedance Controlled Routing New PCB Design Rule Scoping System Understanding Queries Definable Rule Priorities PCB Layout Enhancements PCB Board Shape PCB Sheet Templates Component Placement Rooms Associative Dimensioning tools Enhanced Splitting of Power Planes Managing Component Heights on the PCB Working with Dual Monitors Interfacing to Other Design Tools Other New and Enhanced Features Introduction This document gives an overview of the new features in nvisage and Protel DXP. To help you get started designing with nvisage or Protel, it is recommended that you do the introductory tutorial, Design Capture, Simulation & Layout. The tutorial is a simple design for a multivibrator, it will take you through the entire design process from creating a project, to capturing the schematic, transferring the design to the PCB Editor, generating output, and also simulating the schematic. Doing this tutorial will give you a good overview of designing in nvisage and Protel DXP. There are also introductory tutorials for signal integrity analysis, FPGA design, and VHDL simulation. Both nvisage and Protel are project-centric design environments, with powerful new navigation and object management features, new high-level design capabilities such as design variants and multichannel design, and numerous enhancements in the design tools. The user interface has been extensively redesigned, bringing superior functionality to the design space. Features such as panels that can be docked, float, or set to Pop Out mode, automatic fade for floating panels and toolbars whenever an edit is performed, support for dual-monitors, and click and drag customization of resources, all go to make the design process more efficient and enjoyable. As to the difference between nvisage and Protel, think of nvisage as the tool for the design engineer as such it includes all the capture and analysis features, as well as certain PCB features. The PCB features are all those that the engineer might need transfer of design information from schematic to PCB, component placement, rule definition, printing, and post-routing signal integrity analysis. Protel includes all the nvisage features, plus the familiar Protel PCB design tools and the comprehensive CAM verification, NC route, and output generation features included in CAMtastic. These icons indicate if a feature has been added or enhanced in service pack 1 or

13 Feature Highlights of Protel DXP A Multi-dimensional Approach to Design nvisage DXP and Protel DXP are true, multiple capture, multiple analysis and multiple implementation design environments. The basis of any design in nvisage or Protel is the project. The project links the elements of your design together, including the source schematics and VHDL files, the netlist, any libraries or models you want to keep in the project, and the PCB. The project also stores the project-level options, such as the error checking settings, the multi-sheet connectivity mode, and the multi-channel annotation scheme. To create a new project, select New Project from the File menu. nvisage and Protel currently support three project types, FPGA projects, PCB projects and Library Packages (the source for an integrated library). Related PCB projects and FPGA projects can also be linked under a common project group, giving easy access to all files related to a particular design. As you add documents to a project, such as a schematic sheet or a VHDL testbench, a link to each document is entered into the project file. The documents can be stored anywhere on your network, they do not need to be in the same folder as the project file. To edit a document that is part of a project, first open the project to display a list of the documents in the project, then double click on the document you wish to edit in the Projects panel. To add a new document to the active project right-click on any document in the project and select New from the floating Project menu. Note that this action adds the document to the project to get a schematic sheet to become part of a schematic hierarchy you place a sheet symbol on the parent schematic, and set the sheet symbol Filename field to that of the child schematic sheet. As well as being able to open and edit documents by first opening their project, you can also directly open and edit any document. Multiple Capture Modes Both nvisage and Protel DXP provide a versatile and fully integrated design capture system for both PCB and FPGA applications. Designs can be captured using schematic, or any mixture of schematic and VHDL for an FPGA design. The schematic editor supports both top-down and bottom-up design, using a block diagram metaphor to provide an intuitive link between the sheets in the project hierarchy each Orcad Capture V7 and V9 block representing an individual schematic sheet. Wiring these blocks designs and libraries can be together creates connectivity connectivity that can be verified and navigated imported directly. Export as soon as the design is compiled. There is no limit to the number of from DXP to Orcad V7. schematic sheets, or the depth of design hierarchy. Beyond the traditional schematic capture model, nvisage and Protel also support true multi-channel design. Unlike other schematic capture programs, which flatten hierarchy and physically copy and 2-3

14 Feature Highlights of Protel DXP paste sheets to construct multiple channels, nvisage and Protel maintain design hierarchy at all times. Nested hierarchy is also supported, allowing you to create channels within channels. Because the system maintains channel hierarchy, you can edit a channel at any time, or change the number of channels, without needing to manually propagate the changes through each channel instance. Channel instantiation is handled automatically during compilation. Within an FPGA project you can mix schematic-driven design with VHDL source files to provide complete flexibility in the capture of your design. nvisage and Protel come with a complete set of presynthesized macro and primitive schematic libraries for both Altera and Xilinx FPGA families. For VHDL development, the VHDL editor is a fully-featured coding environment that supports programming features such as syntax highlighting and auto-indenting. nvisage and Protel also includes a range of navigational features to support mixed VHDL / schematic designs. You can navigate through the entire VHDL / schematic hierarchy from the Navigator panel, as well as cross-probe between schematic sheets and VHDL code. Powerful Compilation and Validation At the core of the DXP environment is a powerful design compiler and comparison engine. The compiler builds a compiled model of the design in memory, which is then checked for an array of possible error conditions. A view of the compiled design is displayed in the Navigator panel, which can be used to examine the connective relationships throughout the design. If warnings or errors are detected they are listed in the Messages panel, from which a double-click takes you to the relevant location on the source document. Once a design has been compiled and checked to ensure that it has been captured correctly it is ready for analysis, or transfer to the next stage of the design process. Comprehensive Design Analysis nvisage and Protel include a range of analysis and verification tools including a SPICE3f5/Xspice compliant circuit simulator, a VHDL simulator, and a comprehensive signal integrity analysis feature. These tools are completely integrated, ready to be used when needed. 2-4

15 Feature Highlights of Protel DXP Circuit Simulation The circuit simulator uses an enhanced version of Berkeley SPICE3f5/Xspice, allowing you to accurately simulate any combination of analog and digital devices, without manually inserting D/A or A/D converters. This mixed-signal simulation is possible because the simulator includes accurate, event-driven behavioral models for its digital devices, including TTL and CMOS digital devices. All SPICE-compliant analog simulation models are supported. The circuit simulator includes the standard analyses operating point, transient and AC small signal as well as a number of advanced analyses including DC sweep, temperature sweep, parameter sweep, noise, pole zero and Monte Carlo analysis. VHDL Simulation The VHDL simulator is a complete system for the compilation and execution of VHDL design descriptions. The optimized VHDL simulator includes a VHDL compiler, linker and simulator. It gives you fast functional and timing analysis of your FPGA design, allowing you to view output waveforms and debug your VHDL code. Using the VHDL simulator s Step Mode, you can step through the execution of your test bench and cross-probe from the code to the relevant component in the schematic. There are over 40 circuit simulation examples, covering a wide range of circuit examples and analysis types. The simulator also supports post place and route simulation, include the SDF timing file in your design to verify that the design is still within specification. The \Examples\FPGA folder includes a number of mixed schematic / VHDL examples that can be simulated. 2-5

16 Feature Highlights of Protel DXP Signal Integrity Analysis With increasing device switching speeds signal integrity issues are no longer restricted to the high speed engineer. Both pre and post-layout signal integrity analysis can be performed in nvisage and Protel. The guiding rule to designing to avoid signal integrity issues is impedance matching achieved at the capture stage through correct device matching and termination, and at the PCB layout stage through correct definition of the physical characteristics of the PCB materials and the routing. Pre-layout signal integrity analysis allows you to check the signal 2-6 Use the termination advisor to explore possible solutions to potential signal integrity problems integrity during schematic capture, avoiding the risk of costly design rework after layout if terminations are required or device technology must be changed. Specify an average impedance for routing, then analyze the design and check the integrity of the signals on the oscilloscope-like waveform viewer. If problems are found you can explore different device technologies or the effect of different termination options, using the sweep feature to quickly determine the optimal termination component values. The average impedance value specified during pre-layout analysis can then be used during PCB design to correctly define the layer stackup and configure the new impedance controlled routing rules. Protel s post-layout analysis then confirms that the quality of the routed signals are still within specifications. The signal integrity analyzer uses the characteristic impedance of the traces, calculated through a transmission line calculator, and I/O buffer macromodel information, as input for the simulations. It is based on a Fast Reflection and Crosstalk Simulator which produces very accurate simulations, using industry-proven algorithms. It can test for a variety of conditions, including overshoot and undershoot, impedance, flight time and rise time. Signal integrity analysis can be performed even if models have not been assigned for every component the SI engine will select a suitable default model, and indicate the confidence in the assumed model. Refer to the Signal Integrity tutorial for an overview of performing an SI analysis on your design.

17 Feature Highlights of Protel DXP Working with Analysis Results The DXP environment includes two powerful waveform viewers. The analog viewer supports multiple plots, overlaid plots with multiple Y axes, tracking measurement cursors, mathematical formula applied to plot results, copy to clipboard and export of plot data. The digital viewer supports typical functional timing features such as transition stepping, time measurement and value display. There are synthesisready example designs in the \Examples\FPGA folder. VHDL Synthesis for FPGA Implementation Synthesis is the process of transforming a logic design specification into an implementation. nvisage and Protel s fast and proven RTL-level VHDL synthesis engine allows you to target devices from multiple vendors, giving you complete freedom in your choice of FPGA architecture and device family. The synthesis engine includes advanced features such as module generation, hierarchical synthesis, automatic I/O insertion and macrocell inference - features traditionally found in expensive FPGA synthesis tools. Back-annotation of pin information from the place and route tools to both board-level and FPGA projects is supported, allowing you to easily synchronize FPGA pin assignments throughout the entire design. The following FPGA devices are currently supported: Xilinx, 3k, 4k, 5k, 7k, 9.5k, Spartan, Virtex and Coolrunner Series Altera Stratix, APEX, Cyclone, ACEX, FLEX, MAX and Excalibur Series Actel ACT, 40MX, 42MX, 54SX, ex, 500k and proasic Series Atmel PLD Lattice PLSI and ORCA Series Quicklogic pasic Series Vantis CPLD. 2-7

18 Feature Highlights of Protel DXP True Multi-channel Design How often has your design included a section of the circuit that is repeated repeated twice, four times, or perhaps 32 times? nvisage and Protel DXP includes a number of features that bring full support for true, nested, multi-channel design including sheet symbol instantiation, multi-channel designator management, automatic component class and room creation, and step and repeat of channel placement and routing. Reset Connector For Banks Bank 1 Bank 2 Bank 3 Bank 4 Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Peak Detector Channel Bank Connector Bank Connector Bank Connector A diagram of a 32 channel design, configured as 4 banks of 8 Bank Connector True multi-channel design means that you only draw the channel schematic once there is no need to create multiple copies of the sheet. The schematic project remains in this state even after you transfer the design to PCB layout, the system maintains the relationship from the single logical component to the many-physical components. There are two approaches to drawing the multi-channel design in the schematic editor place a sheet symbol for each channel with each referencing the same schematic sheet, or use the new sheet symbol instantiation syntax to reference all channels from a single sheet symbol. The sheet symbol instantiation syntax uses the Repeat keyword to define the number of times the channel is to be instantiated. When the project is compiled the compiler instantiates the channel the required number of times as it builds the internal compiled model, using a chosen annotation scheme to uniquely identify each component in each channel it does not duplicate the channel sub-sheet. Once the project is compiled a Tab appears at the bottom of the Schematic Editor window, with one Tab for each channel of that sub-sheet. 2-8 Each instantiated physical component is uniquely identified by the designator assigned when the project is compiled. The annotation scheme is controlled in the Multi-channel Tab of the Project Options dialog. The mapping from the single logical component on the schematic to the multiple physical instances on the PCB is controlled by the multi-channel designator scheme selected in the Multi-Channel Tab of the Project Options dialog.

19 Feature Highlights of Protel DXP Multi-channel support flows through to PCB layout. When the design is transferred the components are placed in their channel groups (component classes), with each component class on the board automatically clustered into a placement room. After positioning the components in one channel within their room use the Autoroute» Room command to route the channel, then select the Tools» Rooms» Copy Room Formats command to step and repeat the placement and routing across all the channels. The step and repeat function supports double sided placement and routing of a channel, as well as step and repeat of a single sided channel onto both sides of the PCB. For more overview information refer to the Multi-Channel Design Concepts article. For a description of the process of creating a nested multi-channel design refer to the Multichannel Design tutorial. Example multi-channel projects include the Multichannel Mixer and the Peak Detector. Step and repeat the placement and routing of one room (channel) to all other channels 2-9

20 Feature Highlights of Protel DXP Design Navigation Design navigation is an activity that is carried out throughout the design process. This includes during the initial capture phase as you place and wire components, during the verification process as you analyze and validate the design, and also as you work between the schematic and the PCB during layout. The DXP Navigator panel supports the traditional click-to-highlight style of browsing the design, as you click the selected object(s) is presented on screen. Beyond that, you can also analyze and trace the connectivity in the design either spatially in the actual workspace, or in the special floating Browser. Design navigation is enabled by compiling the design, select Compile from the Project menu. Use the options at the top of the Navigator panel to control the display as you browse, more options are available in the Options tab of the Project Options dialog. The Navigator panel can be used to browse and cross probe to documents, components, buses, nets and pins. A single click on an entry in the panel will browse to that object in the source schematics and VHDL documents, hold the Alt key as you click to simultaneously cross probe to the same object(s) on the PCB. Spatial navigation is a browsing technique where you navigate directly in the sheet click on a net to highlight all objects in the net, click on a port to jump to the sheet entry it connects to, and so on. Enable the Graph option to display the connective relationship between objects red for net objects, green for components. Highlight by Masking and Graph the net 2-10

21 Feature Highlights of Protel DXP The Browser offers a different perspective of the connectivity, placing you within the design and letting you follow signals throughout the project hierarchy, as well as cross-probe to both the schematic object and their PCB counterpart. An alternative method of navigating your design is available with the new design Browser. In contrast with the Navigator panel's top-down overview, the Browser lets you trace connectivity from an object's point of view. Use the Browser to navigate and analyze the relationship between objects in your design. The object you click on presents in the center of the Browser, around it are displayed any related objects. For example, if a pin is in the center of the Browser, it shows related component information on the left, with the parent component above and other pins below, and related net information on the right, with the parent net above and other pins in the net below. As you click on another object it moves to the center of the Browser, with the surrounding information being updated accordingly. As you click on an object in the Browser that object is displayed in the schematic window. Another powerful navigation mode is cross-probing, where you click on an object in one view to display the corresponding object in another view. An example is cross probing from a component on the schematic, to the component on the PCB. To do this in the DXP environment simply click the cross probe button and click on a component the corresponding component is displayed in the PCB window. 2-11

22 Feature Highlights of Protel DXP The DXP Data Editing Paradigm A typical electronic design can include many hundreds of objects in the schematic, and many thousands of design objects on the PCB. While the traditional graphical view of the data has many strengths, it does not present the engineer or board designer with efficient ways of finding and editing multiple objects in a densely packed design space. nvisage and Protel DXP present a new paradigm for data editing it combines powerful object filtering with flexible view and highlighting options to give complete control over the selection, presentation and editing of design data. There are 3 elements to the data editing system the design data, the views of the data, and the view control system. The view control system performs 2 functions, it gives you control over what is displayed in a data view, and it also lets you control how it is displayed. Controlling What is Displayed Filtering the Data To cope with the large amount of data in the workspace DXP includes a comprehensive filtering system. Filtering can be performed in a number of ways, including using the Navigator panel, the Find Similar Objects dialog, or by writing a filter query. The Find Similar Objects dialog is used to start from one object, then based on its attributes find other objects that have similar attributes. Right-click on an object, select Find Similar, and set the attributes to match by in the right-hand column. If the Select option is enabled the required set of objects will then be available for editing in the Object Inspector panel. Another approach to finding objects is to write a query, the DXP query language is a powerful and flexible tool for precisely targeting objects in the design. Controlling How it is Displayed Highlighting the Data Different design tasks present different demands on the engineer or board designer to edit a font style for a number of strings on the schematic you need to select those strings and then edit them simultaneously. On the other hand, if you are checking the routing of a net selecting the objects would obscure vital layer information in this case it is better if only those objects that make up the routing are visually enhanced in some way. Using the masking feature to find a routed net on the PCB 2-12

23 Feature Highlights of Protel DXP The DXP environment offers three highlighting modes selecting, zooming, and the new masking mode. Masking is a powerful visualization aid, where all objects in the workspace are faded, except those of interest. DXP Data Views the Object Inspector The traditional graphical view gives excellent spatial information about the relationship of design objects, but does not give access to other important attributes such as parameters, or location data. DXP includes three alternate views of the design data: the traditional graphical view, the spreadsheet-like List view, and the Object Inspector. Use the List panel when you need to compare the attributes of a set of objects, and to easily paste in data cells from a spreadsheet program. Use the Inspector to easily edit common attributes in the currently selected objects. Use the Object Inspector to change the footprint of 8 selected schematic components DXP Data Views the List Panel As well as the traditional graphical view, where the objects are arranged in the workspace as you placed them, you can also view and edit objects in the new List panel. The List panel is a combination of a query editor, highlight controls, and a spreadsheet. When you type in a query at the top of the panel Refer to the DXP Data Editing Paradigm poster for more information on the Data Editing paradigm. and enable the Mask highlighting option, the contents of the spreadsheet are automatically updated to remove all objects filtered out by the query. The spreadsheet is a genuine alternate view any action you perform in the spreadsheet, such as selecting a group of objects, or editing an object, occurs simultaneously in the graphical view. 2-13

24 Feature Highlights of Protel DXP Editing Essentials The unique data editing system in the schematic and PCB editors provides a number of features for finding and highlighting objects in the design workspace. As well browsing your design to find objects, they can also be used to edit objects in the design. The basic sequence to editing multiple objects is to Find, Select and Edit. Find there are a number of features for finding objects, including the Navigator, the Browser, the Find Similar dialog, or by writing a query. Select select the objects to be edited. Enable the Select check box (available in the Find Similar dialog, and the Navigator and List panels), use CTRL+A if masking is enabled, or build the selection manually. Queries are a powerful mechanism to find objects in your design refer to the article, An Insider s Guide to the Query Language for a comprehensive description of how to make the most of using queries. Edit display the Object Inspector (F11) and edit the selected objects (the Inspector displays all properties that are common to the selected objects). After making a change in the Inspector, press the Enter key on the keyboard to apply the change. Selection Memory To enhance this selection-oriented editing model, 8 selection memories are available in the schematic and PCB editors, which can be used to store and recall the selection state of up to 8 sets of objects on the schematic or PCB. The following selection memory options are available: Store in memory (CTRL + number 1 to 8) Add to memory (SHIFT + number 1 to 8) Recall from memory (ALT + number 1 to 8) Recall and Add from memory (SHIFT + ALT + number 1 to 8) Apply memory as a workspace filter (SHIFT + CTRL + number 1 to 8) Display Selection Memory control panel (CTRL + Q) As well as using shortcuts to access the selection memories, there is also a Selection Memory sub-menu in the Edit menu, and a Selection Memory control panel that is opened by clicking the button next to the Mask Level button at the bottom right of the workspace. To prevent inadvertent overwriting of a selection memory enable the Confirm Selection Memory Clear option in the Preferences dialog. Refer to the tutorial, Editing Multiple Objects for examples of how to find, select and edit multiple objects in the design workspace. 2-14

25 Feature Highlights of Protel DXP Components the Core of the Design Every engineer and designer knows that the components are the core of their design. The components manipulate the electrical energy to produce the functionality required in the product. To create the final product the component must be represented, or modeled, in a variety of forms during the design capture, analysis and implementation phases. In nvisage and Protel DXP the schematic component is the centre-point of the component definition. The basic representation of the component is the symbol, used to instantiate the component in the schematic. Beyond the symbol, other representations are added as models. nvisage supports a variety of model kinds, including footprint, simulation, VHDL, EDIF and Signal Integrity. A link to each required model file is added to the component, either in the schematic library or on the schematic sheet. Refer to the Creating Components tutorial for a complete description of the component creation process, including model creation and linkage. As well as the visual and electrical information that is represented in the schematic symbol and the associated model files, the component will typically have many other attributes, or parameters that must be specified. These can include electrical parameters important to the design, such as wattage, or tolerance, and they can also include manufacturing information, such as a company stock number or the supplier s reference number. This information is included in the component as parameters any number of parameters can be added, either at the schematic library or on the schematic sheet. Parameters can also be linked to a company database. The properties of the component, including models and parameters, are defined in the Component Properties dialog 2-15

26 Feature Highlights of Protel DXP Integrating all the Component Information into a Single Package Typically each model type is defined in a model file or library, with each having a different file format. To support the variety of model formats the model data is not stored in the schematic component, it is linked to it. This provides a flexible and extensible component specification system. The disadvantage of this approach is that the separate files must be managed All library types, including schematic, PCB and integrated libraries are accessed through the Libraries panel. in a library with a large number of components, each using a number of models, the total number of files can be high. To resolve this the DXP environment supports the creation and use of integrated component libraries. An integrated component library is a complete and portable package of schematic symbols, PCB footprints, simulation models, SPICE models, VHDL models, EDIF models and signal integrity models. To build an integrated component library you start by creating a library package. The library package is a project file that defines what components are in the integrated library. Once the library package is complete, you compile it to produce the integrated library. The integrated library (*.IntLib) is a single, portable, compiled file that cannot be edited. It is added in and used in the DXP environment like any other library. Component Parameter Management 2-16 Refer to the following tutorial and articles for more information on libraries: - Integrated Libraries tutorial - Enhanced Library Management using Integrated Libraries - Component, Model and Library Concepts. As well as the visual and electrical information that is defined in the schematic symbol, the component will typically have many other attributes, or parameters that must be specified. These could include electrical design parameters, purchasing information, and assembly information. This information is included by adding parameters to the schematic components, either in the schematic library or on the schematic sheet. Right-click in the Parameter Editor for a complete list of options, press F1 for detailed information. To manage these parameters the DXP schematic editor includes a powerful Parameter Editor. When you select Tools» Parameter Manager from the menus, you first specify the scope of parameters which you wish to review or modify. Suppose, for example, that you had defined a PCB design rule for a bus by adding a parameter to its port, and now you want to add the same rule to other buses and nets. Rules are system parameters, so these should be included when you show all parameters for nets and ports. After defining the scope, the Parameter Table Editor appears. The Table Editor supports the addition/removal of parameters, and editing of one or many parameter values. It includes full support for table copy/paste operations to and from your preferred spreadsheet program, including mismatched cell ranges. Right-clicking on any field will display a full range of parameter editing options. Differences that are created during parameter editing are indicated using icons a green plus indicates that a parameter is being added, a red minus The Parameter Table Editor gives you full editing access to all design parameters (including locked ones). On the other hand, you can set any parameter to ignore update instructions from libraries or a database.

27 Feature Highlights of Protel DXP indicates a parameter is being removed, gray hatching indicates that this component does not include this parameter. So to continue the task mentioned above, you would locate the Rule column among the System parameters, then browse down to the one you defined. Now you can either copy it for pasting into the destination cells, or you can select all the destination cells together, right-click in the selection and choose Edit, then find your defined rule in the drop-down list. Linking from Components to a Company Database Design capture in nvisage or Protel is one stage of the product development process. For a company to correctly manage designs developed in nvisage or Protel they need information to flow between the DXP design environment and the company component management system. This can be achieved by linking from the components on the schematics to a company database. Database linking allows data to be transferred from the database to the components on the schematic, and that data can then be included in the Bill Of Materials produced at the end of the development process. Links are established between schematic component parameters and an external database through a Database Link (.DBLink file) added to your project. This file allows for links to be specified via ODBC connections, as well as having predefined support for MS-Access and MS-SQL server connections. The key ingredient to database linking is the key field this information is read from the schematic component, then searched for in the database. When there is a match, other cells from that record in the database can then be taken back to the mapped parameters in the schematic component. Once you have added a DbLink file you first specify the connection to the database, then indicate which database fields should match up with which design parameters, and how design updates should occur. The Table Browser tab in the DbLink file allows you to view your database tables for reference. The Database Links tab is used to correlate database fields for each table, with your design parameters. For each table you must first select one database field and one existing design parameter as the key fields used for matching from the schematic part to a table row. If no suitable parameter exists in your schematic parts, you must create one. This can be done easily in DXP, using the Parameter Manager to add a parameter to all relevant components, which you can then use as the key parameter in the DbLink file. Once the connection from the schematic to the database is defined then any other values that are in the database can be transferred back to the schematic, by mapping them in the Database Links tab. The fastest way to create these links in the Database Links tab is to highlight a row and press 2-17

28 Feature Highlights of Protel DXP Ctrl+D. This creates a proposed Design Parameter for your design (named the same as the database field name), and enables all the default update options (defined in the Database Link Options dialog). If you want the database field to link to a different parameter name (existing or new), you can either choose the name from the drop-down list or type it in yourself. Return to your schematics and select Tools» Update from Database to synchronize parameter values with your database. Any Design Parameters that exist in the DbLink file that are not in the schematics are automatically added. You will still have options to reject any of the proposed updates before executing the changes in an ECO dialog. You can then use the parameter manager to review and edit all parameters for the entire design. Open the DbLink document in the 4 Port Serial Interface project for an example of database linking. Linking to the example database is done using an absolute path, which defaults to C drive. Change this in the Database Connection dialog if required. Complete Management of Component Updates An essential aspect of component management is controlling the propagation of component and library updates out into the designs that use them. The Update From Library wizard gives complete control over this update process, enabling you to update components on one or more schematic sheets of the active project, with information from components stored in selected schematic library documents. Updates can be done by component type to update all components of the specified type in the entire design, or it can be done on a per-component instance basis, where the updates are controlled down to the level of each individual component in the design. With the required schematic(s) open, select Tools» Update from Libraries to launch the Update From Library wizard. Choosing Schematic Documents and Component Types to Update Use the first page of the Update From Library wizard to select which schematic documents and component types you wish to include in the update. Initially, all component types are enabled for inclusion in the update, disable component types that you do not want to consider in the update. Select Fully replace symbols on sheet with those from library to fully replace the components on the schematic sheet(s) with those that are stored in the source schematic library. Graphical attributes, parameters and 2-18 The Wizard includes a summary of its behavior in the panel at the top. Press F1 for detailed information.

29 Feature Highlights of Protel DXP models will all be updated from the source library. Click the Finish button, check the changes that will be implemented in the subsequently generated ECO, and execute them. All component instances of the component types enabled will be updated with the current information in the source library. The library that is used to Setting the Level of Control of the Update Process If you want more control over what is updated, disable the Fully replace option in the Update from Library wizard and enable/disable the default actions you require for the update of graphical attributes, parameters and models. Click on the Advanced button to display the Library Update Settings dialog where you can define default update actions with respect to parameters and/or models. Click on the Finish button. An ECO will be created, which you can use to view and execute the changes to be implemented in the update. Controlling the Changes to Individual Schematic Parts If you require control over the update of individual component instances, click on the Next > button to display the second page of the Update from Library wizard. You can enable/disable which update actions are performed and selectively control changes at the parameter level as well. update the component is the one specified in the component on the sheet. The library must be listed in the Available Libraries dialog. To force a search in a different library (or all libraries) edit the Library setting in the component. Use the Parameter Manager to edit multiple components. You can also specify a new component (new Lib Ref) and/or source schematic library. Alternatively, you can select a component instance and click the Choose Component button to browse for a particular component in an available library or along any nominated search path. Click on the Parameter Changes button to display the Select Parameter Changes dialog which summarizes the changes that will be made to parameters for those components with a parameter update action enabled. You are given final control over whether to accept or reject changes for each component instance. Having defined the update actions for each individual component instance, click on the Finish button to open the Engineering Change Order dialog. Here you can review, validate and execute the changes to be implemented. Placed schematic components will be updated with the selected information from the source schematic libraries when you close this dialog. 2-19

30 Feature Highlights of Protel DXP Defining PCB Design Rules in the Schematic PCB specific design rules can be defined in the schematic, they are added as parameters. When you add a parameter to an object there is an button. If this is clicked the resulting Parameter Properties dialog will include an button, click this to display the Choose Design Rule dialog,where the rule type can be chosen, and then configured in an edit rule dialog. In the PCB Editor the scope of a rule the set of objects that this rule will target is defined as part of the rule. In the schematic editor the scope of the rule is defined by where the parameter is added. The following schematic parameter to PCB rule scope options are supported: Add Parameter to Pin Port Parameter Set object on a wire Parameter Set object on a bus Component Sheet symbol Sheet For a PCB rule scope of pad net net net class component component class All objects Interfacing to a Version Control System Version Control you can interface directly from the Protel DXP interface to popular third party version control systems, including Visual SourceSafe. Right-click in the Project panel to access the version control menu options, or select Version Control in the project menu for a complete set of features. The VCS interface compiles with the Microsoft SCC interface, giving direct access to an SCC compliant VCS from within the DXP environment. Refer to the DXP Version Control tutorial for more information on working with a VCS. 2-20

31 Feature Highlights of Protel DXP Design Synchronization linking the Schematic to the PCB One of the challenges of PCB design is keeping the schematic and the PCB synchronized, or matched. Invariably design changes are made to the schematic, the PCB, or both and these changes must be transferred to the other design documents. Traditionally this is done using a transfer file of some sort, typically either a netlist or an ECO file. In the DXP environment synchronization is performed directly between the schematic and PCB. DXP synchronization is also bi-directional, meaning that changes can be transferred in both directions in the one update. Underlying design synchronization in nvisage and Protel DXP is a powerful comparison engine. This comparison engine is used to compare the source schematic project to the PCB. The comparison engine does a complete comparison of all appropriate aspects of each design, including component data such as designator, value, footprint and relevant parameters as well as connectivity information including net names and net nodes. How the Schematic Components Link to their PCB Footprint The comparison engine can be used to compare any appropriate design documents including a PCB to a netlist, netlist to a netlist, schematic sheet (or project) to schematic sheet (or project), and so on. The key to synchronizing between the schematic and PCB is linking from each schematic component to its corresponding PCB footprint. In Protel DXP this can be done in two ways, either by designator, or by a unique identifier. To check the status of the component links select Component Links from the Project menu in the PCB editor. The Component Links dialog display the linkage state of the components. 2-21

32 Feature Highlights of Protel DXP Components that are linked with a matching unique ID are listed in the Matched Components region on the right, components that are not currently matched by a unique ID are shown in the two fields on the left. At the bottom of the dialog are controls that can be used to quickly match components, or you can select unmatched schematic and PCB components and match them manually. Generally it is better to match components using a unique ID, this allows you to re-annotate the designators on the schematic or the PCB, and always be able to resynchronize the design. If you attempt to synchronize the design and unique IDs are not assigned for all the components, you will be prompted to attempt to match these components by designator. Note that this matching is by designator only, it does not check the footprint or comment. If you are unsure if matching by designator will be correct click No when prompted, then launch the Component Linking dialog to review the matching. To give complete control over the assignment and management of linking via unique IDs, DXP will only assign UIDs when the software places a component into the PCB workspace. If components have been placed manually from a library you can use the Component Links dialog to match and assign their UIDs. Passing Design Changes Between the Schematic and PCB Select Update in the Design menu to transfer design changes from the schematic to the PCB, or from the PCB back to the schematic. The Engineering Change Order dialog will appear, listing the changes that need to be applied to the target document(s), to make them match. Not all differences can be resolved when you perform an Update, for instance net connectivity changes can not be transferred from the PCB back to the schematic. If there are changes that can not be transferred a Confirm dialog will appear, detailing how many changes can not be performed. If you click No in this dialog the Differences dialog will appear, listing all differences found between the 2 views of the design. The role of this dialog is described below. Resolving Differences - How Does it Work? The comparison engine works by performing a detailed comparison of the connective model (netlists) compiled from each design view. The result of this comparison process is a set of differences. The process of detecting and resolving differences between design documents works in the following way: Compare the design views: Typically this is the schematic project to the PCB. This is done either by selecting Update in a Design menu, or by selecting Show Differences in the Project menu. Generate the list of differences: If you selected Update then Protel DXP knows which way you want the changes applied, so the Differences dialog is not displayed. If you selected Show Differences all differences are listed in the Differences dialog. Set the change direction: If you have opted to examine the differences first, you must set the change direction in the Differences dialog. Right click and choose from the floating menu to set all updates in one action, or click in the Update Decision column and individually set the change direction. 2-22

33 Feature Highlights of Protel DXP Generate the Change list: After setting the direction you generate an ECO. The ECO is a list of actions that will be performed to resolve the differences. Apply the changes: Execute the ECO to perform the updates. For a general overview of the update process refer to the Design Updates and ECOs article. For a list of the object kinds supported in a schematic-to-pcb comparison, look in the Comparator Tab of the Project Options dialog. Not all object kinds are supported in each design view, for example a Protel Netlist does not support Rooms or Classes. The Differences dialog lists all detected differences right click to control which updates are applied in each direction. Once the updates are defined click to generate the ECO. 2-23

34 Feature Highlights of Protel DXP Designing Assembly Variants nvisage and Protel DXP support assembly variants. An assembly variant is created when you wish to design one PCB, but load it in different configurations each configuration is referred to as an assembly variant. The typical process is to complete the full design and layout the PCB. Once it is complete, and the schematic and PCB synchronized, you are ready to define the assembly variants. Variants are created and managed in the Variant Management dialog. Variant specific output, such as assembly drawings, is generated from an OutJob file. Select Project» Variants to create an assembly variant. The Variant Management dialog shows the set of components for the entire design. Once you have added in the required variants and set the Not Fitted option for those components that are to be left off in that variant, you can generate the variant specific outputs, including the Bill of Materials, the pick and place file, and the assembly drawing from the Output Job File (*.OutJob). 2-24

35 Feature Highlights of Protel DXP Generating Project Outputs The end goal of the design process is to produce the necessary output files to manufacture and deliver the product. These include: a set of schematics to supply with the product; a Bill Of Materials to go into the company s product manufacturing system; the Gerber, NC drill and manufacturing files to fabricate the bare board; assembly drawings, pick and place, and testpoint files to assemble the board; as well as numerous other incidental files that might be needed for the product handbook, special netlist formats for RF analysis, and so on. These outputs can be generated individually using the relevant commands in the File, Design and Reports menus. Output Job Setup and Management Right click for a list of options, or double-click on an output to configure it. Management and generation of project outputs can also be achieved through the use of an Output Job file. The Job file stores a set of output setups, including print, CAM, report and netlist. Any combination of output setups can be included in the Job file, and any number of Job files can be included in the project allowing you to use them in the way that works best in your organization. When a new Job file is added to a project it defaults to include all possible output setups. Selected setups can be deleted (use the CTRL+A shortcuts to select all), and new outputs can be added at any time. Each output setup uses a specific data source, sources include the entire project (all schematic sheets), an individual schematic, or the PCB. Double-click to configure the specifications for an individual output setup. The Tools menu includes a number of Run options, when the Run Batch command is selected (F9) all output setups with the Batch checkbox ticked will be generated. At this point, all CAM files will be saved according to your project options, and normal print dialogs will appear for hard copies. You can also generate output for a selected group of outputs from within the output job file, highlight them and invoke the Run Selected command (Shift+Ctrl+F9). Fabrication-type outputs can be loaded automatically into the DXP CAM tool, CAMtastic. The file types that are automatically loaded are defined in the Output Job Options dialog. 2-25

36 Feature Highlights of Protel DXP Flexible Report Generation Every company has their own reporting requirements. To support this, the Report Outputs include a completely configurable reporting output generator. Several component reports, such as the Bill of Materials (BOM) report and the Component Cross Reference report, can be customized in DXP using this Report Manager. This facility allows you to sort and group the data gathered You can also access the Report Manager from the output job configuration file (File» New» Output Job File). when the report is run. You can also export the report in various formats, such as a Microsoft Excel document, or use an Excel template to format the exported data. The Report Manager can be accessed via the Bill of Materials option in the Reports menu, or by adding a Bill of Materials output setup in an OutJob file. Fully Customizable Reporting The report structure is defined in the Report Manager dialog. The dialog takes on the title specified in the OutJob file, the default is Bill Of Materials. The information in the Report Manager dialog is sourced from the properties of all components in the project. Use this dialog to build up the information to include in your BOM. To configure the report: Enable the Show option next to the columns you want to be displayed in the report, each one that is ticked is added to the main grid. For a complete description of the process of setting up Arrange columns in the main grid by clicking and dragging the column a custom report, refer to the heading. Customizing Component Reports tutorial. Group the data in the main grid by specifying which columns to group by to do this drag a column from the Other Columns list to the Grouped Columns list. Multiple 2-26

37 Feature Highlights of Protel DXP levels of grouping are supported. For example, if you group by Value, all components that have the same value will be grouped into a single row in the main grid. If you then add Footprint to the Grouped Columns, all components that have the same Value AND Footprint will be grouped into a single row. If required, sub-sort the data by applying a filter in the Custom AutoFilter dialog (click on a column heading). Once the data is configured, it is ready to generate the output. Generating the report There are two primary methods of generating output, using the Export button or the Excel button. The Export option generates output in a number of file formats, including Microsoft Excel Worksheet (*.xls), Comma Separated Value (*.csv), Web page (*.html), XML Spreadsheet (*.xml), and Tab Delimited Text (*.txt). Using Excel Templates The Excel option allows you to generate and load the generated output directly into an Excel spreadsheet, automatically applying the selected Excel template as it is generated. To examine how the data in the report maps to the fields in the Excel template open one of the example templates in the Altium\Templates\ folder. All templates in this folder automatically appear in the Template drop down in the Report Manager dialog. 2-27

38 Feature Highlights of Protel DXP Situs Topological Autorouter Design Rule Compliance Situs offers complete design rule compliance for all electrical and routing design rules, including via style and blind and buried vias. Sophisticated BGA and Surface Mount Component Fanout Strategies Situs includes a number of sophisticated fanout strategies, supporting all surface mount packaging technologies including BGA, QFP and LCC fine pitch components. These can be run during autorouting, or used interactively to pre- fanout components, nets, connections, and so on. Select the required fanout option in the Auto Route» Fanout sub-menu. The fanout behavior is controlled by the Fanout Control design rules, define the required number of rules to suit the surface mount components used in the design. Multiple Routing Strategies Situs comes with a number of default routing strategies, each focused to route well in a specific situation. Situs will automatically select either the default 2 layer or the default multilayer strategy automatically, but you are free to select a different strategy. The main difference between the two default strategies is that the default multilayer strategy includes a signal fanout pass. Select the preferred routing strategy before launching the router. User definable Routing Strategies The default strategies cannot be edited. They can be duplicated, and any number of user defined strategies can be created. Choosing the optimal combination of strategies is highly dependant on the characteristics of the board being routed. It is recommended that you start by duplicating one of the default strategies, then experiment by adding, removing and reordering routing passes. 2-28

39 Feature Highlights of Protel DXP Impedance Controlled Routing Routing a PCB to ensure it meets the impedances requirements is a process of configuring the physical properties of the stackup; including material properties, copper and insulation thicknesses, and placement of plane layers relative to signal layers as well as selecting suitable track routing widths. To give you control over this process the Layer Stack Manager includes built-in impedance calculators for both microstrip and stripline impedance calculations. Click the Impedance Calculation button in the Layer Stack Manager to examine the equations used to calculate the impedances. These calculators work in harmony with the Routing Width design rules whenever they are configured in the Characteristic Impedance Driven Width mode. In this mode the routing width required on each layer is calculated based on the specified impedance, using the appropriate equation and the physical parameters defined in the layer stack. It is important that the layer stack parameters are correctly defined to achieve realistic results. With the rule defined, as you route a net covered by that rule it will automatically be set to the width required on that layer to meet the specified impedance. Impedance controlled routing requires power/ground planes in the stackup, if you enable the Characteristic Impedance Driven Width option without a power plane in the stackup the routing widths will be held at the values that were in the dialog before the option was enabled. 2-29

40 Feature Highlights of Protel DXP New PCB Design Rule Scoping System The design rules define the requirements of your design, including clearances, routing widths, power plane connection styles, routing via styles, and so on. Each rule has a rule scope, the scope defines exactly what the rule applies to such as all objects on the board, or all objects in a particular net, or all components with a certain footprint. Rather than using a fixed, predefined set of rule scopes, Protel DXP uses queries to define what objects a rule is to apply to. There are a number of methods you can use to create the rule scope. These include: The pre-defined options in each rule dialog for Net, Net Class, Layer, and Net and Layer. Selecting one of these and then choosing from the drop down lists automatically writes the query. The Query Builder select from lists to quickly build the query. The Query Helper includes all available query keywords, with a short description of each. Press F1 when the cursor is within a keyword for a comprehensive description of the keyword and examples of using it. Querying is a technique used to find, or target objects in the design workspace. For a comprehensive description of how to make the most of using queries refer to the article, An Insider s Guide to the Query Language. A paste mask expansion rule, targeting all components that use a TSOP12X16 footprint 2-30

41 Feature Highlights of Protel DXP Understanding Queries A query is a combination of symbols keywords, object identifiers, operators, and values that are analyzed, and then applied to every object in the workspace to see if the object complies with that query. The results of the query is the set of objects that the rule will apply to. Some tips on becoming familiar with Queries include: Use the Query Helper when you know what sort of keyword you are looking for, but are not sure what the exact syntax is, try typing it, the type-ahead prompts will help. Also, use the Mask field, for example if you are looking for footprint related keywords type *footprint in the mask field, then click on each of the categories to list only those keywords that include the string footprint in the keyword or description. Use the List panel to test a query type the query in the editor at the top of the List and click Apply, that way you can visually check to see if it is targeting the correct objects. You can also review the current rule scopes at any time by setting the PCB panel to Rules, when you click on an individual rule in the panel it will filter the workspace to show only the objects that the rule will apply to. Definable Rule Priorities To make the scoping system more flexible, the order that rules are applied the rule priority is userdefinable. The priority is displayed in the main window of the Design Rules dialog, if you navigate down using the tree on the left, when you select a rule Type (for example Width) you can click the Priorities button at the bottom of the dialog and change the priority. The highest priority rule is priority

42 Feature Highlights of Protel DXP PCB Layout Enhancements PCB Board Shape The board shape defines the boundary, or extents of the board. It is used by Protel DXP to determine the extents of the power planes for power plane edge pullback, and for calculating the board edge when outputting design data, such as Gerber. Press the Spacebar to change the corner style while you are defining the board shape. When a new board file is created a default board shape is also created. This can be resized, or redefined using the commands in the Design» Board Shape sub-menu. If your design already includes a board boundary defined on a mechanical layer, use the Define from Selected Objects command to automatically match the board shape to your outline. Make sure that the shape defined by the selected objects on the mechanical layer is closed there are no gaps in the boundary. The board shape defines the edge of the board and is used for automated functions such as the plane pullback. 2-32

43 Feature Highlights of Protel DXP PCB Sheet Templates If you open the PCB example files you will notice that most of them display the board on a sheet, and that the sheet includes a border, grid reference, and title block. Rather than use special objects to implement the template; the border, grid references and title block are drawn on one of the mechanical layers (Mechanical16 in the examples). The sheet itself the white region is a special drawing feature. It is controlled using the options in the Board Options dialog. The sheet can be associated with mechanical layers by placing objects on mechanical layers you can then create any sort of drawing template you require. Once the template elements are placed on a mechanical layer, the layer can be Linked to the Sheet in the Board Layers dialog. The sheet can be hidden at any time, disable the Display Sheet option in the Board Options dialog. All linked mechanical layers will also be hidden. If you set the workspace start and end colors to black (Board Layers dialog) you can easily switch from the new sheet mode to the tradition full black mode by switching the sheet display on and off in the Board Options dialog. Protel DXP includes a set of pre-defined PCB templates (\Altium\Templates), open the required template and copy the contents from it and paste them into your board file. While the sheet size and location can be defined manually, if you have linked the sheet to a mechanical layer the white sheet background is resized automatically to fit the objects on the linked layer when you select View» Fit Sheet from the menus. Component Placement Rooms Protel DXP has enhanced component placement room functionality, including polygonal rooms, copy room formatting, creating a room to fit a component class, and autorouting and unrouting in a room. The set of tools for working with rooms are detailed below. Watch the status bar when using each of the tools: Place Rectangular Room place a rectangular room on the top or bottom side of the board (Tools» Rooms menu). Place Polygonal Room place a polygonal room on the top or bottom side of the board (Tools» Rooms menu). Copy Room Formats copy the placement and routing in the selected room, to other rooms that contain an identical set of components. Use this feature in a multi-channel design, after placing and routing one channel Protel DXP will automatically place and route the other channels (Tools» Rooms menu). Wrap Room Around Components if you have already placed the components in a component class use this command to automatically wrap the room around the components. Create Non-Orthogonal Room from selected components create a component class from the selected components, then create a non-orthogonal room around them (Tools» Rooms menu). Create Orthogonal Room from selected components create a component class from the selected components, then create an orthogonal room around them (Tools» Rooms menu). 2-33

44 Feature Highlights of Protel DXP Create Rectangle Room from selected components create a component class from the selected components, then create a rectangular room around them (Tools» Rooms menu). Autoroute room autoroute all connections that start and end within a room (Autoroute menu). Un-route room un-route all connections that have at least one node in a room (Tools» Un-Route menu). Slice a room use this to slice one room into 2 rooms (Edit» Slice menu). Associative Dimensioning tools Protel DXP includes a comprehensive set of dimensioning tools, including Linear, Baseline, Datum, Leader, Angular, Center, Radial, Linear Diameter, Radial Diameter. Dimensions can be placed from the Dimensions sub menu, or the Dimensions toolbar. Dimensions are associative, once they are connected to an object they will remain connected to the object as it is moved. To associate a dimension to an object, such as a track end, look for the small hollow circle drawn in the same color as the layer being placed on, this circle indicates that the dimension will associate with this point. Each dimension type also offers complete control over the units, the precision, the text alignment, and the arrow characteristics double click on a dimension to edit any of these parameters. Keep an eye on the Status bar when you are placing a dimension each type has a different placement sequence, the Status bar will prompt you what to do next as you place the dimension. For information on a particular dimensioning tool press F1 when the mouse is over a dimension menu entry or toolbar button. 2-34

45 Feature Highlights of Protel DXP Enhanced Splitting of Power Planes DXP s new power plane splitting feature works like cutting with a knife. To split a plane make the plane the current layer, and switch to single layer mode (Shift+S shortcut toggles single layer mode). Select Place» Line from the menus. Starting from just outside the board shape, place lines to define the cut, or separation, between the two regions you are splitting apart. The width of the line defines the no-copper separation, press the Tab key during line placement to change the width. When you first split a plane you must start from outside the board shape and finish outside the board shape. You can also cut within the plane, as long as you always start and finish on an edge, or an existing cut. Fully Definable Pad Shapes Protel DXP supports 3 types of pad definition: Simple where the pad properties are the same on all layers Top-Mid-Bottom where the top layer and bottom layer are defined individually, and all midlayers are defined as a set Full Stack where the pad properties can be defined uniquely on every layer. Click the Edit Full Pad Layer Definition button to configure the pad. 2-35

46 Feature Highlights of Protel DXP Managing Component Heights on the PCB A height property has been added to PCB footprints. The height can be defined on the board in the Component dialog, or via the PCB Library Component dialog in the PCB Library Editor (Tools» Component Properties). A new Height design rule has been added to the Placement rules section in the PCB Rules and Constraints Editor. Use this when you need to define height restrictions on the PCB. To define height restrictions on an area basis you can scope the rule using a query keyword of WithinRoom, or TouchesRoom (place the room which defines the restricted area using the Design» Room sub-menu), or one of the region checking queries, InRegion, InRegionAbsolute or InRegionRelative. For information on the query keywords, click the Query Helper button, type the keyword in, then press F1 when the cursor is within the keyword. 2-36

47 Feature Highlights of Protel DXP Working with Dual Monitors nvisage and Protel DXP take full advantage of a dual monitor configuration. You can arrange the documents across both monitors, or you can use the second monitor for secondary views, such as the object Inspector Panel or the List Panel. To position a document on the second monitor, right-click on a document Tab and select Open in New Window to create a second DXP window, ready to position on your second monitor. Alternatively, you can drag a document Tab out when DXP is not maximized. Note that this second window is not a second instance of Protel DXP, it runs in the same Microsoft Windows process. To position an individual panel on the second monitor simply click and hold on the actual Panel name in the caption bar of the panel, and drag and position it. Hold the CTRL key as you drag it to prevent it from docking to the edge of the application. Interfacing to Other Design Tools nvisage and Protel support translation from numerous other design tool formats. Schematic Capture Direct Orcad Capture V9 & V7 schematic & library import/export AutoCAD DXF & DWG files up to R14 import/export P-CAD schematic & library import/export. PCB Design Orcad layout V9 PCB & library files import PADs PCB import up to V3.5 AutoCAD DXF & DWG files up to R14 import/export P-CAD PCB import/export Specctra DSN export and RTE import. Netlist Outputs nvisage and Protel come with a number of netlist output formats built in, including Protel, EDIF, SPICE, VHDL and Multiwire. The DXP environment supports new netlisters being dropped in at any time, visit the Downloads section of the nvisage website to download a variety of netlisters, including Mentor, Intergraph, Orcad, PADs and Tango. Orcad Capture Translation Notes Binary Orcad Capture V7 and V9 schematic and library files load directly into nvisage and Protel s schematic editor, simply select Open Project and open the DSN or OLB file. 2-37

48 Feature Highlights of Protel DXP The Orcad Hierarchical Block object is translated to a Sheet Symbol, a Page is translated to a Sheet, and Off Page Connectors are translated to Off Sheet Connectors, a new net identifier which creates horizontal net connectivity among sheets referenced by a single sheet symbol. Refer to the Net Connectivity & Navigation article for more information on Off Sheet Connectors. A new schematic library file (Schematic Title Blocks.SchLib) has been created with a selection of title block components. The new template library file has been added to the \Altium\Templates folder. This file provides an alternative to the existing templates and gives Orcad Capture users a familiar way of supporting title blocks. To export a design back to Orcad Capture V7, select File» Save Project As. Other New and Enhanced Features There are numerous other new and improved features in nvisage and Protel DXP. Below is a short summary of some of the other features, for a complete list of the new features refer to the Release Notes PDF available on the website. PCB routing when you start on existing routing it picks up the current track width, if it is within the range allowed by the design rules. Schematic document opening hold Ctrl as you double click on a sheet symbol to open the subsheet. Mouse zooming can now use Ctrl+roll to zoom while executing a command. Auto-increment controls added in schematic preferences use these to control the auto-increment pattern when placing objects such as net labels or pins on a component. Values can be numeric or alpha, incremented or decremented. Embedded images images can be embedded in schematic files. Copy/Paste to lists in most list displays (e.g., List panel, Parameter Manager) you can copy and paste multiple cells. New shortcuts F5 to switch between a panel and the document, F4 to hide all floating panels (very handy when there is a large floating panel displayed). Selected objects flagged in pick lists a small dot appears next to each selected object in a PCB pick list. Context sensitive right click menu the PCB workspace right-click menu is truly context sensitive, it now includes specific sub-menus depending on what is under the cursor when the click occurs. VHDL simulation results includes multiple cursors add multiple cursors in a VHDL waveform window, and take measurements between them. 2-38

49 Design capture, simulation and layout an introductory tutorial 3 Design capture, simulation and layout Welcome to the DXP introductory tutorial The Design Explorer How the design documents are stored Creating a new project Creating a new schematic sheet Adding schematic sheets to a project Setting the schematic options Drawing the schematic Locating the component and loading the libraries Placing the components on your schematic Wiring up the circuit Setting up Project Options Checking the electrical properties of your schematic Compiling the project Creating a new PCB document Adding a new PCB to a project Transferring the design Updating the PCB Designing the PCB Setting up the PCB workspace Defining the layer stack and other non-electrical layers Setting up new design rules Positioning the components on the PCB Manually routing the board Automatically routing the board Verifying your board design Setting up the Project Outputs Printing Manufacturing output files Simulating the design Setting up for simulation Running a transient analysis Further explorations

50 Design capture, simulation and layout an introductory tutorial Welcome to the DXP introductory tutorial Welcome to the world of DXP a complete 32- bit electronic design system for Windows 2000 and XP. DXP provides a completely integrated suite of design tools that lets you easily take your designs from concept through to final board layout. All DXP tools run within a single application environment the Design Explorer. Start DXP and the Design Explorer opens, putting all your design tools at your fingertips. You benefit from a single, customizable user environment. This tutorial is designed to give you an overview of how to create a schematic, update the design information to a PCB and generate manufacturing output files. It also investigates the concept of projects, integrated libraries and circuit simulation. The Design Explorer The Design Explorer is your interface to your designs and the design tools. To start DXP and open the Design Explorer, select Programs» Altium» DXP from the Windows Start menu. When you open DXP, the most common initial tasks are displayed for easy selection. DXP System Menu Click the down-arrow icon to display the System menu and set up the system preferences. All other menus and toolbars automatically change to suit the document being edited. Workspace panels These include Files and Projects panels. These panels can be moved, docked or clipped by clicking on the panel title and dragging it to a new location. Click on the tab at the bottom of the panel to display its contents. Workspace Common tasks are listed to get started quickly. Panel Control Editor specific and shared panels can be chosen from the Panel Control list. Workspace panels More pop out panels are displayed by clicking on these tabs. These panels can also be moved, docked or clipped. Help Advisor Use the natural language help system to quickly find the answer to your question. 3-2

51 Design capture, simulation and layout an introductory tutorial As you create your design documents, you can easily switch between editors, for example, the Schematic Editor and the PCB Editor. The Design Explorer will change toolbars and menus according to the editor you are currently working in. The name of some workspace panels will initially be displayed down the right side of the workspace. Click on these names to pop out the panels, which then can be moved, docked or clipped to suit your work environment. The following diagram shows the Design Explorer when several documents and editors are open at the same time and the windows have been tiled. Document tabs Each open document has its own tab at the top of the design window. Right-click on a tab to close, split or tile the open windows. Design Window Displays the documents that are currently open in this design. Schematic Editor Graphical and List views You can choose between showing your documents in a graphical view in the design window, or as a list of objects with their properties in the List view (View» Workspace Panels» List), or both. Layer tabs Each PCB layer has its own tab. PCB Editor Workspace panels Click on these buttons to display the associated workspace panel. The Selection Memory button saves selections. The Mask Level button allows you to change the level of dimming of unmasked objects. Click Clear to clear the current mask. How the design documents are stored DXP stores all the design documents and output files on your hard disk as individual files. You can use the Windows Explorer to search for them. Project files can be created that contain links to the design documents and are necessary for design verification and synchronization. Creating a new project A project in DXP consists of links to all documents and setups related to a design. A project file, e.g. xxx.prjpcb, is an ASCII text file that lists which documents are in the project and related output 3-3

52 Design capture, simulation and layout an introductory tutorial setups, e.g. for printing and CAM. Documents that are not associated with a project are called free documents. Links to schematic sheets and a target output, e.g. PCB, FPGA, embedded (VHDL) or library package, are added to a project. Once the project is compiled, design verification, synchronization and comparison can take place. Any changes to the original schematics or PCB, for example, are updated in the project when compiled. The process of creating a new project is the same for all project types. We will use the PCB project as an example. We will create the project file first and then create the blank schematic sheet to add the new empty project. Later in this tutorial we will create a blank PCB and add it to the project as well. To start the tutorial, create a new PCB project: 1. Click on Create a new Board Level Design Project in the Pick a Task section of the design window. Alternatively, you could select File» New» PCB Project from the menus, or click on Blank Project (PCB) in the New section of the Files panel. If this panel is not displayed, click on the Files tab at the bottom of the Design Manager panel. 2. The Projects panel displays. The new project file, PCB Project1.PrjPCB, is listed here with no documents added. 3. Rename the new project file (with a.prjpcb extension) by selecting File» Save Project As. Navigate to a location where you would like to store the project on your hard disk, type the name Multivibrator.PrjPCB in the File Name field and click on Save. Next we will create a schematic to add to the empty project file. This schematic will be for an astable multivibrator circuit. Creating a new schematic sheet Create a new schematic sheet by completing the following steps: 1. Select File» New» Schematic, or click on Schematic Sheet in the New section of the Files panel. A blank schematic sheet named Sheet1.SchDoc displays in the design window and the schematic 3-4

53 Design capture, simulation and layout an introductory tutorial document is automatically added (linked) to the project. The schematic sheet is now listed under Schematic Sheets beneath the project name in the Projects tab. 2. Rename the new schematic file (with a.schdoc extension) by selecting File» Save As. Navigate to a location where you would like to store the schematic on your hard disk, type the name Multivibrator.SchDoc in the File Name field and click on Save. When the blank schematic sheet opens you will notice that the workspace changes. The main toolbar includes a range of new buttons, new toolbars are visible and the menu bar includes new items. You are now in the Schematic Editor. You can customize many aspects of the workspace. For example, you can reposition the panels and toolbars or customize the menu and toolbar commands. Now we can add our blank schematic to the project before proceeding with the design capture. Adding schematic sheets to a project If the schematic sheets you want to add to a project file have been opened as Free Documents, rightclick on the schematic document in the Free Documents section of the Projects panel and select Add to Project. The schematic sheet is now listed under Schematic Sheets beneath the project name in the Projects tab and is linked to the project file. 3-5

54 Design capture, simulation and layout an introductory tutorial Setting the schematic options The first thing to do before you start drawing your circuit is to set up the appropriate document options. Complete the following steps: 1. From the menus, choose Design» Document Options and the Document Options dialog will open. For this tutorial, the only change we need to make here is to set the sheet size to standard A4 format. In the Sheet Options tab, find the Standard Styles field. Click the arrow next to the entry to see a list of sheet styles. 2. Select the A4 style and click the OK button to close the dialog and update the sheet size. 3. To make the document fill the viewing area again, select View» Fit Document. DXP has a multilevel Undo, allowing you to undo any number of previous actions. The maximum number of Undo steps is userconfigurable and limited only by the available memory on your computer. In DXP, you can activate any menu by simply pressing the menu hotkey (the underlined letter in the menu name). Any subsequent menu items will also have hot keys that you can use to activate the item. For example, the shortcut for selecting the View» Fit Document menu item is to press the V key followed by the D key. Many submenus, such as the Edit» DeSelect menu, can be called directly. To activate the Edit» DeSelect» All on Current Document menu item, you need only press the X key (to call up the DeSelect menu directly) followed by the A key. Next we will set the general schematic preferences. 1. Select Tools» Schematic Preferences [shortcut T, P] from the menus to open the schematic Preferences dialog. This dialog allows you to set global preferences that will apply to all schematic sheets you work on. 2. Click on the Default Primitives tab to make it active and enable the Permanent check box. Click the OK button to close the dialog. 3. Before you start capturing your schematic, save this schematic sheet, so select File» Save [shortcut F, S]. You can save any schematic sheet as a document template (.dot) allowing you to include special information such as a custom company title block and logo. Drawing the schematic You are now ready to begin capturing (drawing) the schematic. For this tutorial, we will use the circuit shown below (Figure 1). This circuit uses two 2N3904 transistors configured as a self-running astable multivibrator. 3-6

55 Design capture, simulation and layout an introductory tutorial Figure 1. An astable multivibrator Locating the component and loading the libraries To manage the thousands of schematic symbols included with DXP, the Schematic Editor provides powerful library search features. Although the components we require are in the default installed libraries, it is useful to know how to search through the libraries to find components. Work through the following steps to locate and add the libraries you will need for the tutorial circuit. First we will search for the transistors, both of which are type 2N Click on the Libraries tab to display the Libraries panel. 2. Press the Search button in the Libraries panel, or select Tools» Find Component. This will open the Search Libraries dialog. 3. Ensure that the Scope is set to Libraries on Path and that the Path field contains the correct path to your libraries. If you accepted the default directories during installation, the path should be C:\Program Files\Altium\Library\. Click on the folder icon to browse to the library folder. Ensure that the Include Subdirectories box is not selected (not ticked) for this example. 4. We want to search for all references to 3904, so in the Name text field in the Search Criteria section, type *3904*. The * symbol is a wildcard used to take into account the different prefixes and suffixes used by different manufacturers. 3-7

56 Design capture, simulation and layout an introductory tutorial 5. Click the Search button to begin the search. The Results tab displays as the search takes place. If you have entered the parameters correctly, a library will be found and displayed in the Search Libraries dialog. 6. Click on the Miscellaneous Devices.IntLib library to select it. This library has symbols for all the available simulation-ready BJT transistors. 7. Click the Install Library button to make this library available to your schematic. Since this library is already installed by default, the button is grayed out in this example. 8. Close the Search Libraries dialog. The added libraries will appear at the top of the Libraries panel. As you click on a library name in the upper list, the components in that library are listed below. The component filter in the panel can then be used to quickly locate a component within a library. Placing the components on your schematic The first components we will place on the schematic are the two transistors, Q1 and Q2. For the general layout of the circuit, refer to the schematic drawing shown in Figure Select View» Fit Document from the menus [shortcut V, D] to ensure your schematic sheet takes up the full window. 2. Make sure the Libraries panel is displayed by clicking on the Libraries tab. 3. Q1 and Q2 are BJT transistors, click on the Miscellaneous Devices.IntLib library to make it the active library. 4. Use the filter to quickly locate the component you need. The default wildcard (*) will list all components found in the library. Set the filter by typing *3904* in the filter field below the Library name. A list of components which have the text 3904 as part of their Component Name field will be displayed. 5. Click on the 2N3904 entry in the list to select it, then click the Place button. Alternatively, just double-click on the component name. The cursor will change to a cross hair and you will have an outlined version of the transistor floating on your cursor. You are now in part placement mode. If you move the cursor around, the transistor outline will move with it. 6. Before placing the part on the schematic, first edit its properties. While the transistor is floating on the cursor, press the TAB key. This opens the Component Properties dialog for the component. We will now set up the dialog options to appear as below. 3-8

57 Design capture, simulation and layout an introductory tutorial 7. In the Properties section of the dialog, set the value for the first component designator by typing Q1 in the Designator field. 8. Next we will check the footprint that will be used to represent the component in the PCB. For this tutorial, we have used integrated libraries which mean that the recommended models for footprints and circuit simulation are already included. Make sure that model name BCY-W3/D4.7 is included in the Models list. Leave all other fields at their default values and click OK to close the dialog. You are now ready to place the part. The link between the schematic component and the PCB component is the footprint. The footprint specified in the schematic is loaded from the PCB library when you load the netlist. Double-click on a schematic component to specify the footprint. 1. Move the cursor (with the transistor symbol attached) to position the transistor a little left of the middle of the sheet. 2. Once you are happy with the transistor s position, left-click or press ENTER to place the transistor onto the schematic. 3. Move the cursor and you will find that a copy of the transistor has been placed on the schematic sheet, but you are still in part placement mode with the part outline floating on the cursor. This feature of DXP allows you to place multiple parts of the same type. So let s now place the second transistor. This transistor is the same as the previous one, so there is no need to edit its attributes before we place it. DXP will automatically increment a component s designator when you place a series of parts. In this case, the next transistor we place will automatically be designated Q2. When you are in any editing or placement mode (a cross hair cursor is active), moving the cursor to the edge of the document window will automatically pan the document. If you accidentally pan too far while you are wiring up your circuit, press V, F (View» Fit All Objects) to redraw the schematic window, showing all placed objects. This can be done even when you are in the middle of placing an object. 3-9

58 Design capture, simulation and layout an introductory tutorial 4. If you refer to the schematic diagram (Figure 1) you will notice that Q2 is drawn as a mirror of Q1. To flip the orientation of the transistor that is floating on the cursor, press the X key. This flips the component horizontally. 5. Move the cursor to position the part to the right of Q1. To position the component more accurately, press the PAGEUP key twice to zoom in two steps. You should now be able to see the grid lines. 6. Once you have positioned the part, left-click or press ENTER to place Q2. Once again a copy of the transistor you are holding will be placed on the schematic, and the next transistor will be floating on the cursor ready to be placed. 7. Since we have now placed all the transistors, we will exit part placement mode by clicking the right mouse button or pressing the ESC key. The cursor will revert back to a standard arrow. Next we will place the four resistors. 1. In the Libraries panel, make sure the Miscellaneous Devices.IntLib library is active. Use the following keys to manipulate the part floating on the cursor: Y flips the part vertically X flips the part horizontally SPACEBAR rotates the part by Set the filter by typing res1 in the filter field below the Library name. 3. Click on RES1 in the components list to select it, then click the Place button. You will now have a resistor symbol floating on the cursor. 4. Press the TAB key to edit the resistor s attributes. In the Properties section of the dialog, set the value for the first component designator by typing R1 in the Designator field. To edit the attributes of an object placed on the schematic, double-click the object to open its Component Properties dialog. 5. Make sure that model name AXIAL-0.3 is included in the Models list. 6. Set up a parameter field for the resistor that will display on the schematic and be used by DXP when running a circuit simulation later in this tutorial. The =Value parameter can be used for any general information about the component but discrete components use it when simulating. We can also set the Comment to read this value and this maps the Comment information to the PCB layout tool. Rather than enter the value twice (in the parameter =Value and then in the Comment field), DXP supports indirection which will replace the contents of the Comments field with the parameter s string If there is not a Value parameter already included in the component properties, click Add in the Parameters list section to display the Parameter Properties dialog. Enter the name Value and a value of 100k. Make sure String is selected as the parameter type and the value s Visible box is ticked. Click OK. This RES1 component already has a Value parameter, so just type 100k in the Value field. 7. In the Properties section of the dialog, click on the Comment field and select the =Value string from the drop down list and turn Visible off. Click the OK button to return to placement mode. 8. Press the SPACEBAR to rotate the capacitor by 90 so it is in the correct orientation.

59 Design capture, simulation and layout an introductory tutorial 9. Position the resistor above the base of Q1 (refer to the schematic diagram in Figure 1) and left-click or press ENTER to place the part. Don t worry about making the resistor connect to the transistor just yet. We will wire up all the parts later. 10. Next place the other 100k resistor R2 above the base of Q2. The designator will automatically increment when you place the second resistor. 11. The remaining two resistors, R3 and R4, have a value of 1k, so press the TAB key to call up the Component Properties dialog and change the Value field of the Value parameter to 1k. Click OK to close the dialogs. 12. Position and place R3 and R4 as shown in the schematic diagram in Figure Once you have placed all the resistors, right-click or press ESC to exit part placement mode. Now place the two capacitors. 1. The capacitor part is also in the Miscellaneous Devices.IntLib library, which should already be selected in the Libraries panel. 2. Type cap in the component s filter field in the Libraries panel. 3. Click on CAP in the components list to select it, then click the Place button. You will now have a capacitor symbol floating on the cursor. To reposition any object, simply place the cursor directly over the object, click-and-hold the left mouse button, drag the object to a new position and then release the mouse button. 4. Press the TAB key to edit the capacitor s attributes. In the Properties section of the Component Properties dialog, set the Designator to C1, check the PCB footprint model RAD-0.3 is added in the Models list. 5. Change the Value field of the Value parameter to 20n. Make sure String is selected as the parameter type and the value s Visible box is ticked. Click OK. 6. In the Properties section of the dialog, click on the Comment field and select the =Value string from the drop down list and turn Visible off. Click the OK button to return to placement mode. 7. Position and place the two capacitors in the same way that you placed the previous parts. 8. Right-click or press ESC to exit placement mode. The last component to be placed is the connector, located in Miscellaneous Connectors.IntLib. 1. Select Miscellaneous Connectors.IntLib from the Libraries list in the Libraries panel. The connector we want is a two-pin socket, so set the filter to *2*. 2. Select HEADER2 from the parts list and click the Place button. Press TAB to edit the attributes and set Designator to Y1 and check the PCB footprint model is HDR1X2. No Value parameter is required as we will replace this component with a power source when simulating the circuit. Click OK to close the dialog. 3. Before placing the connector, press X to flip it horizontally so that it is in the correct orientation. Click to place the connector on the schematic. 3-11

60 Design capture, simulation and layout an introductory tutorial 4. Right-click or press ESC to exit part placement mode. 5. Save your schematic by selecting File» Save from the menus [shortcut F, S]. You have now placed all the components. Note that the components in Figure 2 are spaced so that there is plenty of room to wire to each component pin. This is important because you can not place a wire across the bottom of a pin to get to a pin beyond it. If you do, both pins will connect to the wire. If you need to move a component, click-and-hold on the body of the component, then drag the mouse to reposition it. Figure 2. Schematic with all parts placed. Wiring up the circuit Wiring is the process of creating connectivity between the various components of your circuit. To wire up your schematic, refer to the diagram in Figure 1 and complete the following steps. 1. To make sure you have a good view of the schematic sheet, use the PAGE UP key to zoom in or PAGE DOWN to zoom out. Also try holding down the Ctrl key and using the mouse wheel to zoom. 2. Firstly wire the resistor R1 to the base of transistor Q1 in the following manner. Select Place» Wire [shortcut P, W] from the menus or click on the Wire tool from the Wiring Tools toolbar to enter the wire placement mode. The cursor will change to a crosshair. 3. Position the cursor over the bottom end of R1. When you are in the right position, a red connection marker (large asterisk) will appear at the cursor location. This indicates that the cursor is over an electrical connection point on the component. 4. Left-click or press ENTER to anchor the first wire point. Move the cursor and you will see a wire extend from the cursor position back to the To graphically edit the shape of a wire, or any other graphical object once it has been placed, position the arrow cursor over it and click once. Whenever a wire runs across the connection point of a component, or is terminated on another wire, DXP will automatically create a junction. When placing wires, keep in mind the following points: - left-click or press ENTER to anchor the wire at the cursor position; - press BACKSPACE to remove the last anchor point; - after placing the last segment of a wire, right-click or press ESC to end the wire placement. The cursor will remain as a cross hair and you can begin placing anothe r wire. - Right-click again or press ESC to exit wire placement mode. 3-12

61 Design capture, simulation and layout an introductory tutorial anchor point. 5. Position the cursor so that it is below R1 and level with the base of Q1. Left-click or press ENTER to anchor the wire at this point. The wire between the first and second anchor points will be placed. 6. Position the cursor over the base of Q1 until you see the cursor change to a red connection marker. Left-click or press ENTER to connect the wire to the base of Q1. 7. Right-click or press ESC to finish placing this particular wire. Note that the cursor remains a cross hair, indicating that you are ready to place another wire. To exit placement mode completely and go back to the arrow cursor, you would right-click or press ESC again but don t do this just now. 8. We will now wire C1 to Q1 and R1. Position the cursor over the left connection point of C1 and left-click or press ENTER to start a new wire. 9. Move the cursor horizontally till it is directly over the wire connecting the base of Q1 to R1. A connection marker will appear. 10. Left-click or press ENTER to place the wire segment, then right-click or press ESC to indicate that you have finished placing the wire. Note how the two wires are automatically connected. 11. Wire up the rest of your circuit, as shown in Figure 3. A wire that crosses the end of a pin will connect to that pin, even if you delete the junction. Check that your circuit looks like Figure 3 before proceeding. Figure 3. The fully wired schematic 12. When you have finished placing all the wires, right-click or press ESC to exit placement mode. The cursor will revert to an arrow. Nets and net labels Each set of component pins that you have connected to each other now form what is referred to as a net. For example, one net includes the base of Q1, one pin of R1 and one pin of C1. To make it easy to identify important nets in the design, you can add net labels. To place net labels on the two power nets: 3-13

62 Design capture, simulation and layout an introductory tutorial 1. Select Place» Net Label [shortcut P, N]. A dotted box will appear floating on the cursor. 2. To edit the net label before it is placed, press the TAB key to display the Net Label dialog. 3. Type 12V in the Net field, then click OK to close the dialog. 4. Place the net label so that the bottom left of the net label touches the upper most wire on the schematic. The cursor will change to a red cross when the net label touches the wire. If the cross is light gray, it means you are trying to label a pin instead. 5. After placing the first net label you will still be in net label placement mode, so press the TAB key again to edit the second net label before placing it. 6. Type GND in the Net field, click OK to close the dialog and place the net label. Right-click or press ESC to exit net label placement mode. 7. Select File» Save [shortcut F, S] to save your circuit. Save the project as well. Congratulations! You have just completed your first schematic capture using DXP. Before we turn the schematic into a circuit board, let s set up the project options. Setting up Project Options The project options include the error checking parameters, a connectivity matrix, the Comparator setup, ECO generation, output paths and netlist options and any project parameters you wish to specify. DXP will use these setups when you compile the project. When a project is compiled, comprehensive design and electrical rules are applied to verify the design. When all errors are resolved, the re-compiled schematic designs are loaded into the target document, e.g. a PCB document, by generated ECOs. The project Comparator allows you to find differences between source and target files and update (synchronize) in both directions. All project-related operations, such as error checking, comparing documents and ECO generation, are set up in the Options for Project dialog (Project» Project Options). Project outputs, such as assembly and fabrication outputs and reports can be set up from the File menu options. You can also set up job options in a Job Options file (File» New» Output Job File). See Setting up the Project Outputs for more information. 1. Select Project» Project Options. The Options for Project dialog displays. 3-14

63 Design capture, simulation and layout an introductory tutorial All project-related options are set up through this dialog. Checking the electrical properties of your schematic Schematic diagrams in DXP are more than just simple drawings they contain electrical connectivity information about the circuit. You can use this connectivity awareness to verify your design. When you compile a project, DXP checks for errors according to the rules set up in the Error Reporting and Connection Matrix tabs and any violations generated will display in the Messages panel. Setting up Error Reporting The Error Reporting tab in the Options for Project dialog is used to set up design drafting checks. The Report Mode is the level of severity of a violation. If you wish to change a Report Mode, click on a Report Mode next to the violation you wish to change and choose the level of severity from the dropdown list. For this tutorial we will use the default settings. Setting up the Connection Matrix The Connection Matrix tab (Options for Project dialog) displays the severity of an error type that is produced when error reporting is run to check electrical connections within the design, i.e. connections between pins, ports and sheet entries. The matrix gives a graphical representation of different types of connection points on a schematic and whether they are allowable or not. For example, look down the entries on the right side of the matrix diagram and find Output Pin. Read across this row of the matrix till you get to the Open Collector Pin column. The square where they intersect is orange indicating that an Output Pin connected to an Open Collector Pin on your schematic will generate an error condition when the project is compiled. 3-15

64 Design capture, simulation and layout an introductory tutorial You can set each error type with a separate error level, e.g. from no report at all through to a fatal error. Right-click to see the menu options to control the entire matrix. To make changes to the Connection Matrix: 1. Click on the Connection Matrix tab in the Options for Project dialog. 2. Click on the box that is at the intersection of two types of connection, e.g. Output Sheet Entry and Open Collector Pin. 3. Click until the box changes to the color of the errors as listed in the legend, e.g. an orange box indicates that an error will be generated if such a connection is found. Our circuit contains only Passive Pins (on resistors, capacitors and the connector) and Input Pins (on the transistors. Let s check to see if the connection matrix will detect unconnected passive pins. 1. Look down the row labels to find Passive Pin. Look across the column labels to find Unconnected. The square where these entries intersect indicates the error condition when a Passive Pin is found to be Unconnected in the schematic. The default is a green square, which indicates that no report will be generated. 2. Click on this intersection box until it turns yellow so that a warning will be generated for unconnected passive pins when we compile the project. We will purposely create an instance of this error to check it later in this tutorial. Setting up the Comparator The Comparator tab in the Options for Project dialog sets which differences between files will be reported or ignored when a project is compiled. For this tutorial, we do not need to show differences between some features that refer to hierarchical schematic designs only, such as rooms. Make sure you do not accidentally ignore components when you meant to ignore component classes! 1. Click on the Comparator tab and find Changed Room Definitions, Extra Room Definitions and Extra Component Classes in the Difference Associated with Components section. 2. Select Ignore Differences from the drop-down list in the Mode column to the right of the these options. 3-16

65 Design capture, simulation and layout an introductory tutorial Now we are ready to compile the project and check for any errors. Compiling the project Compiling a project checks for drafting and electrical rules errors in the design documents and puts you into a debugging environment. We have already set up the rules in the Error Checking and Connection Matrix tabs of the Options for Project dialog. 1. To compile our Multivibrator project, select Project» Compile PCB Project. 2. When the project is compiled, any errors generated will display in the Messages panel. Click on this panel to check for errors. The compiled documents will be listed in the Navigator panel, together with a flattened hierarchy, components and nets listed and a connection model that can be browsed. If your circuit is drawn correctly, the Messages panel should be blank. If the report gives errors, check your circuit and ensure all wiring and connections are correct. We will now deliberately introduce an error into our circuit and recompile the project: 1. Click on the Multivibrator.SchDoc tab at the top of the design window to make the schematic sheet the active document. 3-17

66 Design capture, simulation and layout an introductory tutorial 2. Click in the middle of the wire that connects R1 to the base wire of Q1. Small, square editing handles will appear at each end of the wire and the selection color will display as a dotted line along the wire to indicate that it is selected. Press the DELETE key to delete the wire. 3. Recompile the project (Project» Compile PCB Project to check that any errors are found. The Messages panel will display warning messages indicating you have unconnected pins in your circuit. 4. Double-click on an error or warning in the Messages panel and the Compile Error window will display with details of the violation. From this window, you can click on an error and jump to the violating object in a schematic to check or correct the error. Before we finish this section of the tutorial, let s fix the error in our schematic. 1. Click on the tab of the schematic sheet to make it active. 2. Select Edit» Undo from the menus [shortcut Ctrl+Z]. The wire you deleted previously should now be restored. If you wish to clear messages from the Messages panel, rightclick in the window and select Clear All. 3. To check that the undo was successful, recompile the project (Project» Compile PCB Project to check that no errors are found. The Messages panel should show no errors. 4. Select View» Fit All Objects [shortcut V, F] from the menus to restore your schematic view and save your error-free schematic. 5. Save the schematic and the project file as well. Now we have completed and checked our schematic, it is time to create the PCB. 3-18

67 Design capture, simulation and layout an introductory tutorial Creating a new PCB document Before you transfer the design from the Schematic editor to the PCB editor, you need to create the blank PCB with at least a board outline. The easiest way to create a new PCB design in DXP is to use the PCB Wizard, which allows you to choose from industry-standard board outlines as well as create your own custom board sizes. At any stage you can use the Back button to check or modify previous pages in the wizard. To create a new PCB using the PCB Wizard, complete the following steps: 1. Create a new PCB by clicking on PCB Board Wizard in the New from Template section at the bottom of the Files panel. If this option is not displayed on the screen, close some of the sections above by clicking on the up arrow icons. 2. The PCB Board Wizard opens. The first screen you see is the introduction page. Click the Next button to continue. 3. Set the measure units to Imperial, i.e mils = one inch. 4. The third page of the wizard allows you to select the board outline you wish to use. For this tutorial we will enter our own board size. Select Custom from the list of board outlines and click Next. 5. In the next page you enter custom board options. For the tutorial circuit, a 2 x 2 inch board will give us plenty of room. Select Rectangular and type 2000 in both the Width and Height fields. Deselect Title Block & Scale, Legend String and Dimension Lines. Click Next to continue. 6. This page allows you to select the number of layers in the board. We will need two signal layers and no power planes. Click Next to continue. 7. Choose the via styles used in the design by selecting Thru-hole vias only and click Next. 8. The next page allows you to set the component/track technology (routing) options. Select the Through-hole components option and set the number of tracks between adjacent pads to One Track. Click Next. 3-19

68 Design capture, simulation and layout an introductory tutorial 9. The next page, Track/Via Sizes, allows you to set up some of the design rules that apply to your board. Leave the options on this screen set to their defaults. Click the Next button to continue. 10. Click Finish to close the Wizard. 11. The PCB Wizard has now collected all the information it needs to create your new board. The PCB Editor will now display a new PCB file named PCB1.PcbDoc. 12. The PCB document displays with a default sized white sheet and a blank board shape (black area with grid). To turn it off, select Design» Board Options and deselect Display Sheet in the Board Options dialog. You can add your own border, grid reference and title block from other PCB templates supplied with DXP. For more information about using board shapes, sheets and templates, see the Board Shapes and Sheets tutorial. 13. Now the sheet has been turned off, display the board shape only by selecting View» Fit Board [shortcut V, F]. 14. The PCB document is automatically added (linked) to the project and is listed under PCBs beneath the project name in the Projects tab. For more tutorials, press F1 to access the DXP Help and Online Documentation system and click on the Articles & Tutorials link. 15. Rename the new PCB file (with a.pcbdoc extension) by selecting File» Save As. Navigate to a location where you would like to store the PCB on your hard disk, type the name Multivibrator.PcbDoc in the File Name field and click on Save. 3-20

69 Design capture, simulation and layout an introductory tutorial Adding a new PCB to a project If the PCB you want to add to a project file has been opened as a Free Document, right-click on the PCB document in the Free Documents section of the Projects panel and select Add to Project. The PCB is now listed under PCBs beneath the project in the Projects tab and is linked to the project file. Transferring the design Before transferring the schematic information to the new blank PCB, make sure all the related libraries for both schematic and PCB are available. Since only the default installed integrated libraries are used in this tutorial, the footprints will already be included. Once the project has been compiled and any errors in the schematic fixed, use the Update PCB command to generate ECOs that will transfer the schematic information to the target PCB. Updating the PCB To send the schematic information to the target PCB in your project: 1. Open the schematic document, Multivibrator.SchDoc. 2. Select Design» Update PCB (Multivibrator.PcbDoc). The project compiles and the Engineering Change Order dialog displays. 3. Click on Validate Changes. If all changes are validated, the green ticks appear in the Status list. If the changes are not validated, close the dialog, check the Messages panel and clear any errors. 4. Click on Execute Changes to send the changes to the PCB. When completed, the Status changes to Done. You can create a report of ECOs to print out by clicking on the Report Changes button. 5. Click Close and the target PCB opens with components positioned ready for placing on the board. Use the shortcut keys V, D (View Document) if you cannot see the components in your current view. Figure 4. The components next to the board, ready for positioning. 3-21

70 Design capture, simulation and layout an introductory tutorial Designing the PCB Now we can start placing the components on the PCB and routing the board. Setting up the PCB workspace Before we start positioning the components on the board, we need to set up the PCB workspace, such as the grids, layers and design rules. Grids We need to ensure that our placement grid is set correctly before we start positioning the components. All the objects placed in the PCB workspace are aligned on a grid called the snap grid. This grid needs to be set to suit the routing technology that you intend to use. Our tutorial circuit uses standard imperial components that have a minimum pin pitch of 100mil. We will set the snap grid to an even fraction of this, say 50 or 25mil, so that all component pins will fall on a grid point when placed. Also, the The PCB Editor supports imperial and metric units. Select View» Toggle Units to switch. track width and clearance for our board are 12mil and 13mil respectively (the default values used by the PCB Board Wizard), allowing a minimum of 25mil between parallel track centers. The most suitable snap grid setting would, therefore, be 25mil. To set the snap grid, complete the following steps: 1. Select Design» Board Options [shortcut D, O] to open the Board Options dialog. 2. Set the value of the Snap X, Snap Y, Component X and Component Y fields of the dialog to 25mil using the drop-down lists or typing in the value. Note that this dialog is also used to define the electrical grid. The electrical grid operates when you place an electrical object, it overrides the snap grid and snaps electrical objects together. Click OK to close the dialog. Let s set some other options that will make positioning components easier. 1. Select Tools» Preferences from the menus [shortcut T, P] to open the Preferences dialog. In the Editing Options section of the Options tab, make sure the Snap to Center option is checked. This ensures that when you grab a component to position it, the cursor is set to the component s reference point. 2. Click the Display tab in the Preferences dialog to make it active. In the Show section of this tab, uncheck the Show Pad Nets, Show Pad Numbers and Via Nets options. In the Draft Thresholds section of this dialog, check the Strings field is 4 pixels and click OK to close the dialog. Defining the layer stack and other non-electrical layers If you look at the bottom of the PCB workspace, you will notice a series of layer tabs. The PCB Editor is a multi-layered environment and most of the editing actions you perform will be on a particular layer. Select Design» Board Layers & Colors [shortcut L] to display the Board Layers & Colors dialog where you can display, add, remove and rename and set the colors of the layers. 3-22

71 Design capture, simulation and layout an introductory tutorial There are three types of layers in the PCB Editor: Electrical layers these include the 32 signal layers and 16 plane layers. Electrical layers are added to and removed from the design in the Layer Stack Manager, select Design» Layer Stack Manager to display this dialog. Mechanical layers there are 16 general purpose mechanical layers for defining the board outline, placing dimensions on, including fabrication details on, or any other mechanical details the design requires. These layers can be selectively included in print and Gerber output generation. You can add, remove and name mechanical layers in the Board Layers & Colors dialog. Special layers these include the top and bottom silkscreen layers, the solder and paste mask layers, drill layers, the Keep-Out layer (used to define the electrical boundaries), the multilayer (used for multilayer pads and vias), the connection layer, DRC error layer, grid layers and hole layers. The display of these special layers is controlled in the Board Layers & Colors dialog. Layer Stack Manager The tutorial is a simple design and can be routed as a single-sided or double-sided board. If the design was more complex, you would add more layers in the Layer Stack Manager. 1. Select Design» Layer Stack Manager [shortcut D, K] to display the Layer Stack Manager dialog. 3-23

72 Design capture, simulation and layout an introductory tutorial 2. New layers and planes are added below the currently selected layer. Layer properties, such as copper thickness and dielectric properties are used for signal integrity analysis. Click OK to close the dialog. The new board has opened with many more layers enabled than you will use, so let s turn off all the unnecessary layers. To turn off layers, complete the following steps: 1. Press the L shortcut key to display the Board Layers & Colors dialog. 2. Click on Used On to disable all layers except those that have something on them. 3. Make sure the four Mask layers and the Drill Drawing layer will not display by checking there is no tick in the Show button next to their layer names. Click OK to close the dialog. Setting up new design rules The DXP s PCB editor is a rules-driven environment. This means that as you work in the PCB editor and perform actions that change the design, such as placing tracks, moving components, or autorouting the board, the PCB editor constantly monitors each action and checks to see if the design still complies with the design rules. If it does not, then the error is immediately highlighted as a violation. Setting up the design rules before you start working on the board allows you to remain focused on the task of designing, confident in the knowledge that any design errors will immediately be flagged for your attention. The design rules fall into 10 categories and are further divided into design rule types. The design rules cover electrical, routing, manufacturing, placement and signal integrity requirements. We will now set up new design rules to specify the width that the power nets must be routed. To set up these rules, complete the following steps: 1. With the PCB as the active document, select Design» Rules from the menus. 2. The PCB Rules and Constraints Editor dialog will appear. Each category of rules is displayed in the Design Rules panel (left hand side) of the dialog. Double-click on the Routing category to expand 3-24

73 Design capture, simulation and layout an introductory tutorial the category and see the related routing rules. Then double-click on Width to display the width rules available. 3. Click once on each rule in the Design Rules panel to select it. As you click on each rule, the right hand side of the dialog displays the rule s scope (what you want this rule to target) in the top section and the rule s constraints in the bottom section. These rules are either defaults, or have been set up by the Board Wizard when the new PCB document was created. 4. Click on the Width rule to display its scope and constraints. This rule applies to the entire board (All). 3-25

74 Design capture, simulation and layout an introductory tutorial One of the powerful features of DXP s design rule system is that multiple rules of the same type can be defined, each targeting different objects. The exact set of objects that each rule targets is defined by that rule s scope. The rule system uses a pre-defined hierarchy to work out which rule to apply to each object. For example, you could have a width constraint rule for the whole board (meaning all tracks must be this width), a second width constraint rule for the ground net (this rule overrides the previous rule), and a third width constraint rule for a particular connection on the ground net (which overrides both of the previous rules). Rules are displayed in their order of priority. Currently there is one width constraint rule for your design, which applies to the whole board (width = 12 mil). We will now add a new width constraint rule for the 12V and GND nets (width = 25 mil). To add new width constraint rules, complete the following steps: 1. With the Width category selected in the Design Rules panel, right-click and select New Rule to add a new width constraint rule set up to target the 12V net only. A new rule named Width_1 appears. Click on the new rule in the Design Rules panel to modify the scope and constraints. 2. Type 12V or GND in the Name field. The name will refresh in the Design Rules panel when you click back in the Design Rules panel when you have finished setting the rule. 3. Next we set the rule s scope using the Query Builder but you can always type in the scope directly if you know the correct syntax. If your query is more complicated, click on the Advanced button and use the Query Helper. 4. Click on the Query Builder button to open the Building Query from Board dialog. 5. Click on Add first condition and select Belongs to Net from the drop-down list. In the Condition Value field, click and select the net 12V from the list. The Query Preview now reads InNet ( 12V ). 6. Click on Add another condition to widen the scope to include the GND net. Select Belongs to Net and GND as the Condition Value. 3-26

75 Design capture, simulation and layout an introductory tutorial 7. Change the operator by clicking on the operator AND and then select OR from the drop-down list. Check that the query preview reads InNet( 12V ) OR InNet( GND ). 8. Click OK to close the Building Query from Board dialog. The scope in the Full Query section has now been updated with the new query. 9. In the bottom section of the PCB Rules and Constraints Editor dialog, change the Minimum, Preferred and Maximum width fields to 25mil by clicking on the old constraints text (10mil) and typing in the new values. Note that you must set the Maximum width field first before you can change the Minimum value. The new rule is now set up and will save when you choose another rule in the Design Rules panel or close the dialog. 10. Finally, click to edit the original Board scope width rule named Width and confirm that the Minimum, Maximum and Preferred width fields are all set to 12mil. Click OK to close the PCB Rules and Constraints Editor dialog. When you route the board manually or using the autorouter, all tracks will be 12mils wide, except the GND and 12V tracks which will be 25mils. Positioning the components on the PCB Now we can start to place the components in their right positions. 1. Press the V, D shortcut keys to zoom in on the board and components. 3-27

76 Design capture, simulation and layout an introductory tutorial 2. To place the connector Y1, position the cursor over the middle of the outline of the connector, and click-and-hold the left mouse button. The cursor will change to a cross hair and jump to the reference point for the part. While continuing to hold down the mouse button, move the mouse to drag the component. 3. Position the footprint towards the left-hand side of the board (ensuring that the whole of the component stays within the board boundary), as shown in Figure 5. The connection lines are automatically re-optimized as you move a component. In this way you can use the connection lines as a guide to the optimum position and orientation of the component as you place it. Figure 5. Components placed on the PCB 4. When the component is in position, release the mouse button to drop it into place. Note how the connection lines drag with the component. 5. Reposition the remaining components, using Figure 5 as a guide. Use the SPACEBAR key as necessary to rotate components as you drag them, so that the connection lines are as shown in Figure 5. Don t forget to re-optimize the connection lines as you position each component. Component text can be repositioned in a similar fashion click-and-hold to drag the text and press the SPACEBAR to rotate it. DXP also includes powerful interactive placement tools. Let s use these to ensure that the four resistors are correctly aligned and spaced. 1. Holding the SHIFT key, left-click on each of the four resistors to select them. A shaded selection box will display around each of the selected components in the color set for the system color called Selections. To change this selection color, select Design» Board Layers & Colors [shortcut L]. 2. Click on the Align Components by Top Edges button on the Component Placement toolbar. The four resistors will align along their top edge. 3-28

77 Design capture, simulation and layout an introductory tutorial 3. Now click on the Make Horizontal Spacing of Components Equal button on the Component Placement toolbar. 4. Click elsewhere in the design window to deselect all the resistors. The four resistors are now aligned and equally spaced. Changing a footprint Now that we have positioned the footprints, the capacitor footprint appears too big for our requirements! Let s change the capacitor footprint to a smaller one. 1. First we will browse for a new footprint. Click on the Libraries panel and select Miscellaneous Devices.IntLib from the Libraries list. Click on Footprints to display footprints available in the active library. We want a smaller radial type footprint, so type rad in the Filter field. Click on the Footprint names to see the footprints associated with them. The footprint RAD-0.1 will do the job. 2. Double-click on the capacitors and change the Footprint field to RAD-0.1 in the Component dialog. You can simply type in the new footprint name, or click on the button and select a footprint from the Browse Libraries dialog. Click OK and the new footprints are displayed on the board. Reposition the designators as required. 3. Your board should now look like the PCB design above. With everything positioned, it s time to lay some tracks! Manually routing the board Routing is the process of laying tracks and vias on the board to connect the components. DXP makes the job of routing easy by providing a number of sophisticated manual routing tools as well as the new powerful Situs topological autorouter, which optimally routes the whole or part of a board at the touch of a button. While autorouting provides an easy and powerful way to route a board, there will be situations where you will need exact control over the placement of tracks or you may want to route the board manually just for the fun of it! In these situations you can manually route part or all of your board. In this section of the tutorial, we will manually route the entire board single-sided, with all tracks on the bottom layer. 3-29

78 Design capture, simulation and layout an introductory tutorial We will now place tracks on the bottom layer of the board, using the ratsnest connection lines to guide us. In DXP, tracks on a PCB are made from a series of straight segments. Each time there is a change of direction, a new track segment begins. Also, by default DXP constrains tracks to a vertical, horizontal or 45 orientation, allowing you to easily produce professional results. This behavior can be customized to suit your needs, but for this tutorial we will stay with the default. 1. Enable and show the Bottom Layer by pressing the shortcut key L to display the Board Layers & Colors dialog. Click on the Show checkbox next to Bottom Layer in the Signal Layers section. Click OK and the Bottom Layer tab is displayed in the design window. First click starts you placing a track. Now move the cursor toward the bottom pad on R1. 2. Select Place» Interactive Routing from the menus [shortcut P, T] or click the Interactive Routing button on the Placement toolbar. The cursor will change to a cross hair indicating you are in track placement mode. 3. Examine the layer tabs that run along the bottom of the document workspace. The Top Layer tab should currently be active. To switch to the bottom layer without dropping out of track placement mode, press the * key on the numeric keypad. This key toggles between the available signal layers. The Bottom Layer tab should now be active. 4. Position the cursor over the bottom-most pad on the connector Y1. Left-click or press ENTER to anchor the first point of the track. 5. Move the cursor towards the bottom pad of the resistor R1. Note how the track is laid. By default, tracks are constrained to vertical, horizontal or 45 directions. Also note that the track has two segments. The first (coming from the starting pad) is solid blue. This is the track segment you are actually placing. The second segment (attached to the cursor) is called the look-ahead segment and is drawn in outline. This segment allows you to look ahead at where the next track segment you lay could be positioned so that you can easily work your way around obstacles, maintaining a 45 /90 track orientation. 6. Position the cursor over the middle of the bottom pad Note how the connection line guides you to the target pad. Segment you are currently placing Look-ahead segment Position the cursor over the pad on R1. Click a second time to place this track segment. Third click to place the next track segment. You have now routed this connection. 3-30

79 Design capture, simulation and layout an introductory tutorial of resistor R1 and left-click or press the ENTER key. Note that the first track segment turns blue, indicating that it has been placed on the Bottom Layer. Move the cursor around a little and you will see that you still have two segments attached to the cursor: a solid blue segment that will be placed with the next mouse click and an outlined look-ahead segment to help you position the track. 7. Re-position the cursor over the bottom pad of R1. You will have a solid blue segment extending from the previous segment to the pad. Left-click to place the solid blue segment. You have just routed the first connection. 8. Move the cursor to position it over the bottom pad of resistor R4. Note a solid blue segment extends to R4. Left-click to place this segment. You may find using a larger crosshair cursor useful when placing tracks. To change the cursor size, select Tools» Preferences. Select Large 90 from the Cursor Type list in the Options tab of the Preferences dialog. 9. Now move the cursor to the bottom pad of resistor R3. Note that this segment is not solid blue, but drawn in outline indicating it is a look-ahead segment. This is because each time you place a track segment the mode toggles between starting in a horizontal/vertical direction and starting at 45. Currently it is in the 45 mode. Press the SPACEBAR key to toggle the segment start mode to horizontal/vertical. The segment will now be drawn in solid blue. Left-click or press the ENTER key to place the segment. 10. Move the cursor to the bottom of resistor R2. Once again you will need to press the SPACEBAR key to toggle the segment start mode. Left-click or press the ENTER key to place the segment. 11. You have now finished routing the first net. Right-click or press the ESC key to indicate that you have finished placing this track. The cursor will remain a cross hair, indicating that Note that the look-ahead segment is clipping (no longer attached to the cursor). The PCB Editor will prevent you from accidentally placing a track across another object that would cause a violation. This connection must be routed around the capacitor. you are still in track placement mode, ready to place the next track. Press the END key to redraw the screen so that you can clearly see the routed net. 12. You can now route the rest of the board in a similar manner to that described in the previous steps. Figure 6 shows the manually routed board. 3-31

80 Design capture, simulation and layout an introductory tutorial Figure 6. Manually routed board, with tracks placed on the bottom layer. 13. Save the design [shortcut F, S or Ctrl+S]. Tips for placing tracks Keep in mind the following points as you are placing the tracks: Left-clicking the mouse (or pressing the ENTER key) places the track segment drawn in solid color. The outlined segment represents the look-ahead portion of the track. Placed track segments are shown in the layer color. Press the SPACEBAR key to toggle between the start horizontal/vertical and start 45 modes for the track segment you are placing. Press the END key at any time to redraw the screen. Press the V, F shortcut keys at any time to redraw the screen to fit all objects. Press the PAGEUP and PAGEDOWN keys at any time to zoom in or out, centered on the cursor position. Use the mouse wheel to pan left and right. Hold the Ctrl key down to zoom in and out with the mouse wheel. Press the BACKSPACE key to unplace the last track segment. Right-click or press ESC when you have finished placing a track and want to start a new one. You cannot accidentally connect pads that should not be wired together. DXP continually analyzes the board connectivity and prevents you from making connection mistakes or crossing tracks. To delete a track segment, left-click on it to select it. The segment s editing handles will appear (the rest of the track will be highlighted). Press the DELETE key to clear the selected track segment. 3-32

81 Design capture, simulation and layout an introductory tutorial Re-routing is easy in DXP simply route the new track segments, when you right-click to finish the old redundant track segments will automatically be removed. When you have finished placing all the tracks on your PCB, right-click or press the ESC key to exit placement mode. The cursor will change back to an arrow. Congratulations! You have manually routed your board design. Automatically routing the board To see how easy it is to autoroute with DXP, complete the following steps: 1. First, un-route the board by selecting Tools» Un-Route» All from the menus [shortcut U, A]. 2. Select Autoroute» All [shortcut A, A]. The Situs Routing Strategies dialog displays. Click on Route All. The Messages panel displays the process of the autorouting. It s as simple as that! DXP s autorouter provides results comparable with that of an experienced board designer and because DXP routes your board directly in the PCB window, there is no need to wrestle with exporting and importing route files. 3. Select File» Save [shortcut F, S] to save your board. Note that the tracks placed by the autorouter appear in two colors: red indicates that the track is on the top signal layer of the board and blue indicates the bottom signal layer. The layers that are used by the autorouter are specified in the Routing Layers design rule, which was set up by the PCB Board Wizard. You will also notice that the two power net tracks running from the connector are wider, as specified by the two new Width design rules you set up. Don t worry if the routing in your design is not exactly the same as Figure 7; the component placement will not be exactly the same, so neither will be the routing. Figure 7. Fully autorouted board 3-33

82 Design capture, simulation and layout an introductory tutorial Because we originally defined our board as being double-sided in the PCB Board Wizard, you could manually route your board double-sided using both the top and bottom layers. To do this, un-route the board by selecting Tools» Un-Route» All from the menus [shortcut U, A]. Start routing as before, but use the * key to toggle between the layers while placing tracks. DXP will automatically insert vias if necessary when you change layers. Verifying your board design DXP provides a rules-driven environment in which to design PCBs and allows you to define many types of design rules to ensure the integrity of your board. Typically, you set up the design rules at the start of the design process and then verify that the design complies with the rules at DXP supports the end of the design process. hierarchical design rules. Earlier in the tutorial we examined the routing design rules and added a new You can set any number of rules of the same width constraint rule. We also noted that there were already a number of rules class, each with a that had been created by the PCB Board Wizard. defined scope. The rule s priority determines To verify that the routed circuit board conforms to the design rules, we will now the rule s precedence. run a Design Rule Check (DRC): 1. Choose Design» Board Layers & Colors [shortcut L] and ensure that Show button next to the DRC Error Markers option in the System Colors section is checked (ticked) so that the DRC error markers will be displayed, if any. 2. Choose Tools» Design Rule Check from the menus [shortcut T, D]. Both the on-line and batch DRC options are configured in the Design Rule Checker dialog. Click on a category to see all the rules. 3. Leave all options at their defaults and click the Run Design Rule Check button. The DRC will run and the report file Multivibrator.DRC opens. The results will also be displayed in the Messages 3-34

83 Design capture, simulation and layout an introductory tutorial panel. Click back into the PCB document and you will see that the transistor pads are highlighted in green, indicating a design rule violation. 4. Look through the errors list in the Messages panel. It lists any violations that occur in the PCB design. Notice that there are four violations listed under the Clearance Constraint rule. The details show that the pads of transistors Q1 and Q2 violate the 13mil clearance rule. 5. Double-click on an error in the Messages panel to jump to its location on the PCB. Normally you would set up the clearance constraint rules before laying out your board, taking account of routing technologies and the physical properties of the devices. Let s analyze the error then review the current clearance design rules and decide how to resolve this situation. To find out the actual clearance between the transistor pads: 1. With the PCB document active, position the cursor over the middle of one of the transistors and press the PAGE UP key to zoom in. 2. Select Reports» Measure Primitives [shortcut R, P]. The cursor will change to a cross hair. 3. Position the cursor over the middle of the left pad on the transistor and left-click or press ENTER. Because the cursor is over both the pad and the track connected to it, a menu will pop up to allow you to select the desired object. Select the transistor pad from the popup menu. 4. Position the cursor over the center of the middle transistor pad and left-click or press ENTER. Once again, select the pad from the popup menu. An information box will open showing the minimum distance between the edges of the two pads is 10.63mil. 5. Close the information box, then right-click or press ESC to exit the measurement mode and then use the V, F shortcut to re-zoom the document. Let s look at the current clearance design rules. 1. Select Design» Rules from the menus [shortcut D, R] to open the PCB Rules and Constraints Editor dialog. Double-click on the Electrical category to display all electrical rules in the right side of the dialog. Double-click on the Clearance type (listed in the right side) and then click on Clearance to open it. The region at the bottom of the dialog will contain a single rule, specifying that the minimum clearances for the whole board are 13mil. The clearance between the transistor pads is less than this, which is why they generate a violation when we run a DRC. We now know the minimum distance between transistor pads is a little over 10mil, so let s set up a design rule that allows the clearance constraint to be 10mil for the transistors only. 2. Select the Clearance type in the Design Rules panel, right-click and select New Rule to add a new clearance constraint rule. 3. Click on the new Clearance rule, Clearance_1. In the Constraints section of the resulting dialog, set the Minimum Clearance to 10mil. 3-35

84 Design capture, simulation and layout an introductory tutorial 4. Click on Advanced (Query) and then click on Query Helper to construct the query from the Memberships Checks. Alternatively, simply type in the following query in the Query field for the first object: HasFootprintPad( BCY-W3/D4.7, * ) The * (asterisk) indicates any pad on the footprint named BCY-W3/D Leave the scope for the second object at ALL and click OK. Click Close to close the PCB Rules and Constraints Editor dialog. 6. You can now re-run the DRC from the Design Rules Checker dialog (Tools» Design Rule Check) by clicking the Run Design Rule Check button. There should be no rule violations. 7. Save your completed PCB and the project file. Well done! You have completed the PCB layout and are ready to produce the output documents. Setting up the Project Outputs Project outputs, such as printing and output files, are set up in Output Job files which can be copied and pasted into other projects and modified as required. Alternatively, you can select individual commands from the File menu to set up default job options, such as Default Prints. 1. Select File» New» Output Job File, select the output you wish to set up and double-click to modify the setups of that output. Make all necessary configurations and save the output jobs file. 2. If you want the outputs to be sent to individual folders according to the output type, select Project» Project Options, click on the Options tab and click on Use separate folder for each output type and click OK. Printing Once the layout and routing of the PCB is complete, you are ready to produce the output documentation. This documentation might include a manufacturing drawing detailing the fabrication information and assembly drawings detailing component location information and loading order. To produce these drawings, DXP includes a sophisticated printing engine that gives you complete control over the printing process. You can define precisely what mix of PCB layers you want to print, preview the drawings (called printouts) and set the scaling and orientation to see exactly how it will look on the page before you print it. Now we will create a print preview using default output settings and then change the setups. 1. Select File» Print Preview from the PCB menus. The PCB will be analyzed and a default printout displayed in the print preview window. Click on Close. 2. To examine the set of PCB layers that are included in the printout or to change the default print options, select File» Default Prints. The Default Prints tab of the Options for Project dialog displays. 3-36

85 Design capture, simulation and layout an introductory tutorial This tab shows that when you print the PCB, the default print will be a Composite Drawing as this is the default option enabled for PCB printing. 3. Select Composite Drawing from the Documentation Outputs section and click on the Configure button. The PCB Printout Properties dialog displays. You can add or delete layers to be printed using the right-click menu options. 4. Double-click on a layer name to display the Layers Properties dialog where you can set the print type - full, draft or hide (off) -drill layers and drill drawing symbols. Click OK to close the dialog. 5. Click on Preferences to display the PCB Print Preferences dialog to set the color and gray scales, mechanical layers to include in the printout and any font substitutions. Close the dialog. 3-37

86 Design capture, simulation and layout an introductory tutorial 6. While we are in still the Options for Project dialog, we will change the layer configurations for the Combination Drill Guide. Select and enable Drill Drawing/Guides in the Fabrication Outputs section and click on the Configure button. By default, this printout includes both the drill guide, a system layer which includes a small cross at each drill site, and the drill drawing layer, which includes a special shape at each drill site, unique for each drill size. The Drill Guide layer is not required in a typical drill drawing, so to remove it, right-click on the Drill Guide layer in the Printouts & Layers column and select Delete. Click OK. 7. Now click on Page Setup and then Preview to view your drill drawing. You can then click on Print to display your printer setups and then click OK to send your drawing to the specified printer. 8. When in the Print Preview, select Copy from the right-click menu to copy the current printout to the clipboard and paste it into another Windows application. Right-Click and select Export Metafile to export the printouts to the hard disk as EMF files. Click Close to close the print preview window. 9. To change the target printer and set the page orientation and scaling, you can select the Page Setup button in the Options for Project dialog (or File» Page Setup from the menus). Choose your preferred printer and check the printer page is set to Landscape. 10. When you have completed your setups, close all open dialogs. Manufacturing output files The final phase of the PCB design process is to generate the manufacturing files. The set of files that are used to manufacture and fabricate the PCB include Gerber files, NC drill files, pick and place files, a bill of materials and testpoint files. Output job files can be set by selecting File» New» Output Job File or you can create outputs through individual commands on the File» Fabrication Outputs menu. The setups for the manufacturing documents are stored as part of the project file. 3-38

87 Design capture, simulation and layout an introductory tutorial Generating Gerber files Each Gerber file corresponds to one layer in the physical board the component overlay, top signal layer, bottom signal layer, the solder masking layers and so on. It is advisable to consult with your PCB manufacturer to confirm their requirements before generating the Gerber and NC drill files required to fabricate your design. To create the manufacturing files for the tutorial PCB: 1. Make the PCB the active document, then select File» Fabrication Outputs»Gerber files. The Gerber Setup dialog displays. If you do not want output files to automatically open when they are created, select Project» Project Options, click on the Options tab and deselect Open Outputs after compile. 2. Click on the Layers tab to select which layers to use. Click on Plot Layers and select Used On. Click OK to accept the other default settings. 3. The Gerber files are produced and CAMtastic! opens to display the files. The Gerber files are stored in the Project Outputs folder which is automatically created in the folder where your project files reside. Each file has the file extension added that corresponds to the layer name, e.g. Multivibrator.GTO for Gerber Top Overlay. These are added to the Projects panel under Generated Documents. Creating a Bill of Materials 1. To create a Bill of Materials, click on the PCB document, Multivibrator.PcbDoc and select Reports» Bill of Materials. The Bill of Materials for PCB dialog displays. 3-39

88 Design capture, simulation and layout an introductory tutorial 2. Use this dialog to build up your BOM. Click on Show next to the columns you want to add to the report. 3. Select and drag a column heading from Other Columns to Grouped Columns to group components by that column heading in the BOM. For example, to group by the Footprint column, select Footprints in the Other Columns section and drag it into the Grouped Column section. The list will be sorted accordingly. 4. Click on Report to display a print preview of your BOM. This preview can then be printed using the Print button or exported to a file format, such as.xls for Microsoft Excel, using the Export button. Close the dialogs. Congratulations! You have completed the PCB design process. Simulating the design DXP allows you to run a vast array of circuit simulations directly from a schematic. In the following sections of the tutorial we will simulate the output waveforms produced by our multivibrator circuit. 3-40

89 Design capture, simulation and layout an introductory tutorial Setting up for simulation Before we can run a simulation we need to add a few things to our circuit: a voltage source to power the multivibrator; a ground reference for the simulations and some net labels on the points of the circuit where we wish to view waveforms. 1. Click on the Multivibrator.SchDoc tab at the top of the window to make the schematic the active document. 2. We must replace the connector with a voltage source. To delete the connector, click once on the body of the connector to select it (a dotted selection box will appear around the connector), then press the DELETE key on the keyboard. 3. At the moment there is not enough room for the voltage source, so we ll move the free ends of the wires. To move the dangling end of the 12V wire, click once on the wire to select it. When the small square editing handles appear, click once on the handle on the free end of the wire, then move the handle up almost to where the wire changes direction (but not all the way up). Click again to drop the handle. 4. Repeat this process for the dangling end of the GND wire, moving it towards the bottom of the sheet. 5. Select View» Toolbars» Simulation Sources to display the Simulation Sources toolbar. 6. Click the +12V source button on the Simulation Sources toolbar. A source symbol will appear floating on the cursor. Press the TAB key on the keyboard to edit its attributes. In the Component Properties dialog, change the Designator field to V1. Click OK to close the dialog and then place the source between the dangling ends of the 12V and GND wires. 7. Using the same technique you used to move the dangling ends of the 12V and GND wires apart, move them again to attach each wire end to either end of the voltage source, as shown in Figure 9 (simulation-ready schematic). 3-41

90 Design capture, simulation and layout an introductory tutorial The electrical hot spot of a net label is the bottom left corner, so ensure that this corner touches the wire and a red cross appears. Figure 9. Simulation-ready schematic Our last task before running a simulation is to place net labels at appropriate points on the circuit so we can easily identify the signals we wish to view. In the tutorial circuit, the points of interest are the base and collectors of the two transistors. 1. Select Place» Net Label from the menus [shortcut P, N]. Press the TAB key to edit the net label attributes. In the Net Label dialog, set the Net field to Q1B and close the dialog. 2. Position the cursor over the wire coming from the base of Q1. See Figure 9 for net label placement. Left-click or press ENTER to place the net label on the wire. 3. Press the TAB key and change the Net field to Q1C. 4. Position the cursor over the wire coming from the collector of Q1 and left-click to place the second net label. 5. Similarly, place net labels with designators Q2B and Q2C on the base and collector wires of Q2 respectively. 6. When you have finished placing net labels, right-click, or press ESC, to exit placement mode. 7. To save your simulation-ready circuit with a different name to that of your original schematic, select File» Save Copy As [shortcut F, A] and type Multivibrator simulation.schdoc in the Save Copy As dialog. Remove the Multivibrator.SchDoc from the project and add the new document Multivibrator simulation.schdoc to the project and save. Running a transient analysis Your schematic now has all the necessary additions, so let s set up a transient analysis of the circuit. In our tutorial circuit, the RC time constant is 100k x 20n = 2 milliseconds. To view five cycles of the oscillation, we will set up to view a 10ms portion of the waveform. 3-42

91 Design capture, simulation and layout an introductory tutorial 1. With Multivibrator simulation.schdoc open in the Schematic Editor, select Design» Simulate» Mix Sim from the menus to display the Analyses Setup dialog. All the simulation options are set up here. 2. First we will set up the nodes in the circuit that you wish to observe. In the Collect Data For field, select Node Voltage and Supply Current from the list. This option defines what type of data you want calculated during the simulation run. 3. In the Available Signals field, double-click on the Q1B, Q2B, Q1C and Q2C signal names. As you double-click on each one, it will move to the Active Signals field. 4. Make sure the Operating Point Analysis and the Transient/Fourier checkboxes are enabled (ticked) for this analysis. If the Transient/Fourier Analysis Setup does not display automatically, click on the Transient/Fourier analysis name. 5. Check that the Use Transient Defaults option is disabled, so that the Transient Analysis parameters are available. 3-43

92 Design capture, simulation and layout an introductory tutorial 6. To specify a 10ms simulation window, set the Transient Stop Time field to 10m. 7. Now set the Transient Step Time field to 10u, indicating that the simulation should display a point every 10us (giving 1000 display points in all, enough to give an accurate picture of the results). 8. During simulation, the actual timestep is varied automatically to achieve convergence. The Maximum Step field limits the variation of the timestep size, set the Transient Max Step Time to 10u. You are now ready to run a transient simulation. 1. Click the OK button at the bottom of the Analyses Setup dialog to run the simulation. 2. The simulation will be performed, when it is finished you should see output waveforms similar to those shown in Figure 10. Figure 10. Output waveforms from the multivibrator. Congratulations! You have simulated your circuit and displayed its output waveforms. If you like, you can change the values of some of the components on your schematic and re-run the simulation to see the effects. Try changing the value of C1 to 47n (double-click on C1 to edit its attributes) and re-running the transient analysis. The output waveforms will show an uneven mark/space ratio. 3-44

93 Design capture, simulation and layout an introductory tutorial Further explorations This tutorial has introduced you to just some of the powerful features of DXP. We ve captured a schematic, run a transient simulation on the design, and designed and routed a PCB, all with the integrated tools provided in DXP. But we ve only just scratched the surface of the design power provided by DXP. Once you start exploring DXP you will find a wealth of features to make your design life easier. To demonstrate the capabilities of the software, a number of example files are included. You can open these examples in the normal way by selecting File» Open from the menus and then navigating to the \Program Files\Altium\Examples\ folder. As well as the board design examples in this folder, there are a number of sub-folders with examples that demonstrate specific features of DXP. Check out the Circuit Simulation sub-folder to explore DXP s analog and digital simulation capabilities. As well as analog examples that demonstrate various circuit designs, such as amplifiers and power supplies, there are mixed-mode examples, a math function example, and an example that includes linear and non-linear dependent sources and even a vacuum tube example! With faster logic switching and design clock speeds, the quality of the digital signals becomes more important. DXP includes a sophisticated signal integrity analysis tool that can accurately model and analyze your board layout. The signal integrity requirements such as impedance, overshoot, undershoot, and slope are defined as PCB design rules, and then tested during the standard design rule check. If there are nets that you need to analyze in more detail, you can select Tools» Signal Integrity to pass the design to the Signal Integrity Analyzer, where you can perform reflection and cross talk simulations. The results are displayed in an oscilloscope-like waveform analyzer, where you can examine the performance and take measurements directly from the waveforms. Thanks for participating in the DXP introductory tutorial. 3-45

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95 Customizing DXP Resources tutorial 4 Customizing DXP Resources tutorial Customizing DXP resources Customization overview Rearranging the existing menus and toolbars Adding a command to a toolbar or menu Shortcuts to adding commands to existing bars Adding a Group separator to a drop-down menu Deleting commands Delete a custom command Delete a command from one resource Creating a new drop-down menu Creating a new toolbar Duplicating bars Activating toolbars Setting the main menu System level commands Creating a new command Duplicating commands Working with shortcut key tables Restoring menu and toolbar defaults Customizing DXP resources This tutorial covers the following topics on customizing DXP resources: rearranging the existing menus and toolbars adding and deleting toolbar or menu commands creating a new drop-down menu or a new toolbar duplicating and activating toolbars setting the main menu floating main menus and toolbars creating, duplicating and editing commands working with shortcut key tables restoring menu and toolbar defaults. 4-1

96 Customizing DXP Resources tutorial Customization overview Resources in an editor are the menu bars, toolbars and the shortcut key tables. All the commands available from the menus are also available for adding to or deleting from these resources. Behind each resource item, such as a toolbar icon or menu item, there is a pre-packaged process launcher that activates a command when its resource item is selected. The pre-packaged process launchers bundle together the process that runs when the command is selected, plus any parameters, bitmaps (icons), captions (the name of an item that displays on a resource), descriptions and associated shortcut keys. If a process launcher is modified, every linked instance of the command on any bar will be updated. Commands can be customized to meet your own needs. Customizations are stored in the file C:\Documents and Settings\User_name\Application Data\Altium\DXP.rcs. + Rearranging the existing menus and toolbars When the Customizing dialog is open, you can click and drag commands around between the active menus and toolbars. 1. Right-click on a menu bar or a toolbar and select Customize from the drop-down menu. The relevant Customizing dialog displays, e.g. right-clicking on the Schematic Editor menu will display the Customizing Sch Editor dialog. All customization is done while this dialog is displayed. 4-2

97 Customizing DXP Resources tutorial 2. Select the command from an existing menu, submenu or toolbar (a black box around the name or icon shows it is selected) and drag it to its new location on either a menu or toolbar. A black bar will indicate where the command will be added. Adding a command to a toolbar or menu A command can be linked or duplicated when it is added to a bar. A linked command will be updated if the original process launcher is modified. A duplicated command, however, will remain as a copy of the original process launcher and not be updated. Duplicated commands can be modified to create a new command by changing its process launcher properties. See Editing Commands for more details. To add a command to a bar: 1. Right-click on a menu bar or a toolbar and select Customize from the drop-down menu. The relevant Customizing dialog displays. 2. Find the command you wish to add to another bar. The Categories in the Commands tab of the Customizing dialog are the menu and submenu headings sorted alphabetically. By default, the built-in bars (the default menus and toolbars) display in the Commands list. These will show you all the commands installed. You can select and 4-3

98 Customizing DXP Resources tutorial drag these commands to add to another toolbar or menu but you will not be able to edit them from this view. Clicking on a Category will display all the commands associated with that menu bar. 3. Select the command you want to add to a toolbar or menu from the Commands section of the Customizing dialog. 4. With the dialog still open, go to the menu or toolbar that you want to add the command to and right-click to display the Customize drop-down menu. 5. Select Insert Link (to link to the original process launcher) or Insert Duplicate (to create a copy of the command). A line will appear where the insertion will take place and the cursor will change when you place it over anywhere on the bars that you can add a command, as shown below. The cursor changes for a linked command (arrow) and duplicated command (+ sign). 6. Release the mouse button and the command will be added to the menu or toolbar. Shortcuts to adding commands to existing bars With the Customizing dialog open, select the command in a menu or toolbar you want to duplicate or link. Ctrl, click and drag to the new location to Insert Duplicate. Shift+Ctrl, click and drag to the new location to Insert Link. Adding a Group separator to a drop-down menu You can add a line separator above the item in a menu or before an icon in a toolbar. With the Customizing dialog open, right-click on a menu or toolbar item and select Begin Group. Deleting commands You can delete one instance or all instances of a custom Command from menus or toolbars. Note that the default Commands cannot be deleted. 4-4

99 Customizing DXP Resources tutorial Delete a custom command Deleting a customized command stored in the Custom category will delete all instances of the custom command from all resources. 1. Right-click on the main menu bar or a toolbar and select Customize from the drop-down menu. The Customizing dialog displays. 2. Click on the Custom category and select the command you want to delete. 3. Click on the Delete button and click OK to confirm the permanent deletion of the command. All instances of the command will be removed from the bars. Delete a command from one resource If you want to delete just one instance of a command without affecting other instances: 1. Right-click on the menu bar or a toolbar and select Customize from the drop-down menu. The Customizing dialog displays. 2. With the dialog still open, select the command that you want to delete from the actual menu or toolbar. A black box around the item indicates it is selected. 3. Right-click and select Delete. Alternatively, simply click and hold on the menu item or toolbar icon and drag it off its bar. The cursor changes to a cross when you release the mouse button. Creating a new drop-down menu 1. With the Customizing dialog open, place the cursor where you want to add the new menu to appear. It could be added to the main menu or by clicking on an existing command in a menu can be used to create a sub-menu. 2. Right-click and select Insert Drop Down to add a new drop-down menu. The Edit Drop Down Menu dialog displays. 3. Add a new caption (the menu name), a popup key (to quickly access the menu) and a bitmap for an icon (if required) and click OK. The new menu name (caption) displays in the menus. 4-5

100 Customizing DXP Resources tutorial 4. Now, add the commands to your new menu. See Adding a command for details. Creating a new toolbar From the Bars tab of the Customizing Sch Editor dialog, you can select which main menu and toolbars to display, create a new or duplicate toolbar as well as rename, delete or restore toolbars. To create a new blank toolbar: 1. Right-click on a menu or toolbar and select Customize. When the Customizing dialog displays, click on the Bars tab. 2. Click on the New button to create a new bar. A New Toolbar appears in the Bars section. 3. Click on Rename to rename the toolbar. 4. Activate the toolbar by clicking on its selection box. A blank toolbar will appear floating on the screen. 5. Add commands to your new toolbar. See Adding a command for details. Duplicating bars If you want to create a new bar based on an existing toolbar, it is easier to duplicate the original toolbar and edit the commands. 1. Click on the Duplicate button to create a new instance of the selected toolbar. 2. A Copy of xxx appears in the Bars section. Click on Rename to change its title. 3. Add your commands. See Adding a command for details. Activating toolbars Toolbars will only appear on the screen if they are active. 1. Select which toolbars will be active (display) by clicking on the Bars tab in the Customizing dialog. 2. Click on the Is Active box next to the required toolbars until they become checked. Alternatively, position the cursor over a toolbar or menu, right-click and select the required toolbar from the drop-down list. 4-6

101 Customizing DXP Resources tutorial Setting the main menu Nominate which main menu bar will be active (display) by selecting a menu from the Bar to Use as Main Menu drop-down list in the Bars tab in the Customizing dialog. System level commands There is a category in the Customizing dialog named System Level that includes the commands to Toggle Floating Panel Visibility and to Toggle Floating Panel Focus. Any new commands added to this category will become system commands and their shortcut keys can be used in any editor. Creating a new command New commands that are created using the New or Duplicate buttons in the Customizing dialog and are listed in the Custom category of the Commands tab when created. 1. Right-click on a menu or toolbar and select Customize. 2. Click on the New button in the Customizing dialog to create a new command. The New Command dialog displays. 3. Enter the required properties. Click on Browse to find the process required. 4. The Caption will become the name of the command as seen when added to a menu, so make it easily recognizable as a new command. 4-7

102 Customizing DXP Resources tutorial 5. If you require an image to be associated with the new process launcher, click on the button to find a bitmap file. This image (or icon) will display when the new command is added to toolbars, e.g. the Zoom In command uses the Zoomin.bmp bitmap found in the Altium\System\Buttons folder. 6. Add a shortcut key and alternative from the drop-down lists if required and click OK. 7. Click on the Custom category to see the new command in the Command list. 8. Add the new command to the relevant bar(s). See Adding a command for details. Duplicating commands It is often easier to create a new command by duplicating an existing command that is similar and modifying its parameters. To duplicate a Command: 1. Right-click on the main menu bar or a toolbar and select Customize. The Customizing dialog displays. 2. Select the command you wish to duplicate and click on Duplicate to create a new copy of the selected command. 3. Click in the Custom category to see the new command in the Command list. 4. Modify its properties, e.g. add a new parameter and a new caption, and click OK. See Editing commands for more details. 5. Drag the new command onto a toolbar or menu. See Adding a command for details. 6. Click on OK and all resources that use that command will be updated. Working with shortcut key tables A shortcut key table lists all the shortcuts currently available in an editor. Only one shortcut key table can be active per editor, e.g. Schematic Shortcuts is the name of the default shortcut key table for the Schematic Editor. If a shortcut key is changed in a Command, it is updated in the active table automatically. Shortcut key tables can be added, created, deleted or modified in the same way as menus and toolbars. Restoring menu and toolbar defaults To reinstall the original default menus and toolbars and delete customizations: 1. Click on the Bars tab in the Customizing Sch Editor dialog. 2. Select on the bar you wish to restore and click on the Restore button. 3. Click OK to confirm the removal of all customizations from the selected bar. 4-8

103 Creating Components tutorial 5 Creating Components Creating components Creating schematic components Schematic libraries Creating a new schematic library Creating a new schematic component Adding pins to a schematic component Notes on adding pins Setting the schematic component s properties Adding models to the schematic component Search locations for model files Adding footprint models to a schematic component Adding Circuit Simulation models Adding Signal Integrity models Adding component parameters Indirection strings Creating a new schematic component with multiple parts Creating the body of the component Placing lines Drawing an arc Adding pins Creating the new parts Creating an alternate view mode for a part Setting the component s properties Adding components from other libraries Copying multiple components Checking components using Schematic Library reports Component Report Library Report Component Rule Checker Creating PCB component footprints Creating a new PCB Library Using the PCB Component Wizard Manually creating component footprints Placing pads on a new footprint Pad Designators and Paste Arrays Drawing an outline of a new footprint Placing Designator and Comment special strings Adding height to your PCB footprint

104 Creating Components tutorial Creating a footprint with an irregular pad shape Placing the pads Drawing the component outline Checking solder and paste masks Displaying the masks Setting mask expansions by design rules Specifying mask expansions Including routing primitives in component footprints Footprints with multiple connection points on same pin Drawing a footprint with a solder mask Adding footprints from other sources Validating component footprints Creating an integrated library Glossary Creating components The Creating Components tutorial covers the creation of schematic components and PCB footprints using the DXP Library Editors. This tutorial presumes you have a working understanding of the Schematic and PCB environments and are competent with placing and editing components. The example components and libraries used in this tutorial are available for you to look over in the Altium\Examples\Tutorials folder. In this tutorial, we will cover the following topics: creating new libraries creating schematic components with single and multiple parts checking the components using Schematic Library Editor reports creating PCB component footprints manually and using the Component Wizard checking the components using PCB Library Editor reports creating an integrated library of the new components and models. Creating schematic components The Schematic Library Editor is provided in DXP to create and modify schematic components and manage component libraries. It is similar to the Schematic Editor and shares the same graphical objects, with the addition of the Place Pin tool. Schematic components can be made up of parts that are separately selectable and are associated with their nominated PCB footprint components, which are stored in the PCB libraries or integrated libraries, during synchronization. Components can be created in the Schematic Editor and copied and pasted into an open schematic library to create a new component, or you can use the drawing tools in the Schematic Library Editor. 5-2

105 Creating Components tutorial Schematic libraries Schematic libraries (.SchLib) in DXP are included as the essential part of the integrated libraries (.IntLib) supplied in the Altium\Library folder. To create a schematic library out of an integrated library, open the integrated library and choose Yes to extract the source libraries that can then be opened for editing. For more information, refer to the Integrated Libraries tutorial. You can also create a schematic library of all the components that have been placed in the schematic documents of the active project using the Design» Make Project Library command. Creating a new schematic library Before we start creating components, let s make a new schematic library to store them in. To create a new schematic library, complete the following steps. 1. Select File» New» Schematic Library. A new library, named Schlib1.SchLib, is created and an empty component sheet, Component_1, displays in the design window. 2. Rename the library file to Schematic Components.SchLib, for example, by selecting File» Save As. Browse to the folder required, rename the file with a.schlib extension and click Save. 3. Click on the Library Editor tab to open the SCH Library panel. 5-3

106 Creating Components tutorial Creating a new schematic component To create a new schematic component in an existing library, you would normally select Tools» New Component, but since a new library always contains one empty component sheet, we ll simply rename Component_1 to get started on creating our first component, an NPN transistor. 1. Select Component_1 from the Components list in the SCH Library panel and select Tools» Rename Component. Type the new component name that uniquely identifies it, e.g. TRANSISTOR NPN, in the New Component Name dialog. 2. If necessary, relocate the origin of the sheet to the center of the design window by selecting Edit» Jump» Origin [shortcut J, O]. Check the NPN component Status line at the bottom left of the screen to confirm that you have the cursor at the origin. Components supplied by Altium are created around this point, marked with a crosshair through the center of the sheet. The reference point of a component is the point you will be holding the component by when you place it. For a schematic component, this point is the nearest electrical hotspot to the origin, usually the electrical end of the nearest pin. 3. Set the Snap grid to 1 and the Visible grid to 10 in the Library Editor Workspace dialog by selecting Tools» Document Options [shortcut T,D]. Press G to quickly toggle through and set the Snap Grid to 1, 5 or 10 units. 5-4 We will accept the other default settings by clicking OK. If the grid is not visible, press Page Up to display it. 4. To create the NPN example above, we will first define the component body. Select Place» Line [shortcut P, L], or click on the Place Line toolbar button. Press the TAB key to set the line properties in the PolyLine dialog and click OK. Click to start the vertical line at 0, -1 and finish at 0,-19. Right-click to place the line. Now create

107 Creating Components tutorial the other two lines from 0,-7 to 10, 0, and 0,-13 to 10, -20, using Shift+SPACEBAR to set the modes of these lines to Any Angle. Right-click or press ESC to end line placement mode. 5. The arrow is created out of a closed polygon. Select Place» Polygon [shortcut P, Y] or click on the Place Polygon toolbar button. Press the TAB key to set the polygon properties in the Polygon dialog and click OK. Click to form the vertices of a triangle and right-click to end. Right-click or press ESC to end polygon placement mode. 6. Save the component [shortcut Ctrl+S). Adding pins to a schematic components Component pins give a component its electrical properties and define connection points on the component. They also have graphical properties. To place pins on a component in the Schematic Library Editor: 1. Select Place» Pins [shortcut P, P] or click on the toolbar button. The pin appears floating on the cursor, held by the nonelectrical end that goes against the component body. 2. Before placing the pin, press the TAB key during placement to edit the pin's properties. The Pin Properties dialog displays. If you define the pin attributes before you place it, the settings you define will become the defaults and the pin numbers and any numeric pin names will auto-increment when you place them. 3. In the Pin Properties dialog, type in a pin name in the Display Name field and a unique pin number in the Designator field. Click on the Visible checkboxes if you want the pin name and designator visible when you place the component on a schematic sheet. 4. Set the Electrical Type to represent the type of electrical connection the pin makes by choosing an option from the drop-down list. This type can be used by the Electrical Rules Checker when compiling a project or analyzing a schematic document to detect electrical wiring errors in a schematic sheet. In this component example, all pins are a Passive electrical type. 5. Set the length of this pin in hundredths of an inch in the Length field. All pins in this component are set to 20 and click OK. If you wish to alter the position of the pin name or number in relation to the body of the component, select Tools» Preferences and change the Pin Margin options in the Schematic tab. 5-5

108 Creating Components tutorial 6. Press the SPACEBAR to rotate the pin in 90º increments while it is floating on the cursor. Remember that only one end of a pin is electrical and you must place the pins with this end out from the component body. The non-electrical end of the pin has the pin name next to it. 7. Continue to add the pins required to finish the component, making sure the pin names, numbers, symbols and electrical types are correct. 8. You have now finished drawing your component, so select File» Save [shortcut Ctrl+S]. Notes on adding pins To set pin properties after placing the pin, double-click on the pin, or double-click on the pin in the Pins list in the SCH Library panel. Use a backslash (\) after a letter to define an overscored letter in a pin name, e.g. M\C\L\R\/VPP will display as. If you wish to hide the power and ground pins on a component, click on the Hide checkbox. When they are hidden, these pins will be connected to power and ground nets as specified in the Connect To field, e.g. the pin for VCC will connect to net VCC when placed. To view hidden pins, select View» Show Hidden Pins [shortcut V, H]. Any hidden pins will be displayed in the design window. The display name and default designator will display as well. You can edit pin properties directly in the Component Pin Editor dialog, without having to edit each pin through its corresponding Pin Properties dialog. Click on Edit Pins in the Library Component Properties dialog to display the Component Pin Editor dialog. 5-6

109 Creating Components tutorial For a multi-part component, the relevant pins for the selected part will be highlighted with a white background in the Component Pin Editor dialog. All pins of other parts are grayed. You are, however, still able to edit the pins of these non-selected parts. Select a pin and click Edit to display the Pin Properties dialog for that pin. Setting the schematic component s properties Each component has properties associated with it such as the default designator, the PCB footprint and/or other models and parameters of the component. You can also set up the various part fields and library fields that are displayed when the component properties are edited from a schematic sheet. To set the component's properties: 1. Select the component in the Components list of the SCH Library panel and click on the Edit button. The Library Component Properties dialog displays. 2. Type in the default Designator, e.g. Q? and a comment that will display when the component is placed on a schematic sheet, e.g. NPN. Using the question mark will allow the designator number to auto-increment on placement, e.g. Q1, Q2. Make sure the Visible boxes are checked. 3. Leave the other fields at their default values while we add models and parameters, as required. 5-7

110 Creating Components tutorial Adding models to the schematic components You can add any number of PCB footprint models to be associated with a schematic component, as well as model files that are used for simulation and signal integrity analyses. You can then select the appropriate models from the Component Properties dialog when you place the component in a schematic document. There are several different ways to add models to a component. You may wish to download a vendor s model file from the web or add models from the existing Altium libraries. PCB footprint models are located in the C:\Program Files\Altium\Library\Pcb folder in the form of PCB libraries (.pcblib files). SPICE models used for circuit simulation (.ckt and.mdl files) are located within the integrated libraries in the C:\Program Files\Altium\Library folder. Search locations for model files When a model is added to the component in the Schematic Library Editor, the link from the component to the model information is resolved by the following valid search locations: 1. Libraries that are included in the current library package project are searched first. 2. PCB libraries (but not integrated libraries) that are available from the currently Installed Libraries list are searched next. Note that the list of libraries can be ordered. 3. Finally, any model libraries that are located down the Project search paths are searched. These paths are defined in the Options for Project dialog (Project» Project Options). Note that libraries that are down the search path cannot be browsed to locate a model, however, the compiler does include them when searching for a model. Please refer to the Components, Models and Library Concepts article for more information about the way models are searched for in the Schematic Library Editor and the Schematic Editor. In this tutorial, we will use the first method of linking the components and its model files, i.e. by adding all necessary model files to the library package project, along with the schematic library, before compiling the library package into an integrated library. Adding footprint models to a schematic component First, we will add a footprint that the schematic component will use when synchronized to a PCB document. The footprint required for our schematic component is named BCY-W3. Note that when linking a PCB footprint model to a schematic component in the Schematic Library Editor, the model must exist in a PCB library, not an integrated library. 1. Click on Add in the Models List section of the Component Properties dialog. The Add New Model dialog displays. 2. Select Footprint from the Model Type drop-down list. Click OK. The PCB Model dialog displays. 5-8

111 Creating Components tutorial 3. Click on the Browse button to find a model that already exists from the Browse Libraries dialog (or simply type in the name of a model that you are going to create later using the PCB Library Editor). 4. When in the Browse Libraries dialog, click on Find. The Search Libraries dialog displays. 5. Select the scope of Libraries on Path and browse to the \Altium\Library\Pcb folder by clicking on the Browse Folder button next to the Path field and click OK. 6. Make sure Include Subdirectories is selected in the Search Libraries dialog. In the Name field, type BCY-W3 and click on Search. 7. You should get one result in the Cylinder with Flat Index.PcbLib. Click on Select to close the Search Libraries dialog, install the library and select BCY-W3 in the Browse Libraries dialog. Click OK to return to the PCB Model dialog. 5-9

112 Creating Components tutorial 8. Click OK to add the model. The model name is included in the Models list of the Component Properties dialog. Adding Circuit Simulation models SPICE models used for circuit simulation (.ckt and.mdl files) are located within the integrated libraries in the C:\Program Files\Altium\Library folder. Add these models if you wish to run analyses on your design. It is recommended that if you use these simulation models in your library components, open the.intlib file that contains the required models (File» Open and confirm you want to extract the source libraries). Then copy the model files from the output folder (generated when you opened the integrated library) into the folder that contains your source libraries. 1. Click on Add in the Models List section of the Component Properties dialog. The Add New Model dialog displays. Select Simulation from the Model Type drop-down list and click OK. The SIM Model General / Generic Editor dialog displays. 2. For this example, choose a Model Kind of Transistor from the Model Kind drop-down list. The Sim Model Transistor/BJT dialog displays. 5-10

113 Creating Components tutorial The Model Name is the crucial link to the SIM model file, so make sure it is a valid model name. To find existing model file names in the Altium integrated libraries, click on the Search button in the Libraries panel, select the Model Type option of Simulation in the Search Libraries dialog and click on the Search button. 3. Make sure BJT is selected as the Model Sub-Kind. Enter a valid Model Name, e.g. NPN (for model file NPN.mdl), and a description, e.g. NPN BJT, and click OK. Click OK to return to the Component Properties dialog where the model NPN has been added to the Models list. Adding Signal Integrity models The Signal Integrity simulator uses pin models rather than component models. To configure a component for signal integrity simulation, you either set the Type and Technology options, which will use default pin models, or import an IBIS model. 1. To add a Signal Integrity model, click on Add in the Models List section of the Component Properties dialog. The Add New Model dialog displays. 2. Select Signal Integrity from the Model Type drop-down list and click OK. The Signal Integrity Model dialog displays. 3. If you wish to import an IBIS file, click on the Import IBIS button and navigate to the required.ibs file. For this example however, type in the Model Name and Description of NPN (for example) and select a Type of BJT. Click OK to return to the Component Properties dialog where the model is added to the Models list. 5-11

114 Creating Components tutorial For more information about adding and editing Signal Integrity models, refer to the DXP Signal Integrity Tutorial. Adding component parameters Parameters are a means of defining additional information about the component. Parameters, such as strings that identify data like the component manufacturer or the date, can be added to the document. A string parameter could also be added for the component's value, where applicable (e.g. 100K for a resistor). Parameters can be set to display as special strings when components are placed on a schematic sheet. Other parameters are required as values for simulation or can be used as PCB rules created in the Schematic Editor. To add a parameter to a schematic component: 1. Click Add in the Parameters list section of the Component Properties dialog to display the Parameter Properties dialog. 2. Enter the name of the parameter and a value. Make sure String is selected as the parameter type if you require a text string and the value s Visible box is ticked if you want the value to display when the component is placed on a schematic sheet. Click OK. The parameter is added to the Parameters list in the Component Properties dialog. 5-12

115 Creating Components tutorial Indirection strings Using indirection strings, you can set up a parameter field for a component that will display on the schematic and can also be used by DXP when running a circuit simulation, for example. Any added component parameter can be used as an indirection string. The parameter name has a prefix of = attached to it when it is used as an indirection string. Value parameter The Value parameter can be used for any general information about the component, but discrete components, such as resistors and capacitors, use it when simulating. We can set the component s Comment, using indirection strings, to read the value from an added Value parameter that is then mapped to the Comment information in the PCB Editor. Rather than enter the value twice (i.e. in the parameter named Value and then again in the Comment field), DXP supports indirection which will replace the contents of the Comments field with the Value parameter s string. 1. Click Add in the Parameters list section of the Component Properties dialog to display the Parameter Properties dialog. 2. Enter the name Value and a value of 100k. This value will be used when you run a circuit simulation on a schematic sheet with this component placed on it. Make sure String is selected as the parameter type and the value s Visible box is ticked. Set up any font, color or orientation options and click OK to add the new parameter to the Parameters list in the Component Properties dialog. 3. In the Properties section of the Component Properties dialog, click on the Comment field and select the =Value string from the drop-down list and turn Visible off. 4. Save the component sheet and its properties in the library by selecting File» Save [shortcut Ctrl+S]. 5. When viewing special strings in the Schematic Editor, make sure the Convert Special Strings option is enabled in the Graphical Editing tab of the Preferences dialog (Tools» Preferences). If the Comment does not display in the PCB document after updating the PCB from the schematic document, make sure that the Comment is unhidden in the footprint s Components dialog. 5-13

116 Creating Components tutorial Creating a new schematic component with multiple parts In this next part of the tutorial, we will create a new component with four parts, a Quad 2-IN AND gate, named 74F08SJX. We will also create an alternate mode view using an IEEE symbol as an example. 1. Select Tools» New Component [shortcut T, N] when in the Schematic Library Editor. The New Component Name dialog displays. Part A of component 74F08SJX 2. Type in the name of the new component, e.g. 74F08SJX, and click OK. The new component name displays in the Components list in the SCH Library panel and an empty component sheet displays with a crosshair through the center (origin) of the sheet. 3. Now we will create the first part of the new component as shown above, including its pins, as detailed in the following sections. The first part will be used as the basis for the other parts as only the pin numbers will change in this example. Creating the body of the component b The body of this component is constructed from a multi-segment line and a circular arc. Make sure the component sheet origin is in the center of the workspace by selecting Edit» Jump» Origin [shortcut J, O]. Also, make sure the grid is visible [shortcut Page Up]. Placing lines 1. Select Place» Line [shortcut P, L] or click on the toolbar button. The cursor changes to a crosshair and you are now in multi-segment line placement mode. 2. Press the TAB key to set the line's properties. Set the line width to Small in the Polyline dialog. 3. Left-click or press ENTER to anchor the starting point for the line at 25, -5. Check the X, Y co-ordinates in the Status bar at the bottom left corner of the Design Explorer. Then position the mouse and left-click to anchor a series of vertex points that define the segments of the line (at 0,-5; 0,-35 and 25,-35). 4. When you have finished drawing the line, right-click or press ESC. Right-click or press ESC to exit line placement mode. Save the component. 5-14

117 Creating Components tutorial Drawing an arc Placing an arc is a four-step process that sets the center point, radius, start point and end point of the arc. You can press Enter instead of left-click to place the arc. 1. Select Place» Arc [shortcut P, A]. The last arc drawn appears on the cursor and you are now in arc placement mode. 2. Press the TAB key to set the arc's properties. The Arc dialog displays. Set the radius to 15mils and the line width to Small. 3. Position the cursor and left-click to anchor the center point of the arc (25, -20). The cursor will then jump to the current default arc radius (15mils) which we have already set in the Arc dialog. 4. Click to set the radius. The cursor will then jump to the start point of the arc. 5. Move the cursor to adjust the start point, then left-click to anchor it. The cursor will then jump to the end point of the arc. Move the cursor to change the position of the end point, then left-click to anchor it and complete the arc. 6. Right-click, or press ESC, to exit arc placement mode. Adding pins Add the pins to the first part, using the same technique described in the section Adding pins to a schematic component earlier in this tutorial. The pins 1 and 2 are Input electrical types and 3 is Output. The power pins are hidden pins, i.e. GND (pin number 7) and VCC (pin number 14). They will remain constant for all parts and Part A with power pins unhidden 5-15

118 Creating Components tutorial so only have to be set once as belonging to Part zero (Part 0). Part zero is simply a place to store pins that are common to all parts in a component and the pins in this part will be added to each part when it is placed in the schematic. In the Properties tab of the Pin Properties dialog for these power pins, make sure they are set to Part 0 in the Part Number field, the Electrical Type is Power, the Hide box is checked and the power pin connects to the correct net name, e.g. VCC (pin number 14) connects to VCC as entered in the Connect To field. Creating the new parts 1. Select the component using Edit» Select» All [shortcut Ctrl+A]. 2. Select Edit» Copy [shortcut Ctrl+C]. The cursor will change to a crosshair. Click on origin or the top left corner of the component body to set the copy reference point (that is where the cursor will be holding the selection when you paste it) and copy the selected objects to the clipboard. 3. Select Tools» New Part. A blank component sheet displays. The Part counter in the SCH Library panel will be updated to include Part A and Part B if you click on the + to the right of the component name in the Components list in the SCH Library panel. 4. Select Edit» Paste [shortcut Ctrl+V]. The cursor appears with an outline of the component part attached at its reference point. Move the copied part until it is positioned the same as the original part. Click to paste the copied part. 5. Update the pin information in the new part, Part B, by double-clicking on each pin and changing the pin name and number in the Pin Properties dialog. Part B 6. Repeat steps 3 to 5 above to create the remaining two parts, Part C and D. Part C 7. Save the library. Part D Alternatively, copy and paste to create all the new parts and then use the Component Edit Pins dialog (accessed by clicking Edit Pins in the Component Properties dialog) to update all the pin names and numbers in one go. 5-16

119 Creating Components tutorial Creating an alternate view mode for a part You can add up to 255 alternate view modes to a component part. These view modes can contain any different graphical representation of the component, such as DeMorgan or IEEE symbols. A library of IEEE symbols are available from the Sch Lib IEEE toolbar (View» Toolbars» Sch Lib IEEE). If any alternate views of a part have been added, they are displayed in the Schematic Library Editor by selecting an alternate mode from the Mode button drop-down list. When the component is placed on the schematic sheet, the view mode is selected from the Mode drop-down list in the Graphical section of the Component Properties dialog. To add an alternate view mode, with the component part displayed in the design window of the Schematic Library Editor: 1. Click on the button or select Tools» Mode» Add. A blank sheet for Alternate 1 displays. 2. Place the appropriate IEEE symbol, for example, for that part and save the library. Alternate 1 view mode of IEEE symbol Setting the component s properties 1. Set the component's properties by clicking on the Edit button in the SCH Library panel when the component is selected in the Components list. Fill in the Library Component Properties dialog specifying the default designator as U?, the description as Quad 2-Input AND Gate and add the footprint name DIP14 to the Models list. We will create a DIP14 footprint using the PCB Component Wizard later in this tutorial. 2. Save the component in the library by selecting File» Save [shortcut Ctrl+S]. Adding components from other libraries You can also add in components to your schematic library from other open schematic libraries and then edit their properties as required. If the component is part of an integrated library, you will have to open the.intlib file (File» Open) and choose Yes to extract the source libraries. Then open the generated source library (.Schlib) from the Projects panel. 1. Select the component that you wish to copy in the Components list of the SCH Library panel so it displays in the design window. 5-17

120 Creating Components tutorial 2. Select Tools» Copy Component to copy a component from the current library document to any other open library document. The Destination Library dialog displays listing all currently open schematic library documents. 3. Select the document to which you want to copy the component. Click OK and a copy of the component will be placed in the destination library where you can edit it, if necessary. Copying multiple components You can copy single or multiple library components within a schematic library or to another open schematic library using the SCH Library panel. 1. Select the component(s) in the Components list of the SCH Library panel using the standard Windows selection keys (Click, SHIFT+Click and CTRL+Click). Right-click and select Copy. 2. Change to the destination library, right-click in the Components list of the SCH Library panel and choose Paste to add them to the list. Checking components using Schematic Library reports To check that the new components have been created correctly, there are three reports that can be generated when a schematic library is open. All reports are created in ASCII text format. Make sure the library file is saved before the reports are generated. Close the report file to return to the Schematic Library Editor. Component Report To create a report that lists all the information available for the active component: 1. Select Reports» Component [shortcut R, C]. 2. The report 'libraryname.cmp' displays in the Text Editor and includes the number of parts with the pin details for part in the component. Library Report To create a report that lists each component in the library and its description: 1. Select Reports» Library [shortcut R, L]. 2. A report named libraryname.rep displays in the Text Editor. Component Rule Checker The Component Rule Checker tests for errors such as duplicates and missing pins. 5-18

121 Creating Components tutorial 1. Select Reports» Component Rule Check [shortcut R, R]. The Library Component Rule Check dialog displays. 2. Set the attributes you wish to check for. Click OK. A report named libraryname.err displays in the Text Editor, listing any components that violate the rule check. 4. Make any adjustments necessary to the library and rerun the report. Creating PCB component footprints This part of the tutorial covers the following topics: creating a new PCB library using the Component Wizard to create a footprint for a schematic component manually creating unusual footprints in a PCB library using routing primitives within a footprint. Footprints can be created in the PCB Editor and copied into a PCB Library, copied between PCB libraries, or created from scratch using the PCB Library Editor s PCB Component Wizard or drawing tools. If you had a PCB design with all the footprints already placed, you could use the Design» Make PCB Library command in the PCB Editor to generate a PCB library that includes those footprints only. DXP also includes comprehensive libraries of predefined through-hole and SMD component footprints for use in designing PCBs. The footprint libraries (.PcbLib files) supplied are stored in the \Altium\Library\Pcb folder in your DXP installation directory. In this part of the tutorial, we will be creating new footprints to illustrate the procedures required only. Please check the specifications for a particular footprint using the manufacturer s data books. Creating a new PCB Library To create a new PCB library: 1. Select File» New» PCB Library. A new PCB library document, called PcbLib1.PcbLib, is created and an empty component sheet called PCBComponent_1 displays in the design window. 2. Rename the new PCB library document to PCB Footprints.PcbLib, for example, by selecting File» Save As. 3. Open the PCB Library Editor panel by clicking on the PCB Library tab. 5-19

122 Creating Components tutorial 4. You can now add, remove or edit the footprint components in the new PCB library using the PCB Library Editor commands. Using the PCB Component Wizard The PCB Library Editor includes a Component Wizard that will build a component footprint based on your input to a series of questions. We will use the wizard to create a footprint for a DIP14. To create our new component footprint, DIP14, using the Component Wizard: 1. Select the Tools» New Component [shortcut T, C] or click on the Add button in the PCB Library Editor. The Component Wizard will automatically start. Click on Next > to progress through the Wizard. 5-20

123 Creating Components tutorial 2. Answer the questions asked by selecting from the options available. To create our DIP14, select Dual in-line Package (DIP) as the pattern, Imperial units, 60mil round pads with a 32mil hole (select and type over the dimensions), a distance between pads of 300mil (horizontal) and 100mil (vertical) and then accept the rest of the defaults until you need to specify the number of pads required. Type in 14 from the number of pads required. 3. Click Next > until you come to the final page of the Wizard and click Finish. The filename of new footprint, DIP14, will appear in the Components list in the PCB Library Editor panel and the new footprint will display in the design window. You can then further modify the component to suit requirements. 4. Save the library with its new footprint component by selecting File» Save [shortcut Ctrl+S]. Manually creating component footprints Footprints are created and modified in the PCB Library Editor using the same set of tools and design objects available in the PCB Editor. Anything can be saved as a PCB footprint, including corner markers, phototool targets and mechanical definitions. To create the component footprint, we will place tracks and arcs for the outline and then place pads to form the component pin connections. These design objects can be placed on any layer, however the outline is normally created on the Top Overlay (silkscreen) layer and the pads on signal layers. When you place the footprint on a PCB document as a component, all objects that make up the footprint will be assigned to their defined layers. 5-21

124 Creating Components tutorial To manually create a component footprint: 1. Select the Tools» New Component [shortcut T, C], or click on the Add button in the PCB Library Editor. The Component Wizard will automatically start. 2. Press Cancel to exit the Wizard and manually create a component. An empty component footprint workspace displays, called PCBComponent_2. 3. To rename this default footprint, select PCBComponent_2 from the list in the PCB Library Editor panel and click on the Rename button. Type in the new footprint name in If the origin marker is not the Rename Component dialog. displayed, select Tools 4. It is recommended that you build the component footprint around the» Preferences [shortcut T, P], click on the workspace 0, 0 reference point, often indicated by an origin marker. Select Display tab and click on Edit» Jump» Reference [shortcut J, R] to position the cursor at the the Origin Marker bo x. workspace 0, 0 coordinate. The reference point is the point you will be holding the component by when you place it. Typically, the reference point is either the center of pad 1 or the geometric center of the component. The reference point can be set to either of these at any time using the Edit» Set Reference submenu options. Placing pads on a new footprint One of the most important procedures in creating a new component footprint is placing the pads that will be used to solder the component to the PCB. These must be placed in exactly the right positions to correspond to the pins on the physical device. To place the pads on the footprint: 1. Click on the Top Layer tab at the bottom of the design window before you start placing pads. 2. Select Place» Pad [shortcut P, P] or click the 2. Select Place» Pad [shortcut P, P] or click the button on the toolbar. A pad will appear floating on the cursor. Before placing the first pad, press the TAB key to define the pad properties. The Pad dialog displays. 5-22

125 Creating Components tutorial 3. Change the size and shape as required and set the Designator to 1 (to correspond with the component pin number). Click OK. 4. Position the cursor and click, or press ENTER, to place the first pad centered on the origin 0, Before placing the next pad, press TAB to make any changes. Note that the pad designator increments automatically. 6. Right-click, or press ESC, to exit pad placement mode. 7. Save the footprint by selecting File» Save [shortcut Ctrl+S]. Pad Designators and Paste Arrays Pads can be labeled with a designator (usually representing a component pin number) of up to four alphanumeric characters and no spaces. The designator can be left blank if desired. If the designator begins or ends with a number, the number will auto-increment when placing a series of pads sequentially. To achieve alpha increments, e.g. 1A, 1B, or numeric increments other than 1, use the Paste Array feature. By setting the designator of the pad prior to copying it to the clipboard and setting the Text Increment field in the Paste Array dialog, the following types of pad designator sequences can be placed: numeric (1, 3, 5) alphabetic (A, B, C) combination of alpha and numeric (A1 A2, or 1A 1B, or A1 B1 or 1A 2A, etc). To increment numerically, set the Text Increment field 5-23

126 Creating Components tutorial to the amount you wish to increment by. To increment alphabetically, set the Text Increment field to the letter in the alphabet that represents the number of letters you wish to skip. For example, if the initial pad had a designator of 1A, set the Text Increment field to A, (first letter of the alphabet), to increment designators by 1. Set the Text Increment field to C (the third letter of the alphabet) and the designators will become 1A, 1D (three letters after A), 1G etc. 1. Create the initial pad with the designator required, e.g. 1A. Copy this pad to the clipboard using Edit» Copy [shortcut Ctrl+C]. Click on the pad center to define the copy reference point. 2. Select Edit» Paste Special [shortcut E, A]. The Paste Special dialog displays. Select Paste on current layer and Keep net name. 3. Click on the Paste Array button to display the Setup Paste Array dialog. 4. As an example, set the Item Count to 5, the Text Increment to C, select a Linear Array Type and the appropriate array spacing for the copied pad and click OK. 5. Click to place the array. Check that the pad designators have incremented as expected. Drawing an outline of a new footprint We will create the footprint outline on the Top Overlay layer so that it can be included in a silkscreen mask during manufacture of the PCB. The outline is a manufacturing guide only. It is the placement of the pads that is crucial. 1. Click on the Top Overlay layer tab at the bottom of the design window before you start placing lines (tracks). 2. Check the manufacturer s specifications for the footprint. Press Q to toggle the coordinates from imperial (mils) to metric (mm). Check the coordinates in the Status bar at the bottom of the screen to see which measurement mode you are in (mils or mm). Also, set the grids by selecting Tools» Library Options. Always create surface mount footprints on the Top Layer. They can be flipped to the Bottom Layer during placement using the L shortcut key. 3. Use the Line tool to create the component outline on the Top Overlay layer. Select Place» Line [shortcut P, L], or click on the button. If you make a mistake 4. Click to define a start point of the tracks that will define the top of the footprint. 5. Press TAB to define the line width (0.2mm) and check the layer in the Line Constraints dialog. during track placement, press BACKSPACE to remove the last track segment. 6. Click to create the outline tracks and right-click to end this series of connected track segments. 7. To exit track placement mode, right-click or press ESC. Placing Designator and Comment special strings The special strings,.designator and.comment, can be added to the footprint layer in the PCB Library Editor if you require control over their layer, location and text attributes prior to placing the 5-24

127 Creating Components tutorial component on a PCB sheet. These will be in addition to the standard designator and comment, which can be hidden, if required, when placing the component in a PCB document by selecting the Hide option in the Designator and Comments sections of the Component dialog. Typically, these special strings are placed on a mechanical layer which is then included in the assembly drawing. Display the required Mechanical layer by selecting Tools» Mechanical Layers. Click on Enable and then Show next to the Mechanical layer name in the Board Layers and Colors dialog. 1. Click on the Mechanical layer tab at the bottom of the design window to activate this layer. The tab will be highlighted and all new text will be placed on this layer. 2. Select Place» String [shortcut P, S] or click on the Place String button. 3. Press the TAB key to type in the text string and define its properties, e.g. font, size and layer, before you place the text. The String dialog displays. Select.Designator from the Text drop-down list. Set the text height to 60mil and the width to 10mil and click OK. 4. Now we can place the text string. Position the text string in the required location and click. 5. Place the.comment special string using the same procedure. 6. Right-click, or press ESC, to exit text placement mode. If the text is not displaying when the footprint is placed in the PCB document, make sure that the Convert Special Strings option is selected in the Display tab of the Preferences dialog (Tools» Preferences) in the PCB Editor. Adding height to your PCB footprint To add a height attribute to your footprint, double-click on the footprint in the Components list in the PCB Library panel to display the PCB Library Components dialog. Type the recommended height for the component in the Height field and click OK. Creating a footprint with an irregular pad shape You can create irregular pad shapes by joining pad shapes together, as in the first example SOT89, or by adding primitives to a pad that will become connected to the pad s net when placed in a PCB document. This section of the tutorial looks at creating the surface mount footprint SOT89, how to include some routing primitives in a component footprint and also how to create footprints with multiple connection points on same pin. The manufacturer s specifications for this SOT89 footprint are in metric, summarized below. 5-25

128 Creating Components tutorial Dimensions (millimeters) A 5.00 B 6.00 C 1.35 D 0.70 E 1.90 F 3.30 G Press Q to toggle the coordinates from imperial (mils) to metric (mm) if necessary. Check the coordinates in the Status bar at the bottom of the DXP window to see which measurement mode you are in (mils or mm). 2. Make sure you have set the grid to metric, by changing the visible and snap grids by selecting Tools» Library Options [shortcut T,O]. Set up the grids to 10mm and the Snap grid to 1mm. Placing the pads When creating the component footprint SOT89, we will use the reference point on Pin 1 as the origin of this footprint, i.e. the center of pin number one and therefore corresponding pad 1, will be at coordinates 0,0. 1. To place the pads on the Top Layer of the footprint, select Place» Pad [shortcut P, P] or click the button. Press the TAB key to define the pad properties in the Pad dialog. Make sure the layer is set to Top Layer, the Designator is set to 1 (to correspond with the component pin number) and the hole size is 0mil. Click OK. 2. Position the cursor and click to place the three pads. The designators will automatically update. Right-click, or press ESC, to exit pad placement mode. Modify pad 2 to elongate it so it will join to Pad 0 when placed. 3. Finally place pad 0. Set the pad size and shape in the Pad dialog by clicking on Simple and select Octagonal from the Shape drop-down list. SOT89 footprint 5-26

129 Creating Components tutorial Drawing the component outline 1. To create the component outline on the Top Overlay layer, click on the Top Overlay layer tab at the bottom of the design window. Select Place» Line [shortcut P, L], or click the button. 2. Click to place the first corner of the outline box. Press the TAB key to display the Line Constraints dialog, set the Width, check the layer is Top Overlay, and click OK. Click to define the corners of the box and finish the outline by clicking back on the starting point. Right-click, or press ESC, to exit line placement mode. 3. A requirement for this footprint is an indicator near pin 1; in this case, a circle is placed near pad 1 on the Top Overlay. A chamfered edge to the footprint could also be used. To place the circle, select Place» Full Circle [shortcut P, U] or click the button. Click to start the circle at its center. Then drag the crosshair and click to set a circle with a radius of 5mil. Right-click, or press ESC, to exit circle placement mode. Double-click on the circle to change its Width to 10mil in the Arc dialog, thereby creating a filled circle. Checking solder and paste masks Solder and paste masks are created automatically at each pad site on the Solder Mask and Paste Mask layers respectively. The shape that is created on the mask layer is the pad shape, expanded or contracted by the amount specified by the Solder Mask and Paste Mask design rules set in the PCB Editor, or specified in the Pad dialog. Displaying the masks Check the solder and/or paste masks have been automatically created in the correct layers in the PCB Library Editor. In this example, we will turn on the Top Solder layer 1. To make these layer visible, select Tools» Mechanical Layers [shortcut L] and click on the Show boxes next to the Mask Layers in the Board Layers & Colors dialog. 2. Now click on the layer tab, e.g. Top Solder, at the bottom of the design window to view the top solder mask. Use the shortcut toggle keys Shift+S to view the layers in single layer mode. Setting mask expansions by design rules If you wish to use design rules to set the mask expansions: 1. Select Expansion value from rules in the Paste Mask Expansion and/or Solder Mask Expansion sections of the Pad dialog. 2. Set up these rules by selecting Design» Rules from the PCB Editor menus and check or revise the Mask category design rules in the PCB Rules and Constraints Editor dialog. These rules will be obeyed when the footprint is placed in the PCB. 5-27

130 Creating Components tutorial Specifying mask expansions To overwrite the expansion design rules and specify a mask expansion: 1. Select Specify expansion value in the Paste Mask Expansion and/or Solder Mask Expansion sections of the Pad dialog. 2. Type the required value(s) and click OK. Save the footprint. Including routing primitives in component footprints Library component footprints can also include routing primitives, such as tracks and arcs placed on signal layers. The following example of footprint SOT89 includes a primitive object (a wider track connected to pad 2), as well as rectangular pads, which would be part of the net connectivity. This is simply an alternative way to creating the octagonal pad used for its irregular pad shape that we set up in the previous section of this tutorial. If tracks, or any other objects, are used as part of a footprint, solder and paste masks must be defined manually using tracks, etc. on the Mask layers. If you manually place the footprint on the board, only pads will inherit a net name. Any other primitives on a signal layer, e.g. arcs and fills used to create routing within a footprint, will show as a DRC error. If it does not, you could force the online DRC by moving the component. Net names can also be applied to routing primitives that are built into placed components in a PCB document at any time. To assign a net name to the primitive in the placed footprint in a PCB document: 1. Select Design» Netlist» Update Free Primitives from Component Pads from the PCB Editor menu. SOT89 with primitive (track) placed on a signal layer to create an irregular pad shape 2. The net name of the routing primitives are resynchronized to the net name on the pads they connect to, i.e. this command will connect a primitive to the same net as its adjoining pad. Footprints with multiple connection points on same pin The footprint below, a TO-3 transistor, has multiple connection points on same pin. You will notice that there are two pads with the same designator of

131 Creating Components tutorial When the Design» Update PCB command is used in the Schematic Editor to transfer design information to the PCB, the resulting synchronization should show the connection lines going to both pads in the PCB Editor, i.e. they are on the same net, as shown below. Drawing a footprint with a solder mask The following footprint, named LCR1_KC1, is for a push button switch. It requires a solder mask to be included along with the footprint outline (Top Overlay) and the tracks and pads on the signal layer (Top Layer). 1. To create the component outline on the Top Overlay layer, click on the Top Overlay layer tab at the bottom of the design window. Select Place» Full Circle [shortcut P, U] or click the button on the toolbar. Click on 0, -80 mil to start the circle at its center, then drag the crosshair to 100, -80 and click to set a circle with a radius of 100mil. Right-click, or press ESC, to exit circle placement mode. LCR1_KC1 footprint 5-29

132 Creating Components tutorial Mechanical Layers [shortcut L] and click on the Show box next to Top Solder in the Mask Layers section of the Board Layers dialog. Now click on the Top Solder layer tab at the bottom of the design window and draw a circle as shown in the step above with its center on 0, -80 mil, a radius of 45 mil and width of 100mil (to fill in the circle). Right-click to exit circle placement mode. 3. Click on the Top Layer tab at the bottom of the design window and use tracks and arcs to create the copper connections on the Top Layer. To exit track placement mode, right-click or press ESC. 4. To place the pads on the Top Layer of the footprint, select Place» Pad [shortcut P, P] or click the button. Press the TAB key to define the pad properties in the Pad dialog. Set the pad size and shape by clicking on Simple, type in 10mil for both the X and Y size and select Round from the Shape drop-down list. Make sure the layer is set to Top Layer, the Designator is set to 1 (to correspond with the component pin number) and the hole size is 0 mil. Click OK. 5. Position the cursor and click to place the first pad centered on the origin 0,0 and place the second pad centered on 0, -160mil. The designators will automatically update. Right-click, or press ESC, to exit pad placement mode. 6. Save the footprint by selecting File» Save [shortcut Ctrl+S]. Adding footprints from other sources You can add existing footprints to your PCB library. The copied footprint can then be renamed and modified to match the specifications required. If you want to add existing footprints to your PCB library, you can: select placed footprint(s) in a PCB document and copy (Edit» Copy) and paste them into an open PCB library using Edit» Paste Component, or Select Edit» Copy Component when the footprint to be copied is active in the PCB Library Editor, change to the open PCB destination library and select Edit» Paste Component. The footprint is added as a new component in the Components list in the PCB Library panel and displays in the design window. Validating component footprints As in the Schematic Library Editor, there are a series of reports that you can run to check the footprints have been created correctly and identify which components are in the current PCB library. To validate all components in the current PCB library, we will run the Component Rule Check report. The Component Rule Checker tests for duplicate primitives, missing pad designators, floating copper and inappropriate component reference. 1. Save your library file before running any of these reports. 5-30

133 Creating Components tutorial 2. Select Reports» Component Rule Check [shortcut R, R] to display the Component Rule Check dialog. 3. Check all the boxes available and click OK. A report, named PCBlibraryfilename.err, is generated and opens in the Text Editor. Any errors will be noted. 4. Close the report to return to the PCB Library Editor. Creating an integrated library Now we have created a schematic library with some schematic components and a PCB library with related footprint models, we can add these to a library package and then compile these libraries together into an integrated library. The components will then always be stored with their models. Note that simulation model files should be copied into the same folder as the source libraries before compiling. The steps to create an integrated library are detailed in the tutorial Integrated Libraries. 1. Create a source Library Package by selecting File» New» Integrated Library. The Projects panel displays with an empty Library Package file named Integrated Library1.LibPkg. Rename the new Library Package using File» Save As. 2. Add the source libraries to the Library Package by selecting Project» Add to Project. Browse to find the schematic libraries (.schlib) and model libraries (PCB footprint libraries (.pcblib), Protel 99 SE libraries (.lib), SPICE models or Signal Integrity models that you want to add to your Library Package. Click Open and the added libraries are listed as Source Libraries in the Projects panel. If you do not want to add in the model libraries and files, you can set a pathname to where they reside on your hard disk by right-clicking on the Library Package name in the Projects panel and selecting Project Options. Add in the pathnames to the location of the footprints and models required by clicking on Add in the Ordered List of Search Paths section of the Search Paths tab of the Options for Project dialog. 3. Compile the source libraries and model files in the library package into an integrated library by selecting Project» Compile Integrated Library. Any errors or warnings found during compilation are displayed in the Messages panel. Fix any inconsistencies in the individual source libraries at this point and recompile the integrated library. 4. A new Integrated Libraryname.INTLIB is generated, saved in the output folder nominated in the Options tab of the Project Options dialog and displays in the Library panel, ready to use. The integrated library is automatically added to the current Libraries list in the Libraries panel. 5-31

134 Creating Components tutorial Glossary The following definitions are used in this tutorial. Component Designators Footprint A component is a physical device that is placed on the board, e.g. the integrated circuit or resistor. Within these components, there may be either a single part or a set of parts that are packaged together. Unique identifiers that are used to tell one component from another in a PCB. They can alpha, numeric, or a combination of both. Pads also have unique designators that correspond to the component pin numbers. A footprint defines (or models) the space occupied by the component on the PCB. The footprint model of a component is stored in a PCB library. A footprint may contain pads for connecting to the pins of a device and a physical outline of the package created from track and/or arc segments on the silkscreen (overlay) layer. Device mounting features may also be included. Footprints in the PCB library have no designator or comment. They become components when placed on a PCB sheet where the designators and comments are allocated. Hidden pins Library Object Pads Part Pins These are pins that exist on the component but do not need to be displayed. Typically, they are power pins and can automatically be connected to a specified net. A Schematic Library is a set of components and its parts stored on individual sheets. A PCB Library contains the component footprints. Each library type has its own Editor. Integrated libraries combine schematic libraries with their related models and cannot be edited directly by the Library Editors. Any individual item that can be placed in the Library Editor workspace. Pad objects are normally used in a footprint to create connection pads for component pins. A collection of graphical objects represents one part of a multi-device component. Parts are stored in separate sheets within components in the schematic component libraries. Component pins give a component its electrical properties and define connection points on the component. 5-32

135 Integrated Libraries tutorial 6 Integrated Libraries tutorial DXP integrated libraries Using DXP integrated libraries Adding and removing libraries Finding a component in integrated libraries Creating an integrated library Creating a schematic library Making a schematic project library Creating a PCB library Creating the source Library Package Adding source libraries to the Library Package Adding models to the Library Package Adding models as source libraries Setting the pathname to model libraries and files Compiling the integrated library Modifying an integrated library DXP integrated libraries This tutorial looks at using, creating and modifying integrated libraries in DXP. Integrated libraries combine schematic libraries with their related PCB footprints and/or SPICE and signal integrity models, all together in a non-editable form. All model information is copied into the integrated library from the model libraries or files and so all the component information is stored together, regardless of the location of the original source libraries. This makes integrated libraries truly portable. Source libraries, including any number of schematic libraries and the related model libraries and files (PCB footprints, SPICE or signal integrity models) are added to a Library Package project file which is then compiled to generate an integrated library. To modify an integrated library, you must change the source library first and then recompile the integrated library. DXP comes with a set of source libraries and integrated libraries (.INTLIB files) stored according to the manufacturer s name in the \Program Files\Altium\Library folder. The schematic source libraries (.schlib files) are included in these integrated libraries and can be extracted by opening the integrated libraries. PCB footprint models are located in the \Program Files\Altium\ Library\PCB folder in the form of PCB libraries (.pcblib files). 6-1

136 Integrated Libraries tutorial SPICE models used for circuit simulation (.ckt and.mdl files) are located within the integrated libraries in the \Program Files\Altium\Library folder and signal integrity models are located in the Altium\Library\SignalIntegrity folder. Using DXP integrated libraries Using an integrated library is very similar to using schematic libraries to place components and add model names. The only difference is that all the information about the component and its related models has already been added to the schematic symbol for you. You can check the Models list of the Component Properties dialog of a component to see what model names have been included with the schematic symbol. Model names can be changed or added from PCB or other model libraries once you have placed a component in a schematic sheet. When the schematic is transferred from the Schematic Editor to a blank PCB using the Design» Update PCB command, the Source Reference Links fields of the Component dialog for each PCB footprint are populated with source library pathnames so you can easily trace where the components and models originated from if you need to change them. Note that you can still always use any other Protel 99 SE or DXP schematic or PCB libraries independently (without being in an integrated library) by adding them to the Library list as usual. Adding and removing libraries All libraries must be added to the Library list in the Libraries panel for the component symbols to become available for placement in a schematic and footprints for the components to be available when creating the PCB. To add integrated libraries to the Libraries list: 1. Click on the Libraries tab or select View» Workspace Panels» Libraries. The Libraries panel displays. 2. Click on the Libraries button at the top of the panel to open the Available Libraries dialog. 6-2

137 Integrated Libraries tutorial 3. Click on the Installed tab and click Install to add libraries. 4. Browse to the library you require in the Open dialog and click Open. 5. Click Close and the integrated library is added to the Libraries list in the Libraries panel. Select the library from the Libraries drop-down list to make it the active library. 6. If a schematic document is open, you can select the component you wish to place from the Components list of the Libraries panel. Click Place <component name> to place it. To remove a library from the Library list: 1. Click on the Libraries button at the top of the Libraries panel to open the Available Libraries dialog. Click on the Installed tab. 2. Select the library you want to remove. Hold down the Shift key to multiple select libraries. Click on Remove. 3. The library pathname disappears from the Installed Libraries list. Click Close. The library is no longer available in the Library panel. Simply add it back in when required. Finding a component in integrated libraries If you do not know where the component you wish to use is located, use the Search Libraries facility. 1. Click on the Libraries panel tab and the Libraries panel displays. 2. Click on the Search button at the top of the Libraries panel to open the Search Libraries dialog. 6-3

138 Integrated Libraries tutorial 3. Select a Scope for searching in installed libraries or libraries on the search path you nominate by clicking on the folder icon in the Path field. Fill in the required Search Criteria filters making sure the filters you wish to use are ticked. Note that the Name field is the name of the schematic component. Click OK to start the search. 4. The integrated libraries that contain a match will display in the Results tab, together with component names, model names, symbols and footprints. 5. Click on a component name to display its model name and graphical representations. 6. When you have found the component you require, click on Install Library to add the selected library to the Libraries list in the Libraries panel. 6-4

139 Integrated Libraries tutorial 7. If you have the schematic sheet open that you want to place the found component on, click on the Select button to switch to the Schematic Editor. The component symbol is selected in the Libraries panel, ready for placement. Click on the Place <component name> button to place the component. The component appears floating on the cursor. 8. Press TAB to display the Components Properties dialog while placing the symbol to set the designator. 9. Check the Models list to check that all the required model information is already added from the integrated library. 10. Click OK and then click to place the component symbol on the schematic sheet. Right-click or press ESC to end component placement mode. Creating an integrated library A Library Package is created first with at least all the schematic libraries added and pathnames can be set to the models libraries. Using the Project commands, the Library Package is then compiled to create the integrated library. Any errors generated during the compiling of the integrated library are displayed in the Messages panel for analysis. Creating a schematic library Before you can add any schematic libraries to the library package, you need to create some! You can create a schematic library out of the components that have been already placed on schematic documents in a project. 6-5

140 Integrated Libraries tutorial If a schematic file is not part of a project, you can still create a schematic library from it when it is open. The only difference is that it will not be added to a project and will display as a free document in the Projects panel when created. Alternatively, you can create a schematic library from scratch using the File» New» Schematic Library command. Then create your own components using the Schematic Library Editor, or copy in components from other open schematic libraries using the Tools» Copy Component command. See Modifying an integrated library later in this tutorial for more information about extracting a schematic library from an existing integrated library. Making a schematic project library To create a schematic library from components in all schematic documents in a project: 1. Open the documents in the project by right-clicking on the project filename in the Projects panel and selecting Open Project Documents. 2. With the schematic documents that contains all the components you want to add to the new schematic library already active, select Design» Make Project Library in the Schematic Editor. Click OK to confirm. 3. The new schematic library will open in the Schematic Library Editor when it is created. All the components in the open schematic files are copied to the new schematic library, named Projectname.SchLib, stored in the same folder as the project file. The filename will appear in the Projects panel listed under Schematic Libraries. 4. Save or rename the new schematic library using File» Save As and close it. Creating a PCB library PCB libraries are supplied with DXP and are stored in the default location of \Program Files\Altium\Library\PCB. However, you can create your own PCB library of footprints from an open PCB file, in a similar manner to creating a schematic library. 1. With the PCB document that contains all the footprints you want to add to the new PCB library already active, select Design» Make PCB Library. 2. The new PCB library will open in the PCB Library Editor when it is created. All the footprints in the open PCB document will be copied to the new PCB library named PCBfilename.lib, which is stored in the same folder as the source PCB document. The filename will appear in the Projects panel as a free document. 3. Rename the new PCB library using File» Save As and close it. Creating the source Library Package Now that we have some schematic libraries created, we need to add these to a library package which in turn is compiled into an integrated library. 6-6

141 Integrated Libraries tutorial 1. Select File» New» Integrated Library. Alternatively, you can click on Create a new integrated library Project in the Pick a task pane which displays when no editors are open, or click on Blank Project (Library Package) in the New section of the Files panel. 2. The Projects panel displays with an empty Library Package file named Integrated Library1.LibPkg. There are no source libraries (schematic or PCB libraries) added to the Library Package at this stage. 3. Rename the new Library Package using the File» Save As command and save it (with a.libpkg extension) to your chosen location. An output folder is automatically created named Project Outputs for Integrated Libraryname in the folder you chose. The pathname to the Library Package file is added to the Output Path field in the Options tab of the Options for Project dialog (Project» Project Options) and the final integrated library file will be saved to this location when it is compiled. Adding source libraries to the Library Package 1. Add in the source libraries to the Library Package by selecting Project» Add to Project or rightclick on the selected.libpkg file and select Add to Project. The Choose Documents to Add to Project [IntegratedLibraryname.LibPkg] dialog displays. 2. Browse to find the schematic libraries (.schlib) that you want to add to your Library Package. The schematic components store all the information needed to find related models in their Component Properties dialogs, so these are the most essential elements to be included in an integrated library. 6-7

142 Integrated Libraries tutorial 3. Click Open and the added libraries are listed as Source Schematic Libraries in the Projects panel. Adding models to the Library Package You can add PCB footprint libraries (.pcblib), Protel 99 SE libraries (.lib), SPICE models or Signal Integrity models to a Library Package in order to keep related libraries in one integrated library (see Adding models as source libraries below). Note that this is optional. If you do not want to add in the model libraries and files, you can set a pathname to where they reside on your hard disk. See Setting the pathname to model libraries and files below. SPICE models used for circuit simulation (.ckt and.mdl files) are located within the integrated libraries in the C:\Program Files\Altium\Library folder. It is recommended that if you use these simulation models in your library components, open the.intlib file that contains the required models (File» Open and confirm you want to extract the source libraries). Then copy the model files from the output folder (generated when you opened the integrated library) into the folder that contains your source libraries. Adding models as source libraries Add model libraries, e.g. PCB libraries, to the Library Package in the same way as the schematic libraries are added. 1. Select Project» Add to Project, or right-click on the selected.libpkg file and select Add to Project. 2. Browse to find the model libraries which you want to add to your Library Package. 3. Click Open and the added libraries are listed as Source PCB Libraries in the Projects panel. Setting the pathname to model libraries and files Alternatively, if the PCB footprints libraries, SPICE models or signal integrity models are not added to the Library Package, the schematic symbols in the integrated library will refer to them using the pathname set up in the Options for Project dialog and stored in the Library Package project file. 6-8

143 Integrated Libraries tutorial 1. Set up the pathname to the PCB libraries you want used by the schematic symbols in the integrated library by selecting Project» Project Options, or right-click and select Project Options when in the Projects panel. Click on the Search Paths tab of the Options for Project dialog. The current location of the new Library Package will be included as one search path in the Ordered List of Search Paths next time you open the Library Package. 2. Add in the pathnames to the location of the footprints and models required by clicking on Add in the Ordered List of Search Paths section of the Search Paths tab. 3. Browse to the folders required in the Edit Search Path dialog by clicking on the button and locating the required model libraries and clicking OK. In the example below, we have added in the pathname to the folder where PCB footprint models are located, i.e. C:\Program Files\Altium\Library\PCB. 4. Click on Refresh List to confirm that the models are located correctly and click OK. 6-9

144 Integrated Libraries tutorial 5. While you have the Options for Project dialog open, click on the Error Reporting tab to see what type of errors and warnings could be generated when the integrated library is compiled. 6. You can change the severity of the violation by clicking on the Report Mode next to the required violation type and selecting another mode from the dropdown list. Click OK to save the project options and close the dialog. 6-10

145 Integrated Libraries tutorial Compiling the integrated library Once you have added the libraries and set any pathnames required, compile them to create the integrated library. 1. Select Project» Compile Integrated Library or right-click on the selected Library Package (.LibPkg) file and select Compile Integrated Library. 2. DXP compiles the source libraries and model files into an integrated library. The compiler checks for any violations, such as missing models or duplicate pins, that have been set in the Error Checking tab of the Options for Project dialog (Project» Project Options). Any errors or warnings found during compilation are displayed in the Messages panel. Fix any inconsistencies in the individual source libraries at this point and recompile the integrated library. See Modifying an integrated library for more information. 3. A new Integrated Libraryname.INTLIB is generated, saved in the output folder nominated in the Options tab of the Options for Project dialog and displays in the Library panel, ready to use. The integrated library is automatically added to the current Libraries list in the Libraries panel. Modifying an integrated library The integrated libraries are used to place components and cannot be edited directly. To make changes to an integrated library, make modifications in the source libraries first and then recompile the integrated library to include the changes. 1. Open the integrated library (.IntLib) that contains the source library you need to modify. Select File» Open and browse to the integrated library required in the Document to Open dialog and click Open. 2. Confirm that you do wish to open the integrated library to extract the source libraries, not just add the integrated to the Libraries panel. Click Yes. The source schematic and model libraries are generated and saved in a new folder named Integrated_libraryname, which is created in the folder storing the integrated library. A Library Package (integrated_libraryname.libpkg) is also created and the source schematic libraries are extracted and listed in the Projects panel. PCB libraries (.PcbLib) are generated as well and stored in the new library package folder but are not automatically added to the Projects panel. The pathname in the Search Paths tab of the Options for Project dialog (Project» Project Options) indicates where the schematic components will search for when the footprints and model files are required. 3. Open the source library file you want to change. e.g. libraryname.schlib, by double-clicking on the library name in the Source Schematic Libraries list in the Projects panel. The library opens in the Schematic Library Editor. 6-11

146 Integrated Libraries tutorial If you wish to modify a footprint, you would have to add in the required PCB library before you could edit the models. Click on the Libraries button in the Library panel. Alternatively, you could use File» Open to open a model file. 4. Click on the SCH Library tab to activate the Schematic Library Editor. 5. Select the component you wish to alter from the Components list. You can make graphical changes to the component symbol by directly editing in the design window. To change component properties, such as model names, double-click on the selected component in the Components list of the Library Editor panel. Alternatively, click Edit in the Library Editor. The Component Properties dialog displays. 6. Make required alternations, such as adding a new model name to a symbol by clicking the Add button on the Models list of the Component Properties dialog and browsing to the location of the new model. Click OK to close the dialog. 7. Save the modified source library by selecting File» Save and close the library. 8. Select the Library Package in the Projects panel and select Project» Compile Integrated Library. 9. The integrated library is recompiled and any errors are listed in the Messages panel. If there are no errors or warnings, the modified integrated library is added to the Libraries panel and is ready to use. 10. Close the Library Package and save it to the same folder as the source libraries. 6-12

147 Customizing component reports tutorial 7 Customizing component reports Creating customized component reports Creating a BOM report Using the Report Manager dialog Manipulating Columns Showing columns Grouped Columns Sorting the column order Sorting data within columns Custom Filtering Creating the Report Exporting the report Using Excel templates Using Batch mode Creating customized component reports Several component reports, such as the Bill of Materials (BOM) report and the Component Cross Reference report, can be customized in DXP by using the Report Manager. This facility allows you to sort and group the data gathered when the report is run. You can also export the report in various formats, such as a Microsoft Excel document or an Adobe Acrobat PDF, or use an Excel template to format the exported data. A batch mode can be used to generate reports that have been set up from an output job configuration file. In this tutorial, we will look at using the Report Manager to set up a Bill of Materials in the Schematic Editor. The BOM report can also be generated from the PCB Editor. The tutorial uses the Altium\Examples\LCD Controller project as an example. Please note that although referred to as the Report Manager dialog in this tutorial, the dialog name will change according to the type of report you are generating, e.g. Bill of Materials (by PartType) for <project_name>. Creating a BOM report To create a Bill of Materials in the Schematic Editor: 1. With the required project or source documents open, select Reports» Bill of Materials. The Bill of Materials for project_name dialog displays. 7-1

148 Customizing component reports tutorial The dialog is divided into two main parts the Columns lists on the left and the data section (grid contents) that displays the information in the shown columns that is generated when the report is initially run. 2. Use this dialog to build up your BOM, for example, by enabling the Show option next to the columns you want to be displayed in the report. We will now look at ways of changing the look of the raw data to create a customized BOM. Using the Report Manager dialog When you run a Bill of Materials or a Component Cross Reference Report, the Report Manager dialog displays to help you format your report. You can show, hide and move columns and then sort and filter the data within the columns before exporting or printing your report. Manipulating Columns The left-hand side of the Report Manager dialog contains two sections - Grouped Columns and Other Columns. The Other Columns section lists all available information columns that can be used in the report. These information columns are sourced from the properties of all components on the document (or the source documents if a project is open) for which the report is being generated. 7-2

149 Customizing component reports tutorial Showing columns To show the Other Columns in the data section of the Report Manager: 1. Click on the Show option next to a column's entry in the list to enable it. The column will appear in the main information area of the dialog. 2. Each enabled column will list information for each of the components found in the source schematic document(s), where such information exists. If the component does not have any information for that particular property, the field will be blank. Grouped Columns You can choose to group components together by one or more specific columns of information. For example, in a Bill of Materials report, you may wish to group components by Footprint or Comment. 1. Click, drag and drop the desired information column from the Other Columns section into the Grouped Columns section of the Report Manager dialog. 2. The column heading appears in the Grouped Columns section and the data is updated to display according to the new groups. You will note that by grouping by footprints, the Quantity column is updated. 3. Click, drag and drop other columns as required into the Grouped Columns section. 4. If you add the LibRef and Comments columns to the Grouped Columns list (for example), you can then change the sorting order of the groups. 7-3

150 Customizing component reports tutorial You could organize the grouping so that you could make a report for all RES (LibRef column) with the same value (Comment column) and the same package (Footprint column). To do this, simply click, drag and drop the Grouped Columns until they are in the order Footprint, Comment and then LibRef. By sorting and filtering the data, you can then define the limits for each of these columns. Sorting the column order The order of the columns in the data section of the dialog can be changed from the Other Columns section or from within the data section itself. The order of the columns in the Other Columns section is reflected by the order of the columns in the data section unless you change the columns directly in the data section. To change the order of columns from the Other Columns section: 1. Click, drag and drop a column name in the Other Columns section to its new position in the list. Repeat until you are satisfied with the order of the columns. 2. The column headings in the data section are updated. For example, if you dragged the column name Quantity to the top of the Other Columns list and Show was enabled, it would appear as the first column heading in the data section. To change the order of columns from within the data section: 1. Click, drag and drop a column heading in the data section to its new position. 2. Note that when a column heading is selected for moving and a valid position is found, the two green arrows are displayed, showing where the column will be inserted. Note that if you wish to see all the columns within the Report Manager dialog, enable Force Columns into View. Sorting data within columns 1. Click on a column heading (away from the far right drop-down arrow) to toggle the sorting of the information between ascending and descending order. 2. All columns will be affected, but the rows will be sorted according to the information column whose heading you click on. Note that if not all the data is displaying within the column, right-click and select Column Best Fit [shortcut Ctrl+F] to lengthen the width of each column according to the longest field entry. 7-4

151 Customizing component reports tutorial Custom Filtering You can apply filtering to show specific component entries. 1. By clicking on the far right drop-down arrow in a column's heading, either select from the individual row entries available, or select Custom, which displays the Custom AutoFilter dialog. 2. Specify exactly which rows of information you want to show, based on filter criteria you apply to the particular information column. In the simple example above, this filter will only display components with a LibRef called RES. Click OK. The drop-down arrow next to the Footprint column heading turns blue to indicate customization of this column. 3. A textual representation of the filter currently applied, e.g. (LibRef = RES), appears in the bottomleft corner of the data section of the dialog. A filter can be quickly cleared by clicking on the small cross next to the text. Creating the Report The Report command is used to create a report using the current data section. The report is automatically loaded into the Report Preview dialog where you can inspect it using various page and zoom controls before exporting or printing it. 1. Click on Report to display a print preview of your BOM. The Report Preview dialog displays. 7-5

152 Customizing component reports tutorial 2. This preview can be printed using the Print button or exported to a file format, such as.xls for Microsoft Excel, using the Export button. See the table below for more export file formats available in this dialog. Close the dialog. Microsoft Excel Worksheet (*.xls) Web Page (*.htm; *.html) Adobe PDF (*.pdf) Web Layer (CSS) (*.htm; *.html) Window Bitmap File (*.bmp) Quattro Pro Worksheet (*.wq1) Rich Text Format (RTF) (*.rtf) JPEG Image File (*.jpg) TIFF Image File (*.tif) Lotus 123 Worksheet (*.wk1) Exporting the report The grid content of the data section can also be exported and a report generated by using the Export button in the Report Manager dialog. When exporting the data using the Export option from the Report Manager dialog, the following file formats are supported. Microsoft Excel Worksheet (*.xls) XML Spreadsheet (*.xml) Web Page (*.htm; *.html) CSV (Comma Delimited) (*.csv) Tab Delimited Text (*.txt) 7-6

153 Customizing component reports tutorial 1. If you want the relevant software application, e.g. Microsoft Excel, to open once the exported file has been saved, make sure Open Exported is selected in the Report Manager dialog. 2. Click on Export button in the Report Manager dialog and save the file in the appropriate format. Using Excel templates If you want to export your data straight into an Excel template, you can select an existing Excel template or you can use the supplied Default Excel template. 1. Enter the required Excel template file directly into the Template field of the Report Manager dialog, or select BOM Default Template.XLT from the dropdown list, or browse for an existing Excel template (.XLT). The file can be specified with a relative or absolute path. For more information about template creation, refer to your Microsoft Excel documentation. 2. If you have the Open Exported option selected in the Report Manager dialog, the file will open in Excel after export. 3. Click on the Excel button to open the Spreadsheet Preview dialog. 4. Click OK in the Spreadsheet Preview dialog to generate the export. The report opens in Excel, formatted in the nominated Excel template. 7-7

154 Customizing component reports tutorial Using Batch mode The Batch Mode field in the Report Manager dialog allows you to specify the export format when generating a report from an output job configuration file ( *.OutJob). This file is created by selecting File» New» Output Job File. 7-8

155 Multi-channel design tutorial 8 Multi-channel design tutorial Multi-channel design Creating a multi-channel design Setting room and designator formats Room Naming Component Naming Defining your own designator format Compiling the project Viewing the channel designator assignments Multi-channel design This tutorial shows how to create a multi-channel design using DXP. A multi-channel design refers to the same channel many times. The channel needs only to be drawn once as a separate schematic sub-sheet and included in a project. You can easily nominate how many times the channel is used by placing multiple sheet symbols that reference the same sub-sheet, or by including the Repeat keyword in the designator of a sheet symbol. The Designator Manager creates and maintains a table of channel connections which is stored as part of the Projects file. A multi-channel project is supported throughout the design process, including back-annotation of designator changes to the project file. In this tutorial, we will explore the multi-channel design Peak Detector - Multi channel.prjpcb, available in the \Altium\Examples folder. 8-1

156 Multi-channel design tutorial This design has three levels of hierarchy the parent sheet, the bank sheet and the channel sheet. The parent sheet (Peak Detector.SchDoc) includes a sheet symbol for four banks (referencing the one Bank.SchDoc four times). The Bank schematic in turn has a sheet symbol for eight channels for each bank, making a total of 32 channels. Rather than create all these channels as separate schematic sheets, we will use the Repeat command and sheet symbols to reference the one schematic, Peak Detector Channel.SchDoc, for each of the channels required. By formatting room names and component designators, we can reflect this hierarchical design. Creating a multi-channel design When creating this design, a PCB project file was created and the three schematics that represent the levels of this multi-channel design were added, i.e. Peak Detector.SchDoc (top or parent sheet), Bank.SchDoc (bank level) and Peak Detector channel.schdoc (channel level). 1. Create the circuit that you wish to become the channel on a separate schematic sheet as shown below (Peak Detector Channel.SchDoc) and add the new schematic to the PCB project file. 2. Next, create a schematic for the bank level (Bank.SchDoc). A sheet symbol needs to be placed on the Bank.SchDoc to create the required number of channels that will refer to the Peak Detector-channel.SchDoc. 3. Select Place» Sheet Symbol and place the sheet symbol. Double-click on the new sheet symbol to display the Properties tab of the Sheet Symbol dialog. 8-2

157 Multi-channel design tutorial The designator name of the sheet symbol is used to uniquely identify each component in each channel. In the example above, the Designator name of the sheet symbol is PD. You can use any name but short names are recommended for the sheet symbols to keep the designators short. This is because the sheet symbol name and a channel number will be added to the designator name when the project is compiled, e.g. R1 will become R1_PD1. 4. In the Filename field, enter the name of the channel schematic you want to use, e.g. Peak Detector-channel.SchDoc. 5. Nominate how many times you wish to reference the channel schematic by entering the Repeat Channel command in the Designator field. The format is: Repeat(sheet_symbol_name,first_channel,last_channel) So, in this example, the command Repeat(PD,1,8) in the Designator field will reference the Peak Detector channel schematic eight times (1,8) via the sheet symbol named PD. 6. Click OK to close the Sheet Symbol dialog and the symbol will change to reflect the multiple channels it now represents. 8-3

158 Multi-channel design tutorial 7. Nets that are common to all sub-sheets are connected in the normal way. Nets that connect individually to repeated sub-sheets are brought in as a bus, with one bus element connecting to each sub-sheet. In the example above, this is shown by placing the bus name (not including the bus range, e.g. P) on the wire and the sheet entry including the Repeat keyword. When the design is compiled, this bus is resolved into the individual nets (P1 through to P8) with one assigned to each channel; P1 connects to PD_1 sub-sheet, P2 connects to PD_2 sub-sheet, and so forth. 8. Create the parent sheet, Peak Detector.SchDoc and use the Place» Sheet Symbol command to create a sheet symbol to represent the next level schematic down, Bank.SchDoc. 8-4 In the example above, the Designator name of the sheet symbol is BANK. Therefore, the command Repeat(BANK,1,4) in the Designator field in the Sheet Symbol dialog will reference the Bank schematic four times (1,4) via the sheet symbol BANK. Note also that the net labels on the wires in the example above do not include a bus element number and the sheet symbol includes the Repeat keyword. When the design is compiled, this bus is resolved into the individual nets (OFF1 through to OFF4) with one assigned to each channel.

159 Multi-channel design tutorial Setting room and designator formats Once you have created the schematics, you can format the designator and room names that will map from the single logical component on the schematic to multiple physical instances on the PCB. Logical designators are assigned to the components of the source schematics. Physical designators are assigned to the components once they are placed in the PCB design. When creating multi-channel designs, the logical designators for the repeated channel components may be the same, but each component must have a unique physical designator in the PCB design. 1. Select Project» Project Options. Click on the Multi-Channel tab of the Options for Project dialog to specify the room and component designator naming formats. Room Naming 1. Click on the Room Naming Style drop-down list to choose the naming format you require for the rooms in your design. These rooms are created by default when you update the project schematics to the PCB. There are five styles available two flat and three hierarchical. Flat room name formats Flat Numeric with Names Flat Alpha with Names Hierarchical room name formats Numeric Name Path Alpha Name Path Mixed Name Path Hierarchical room names are formed by concatenating all channelized sheet symbol designators (ChannelPrefix + ChannelIndex) in the relevant channel path hierarchy. 8-5

160 Multi-channel design tutorial 2. As you select a style from the list, the image in the Multi-Channel tab (below) is updated to reflect the naming convention that will appear in the design. The image gives an example of a 2x2 channel design. The larger crosshatch regions represent the two upper level channels (or banks) and the shaded regions within represent the lower level channels (with two sample components shown in each). When the design is compiled, a room is created for each sheet in the design, including each bank and each lower-level channel. For the 2x2 channel design shown in the image, a total of six rooms will be created - one for each of the two banks and one for each of the four lower level channels. In our Peak Detector example, 37 rooms will be created one for the top level schematic sheet (1), one for each of the four banks (4) and one for each of the eight channels within each of the banks (32). 3. Use the Level Separator for Paths field to specify the required character/symbol for separating the path information when using the hierarchical naming styles, i.e. those styles that include the path. Component Naming There are no restrictions on the character used for the level separator; however, a single nonalphanumeric character is easier to read. There are several designator formats for naming components. You can choose a format or define your own using valid keywords. 1. Define the naming format you want for the component designators by selecting from the Designator Format drop-down list. There are eight predefined formats five flat and three that can be used in a hierarchical context. Flat designator formats $Component$ChannelAlpha $Component_$ChannelPrefix$ChannelAlpha $Component_$ChannelIndex Hierarchical designator formats $Component_$RoomName $RoomName_$Component $ComponentPrefix_$RoomName_$ComponentIndex $Component_$ChannelPrefix$ChannelIndex $ComponentPrefix_$ChannelIndex_$ComponentIndex 8-6

161 Multi-channel design tutorial The flat designator formats name each component designator in a linear progression, starting from the first channel. The hierarchical formats include the Room Name in the designator for a component. If the Room Naming style chosen is one of the two possible flat styles, then the style for the component designator will also be flat. However, if a hierarchical style has been chosen for Room Naming, the component designator will also be hierarchical because the path information will be included in the format. Defining your own designator format The Room Naming Style is only relevant for component naming if the $RoomName string is included in the Designator Format. You can also define your own component designator format by typing directly into the Designator Format field. The following keywords can be used when constructing the format string. Keyword $RoomName $Component Definition name of the associated room, as determined by the style chosen in the Room Naming Style field component logical designator $ComponentPrefix component logical designator prefix (e.g. U for U1) $ComponentIndex component logical designator index (e.g. 1 for U1) $ChannelPrefix $ChannelIndex $ChannelAlpha logical sheet symbol designator channel index channel index expressed as an alpha character. This format is only useful if your design contains less than 26 channels in total, or if you are using a hierarchical designator format. Compiling the project You must compile your project in order for any changes made to room and/or component designator formats to take effect. 1. Compile the project by selecting Project» Compile PCB Project. When the multi-channel design is compiled, there is still only one sheet shown in the Schematic Editor, however now, there are tabs displayed along the bottom of the schematic sheet in the design window, one for each channel (or bank). The tab names are the sheet symbol names plus the channel number, e.g. BANKA. 2. Once the design has been compiled, it is transferred to the PCB Editor in the normal way (Design» Update PCB). The transfer process will automatically create a component class for each schematic sheet in the design, a room for each component class and group the components in each class in their room, ready for placement. 8-7

162 Multi-channel design tutorial 3. After placing and routing one channel, select Tools» Copy Room Formats in the PCB Editor to copy the placement and routing of that channel to the other channels. Viewing the channel designator assignments To check that your multi-channel designators, you can view all components used in all the source schematic documents in the project in terms of logical and physical designators. To check the designators that are associated with components in a multi-channel design: 1. Select Project» View Channels to display the Project Components dialog which shows the logical and physical designators assigned to each of the components in the source schematic documents. The table shows the number of channels associated with a schematic name in the project. In the example above, the following room and component naming conventions were used: Mixed Name Path and $Component_$ChannelPrefix$ChannelIndex. Each channel will have the designator names augmented with channel number, e.g. designator C1 in the Peak Detector channel.schdoc becomes C1_PD1 for channel 1 through to C1_PD32 for channel 32 when it is updated to the PCB. Remember that there is always only one schematic sheet of the channel; the designator assignments for each channel are stored in a table (Project» View Channels). 2. Click on a Logical Designator to jump to that component in its source schematic. The component will display zoomed and centered in the main design window. The dialog remains open to allow you to jump to other components. 8-8

163 Multi-channel design tutorial 3. Click on the Component Report button to display the Report Preview dialog showing a print preview of the Project Components report. Click Print to print the report. The Print dialog displays. Click OK to send the report to the printer. 4. Choose Export from the Report Preview dialog to save the Project Components report as a file, for example as a spreadsheet (.xls) or a.pdf. Save the file and you can then open it in its appropriate program (e.g. Microsoft Excel or Adobe Reader) by clicking on Open Report. 5. Click on Close to exit the print preview mode and click OK to close the Project Components dialog. 8-9

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165 Board Shape & Sheet tutorial 9 Board Shape & Sheet tutorial Board shapes in DXP Modifying a board shape Using PCB sheets Displaying the sheet Adding a new sheet from a PCB template Keepouts Creating a keepout This tutorial covers board shapes, sheets, templates and keepouts used in DXP s PCB Editor. For more information about setting up the PCB workspace, such as grids, layers and design rules, see Designing the PCB in the Schematic capture, simulation and layout introductory tutorial. Board shapes in DXP The board shape defines the boundary, or extents, of the board in the PCB Editor. The board shape may also be referred to as a board outline and is essentially a closed polygon. It initially displays as a black area with the visible grid on by default when you create a new PCB document. It is used by DXP to determine the extents of the power planes for plane edge pull back, used when splitting power planes and for calculating the board edge when outputting design data to other tools, such as the 3D viewer. When a new board file is created by selecting File» New» PCB from the menus, a default board shape is created, sized 6,000 x 4,000 mils. The board shape can be resized, or redefined, using the commands in the Design» Board Shape sub-menu. PCB documents created using the PCB templates or the PCB Board Wizard have the board shape already correctly sized. Modifying a board shape You can change a board shape by redefining (redrawing) it or by moving the vertices. You can move the board shape around the sheet as well, with or without any placed objects. 9-1

166 Board Shape & Sheet tutorial You can change the color of the board shape by selecting Design» Board Layers & Colors (shortcut key L) and selecting a new color for the Board Area in the System Colors section of the Board Layers & Colors dialog. Redefining a board shape You can redefine the board shape if it does not already exist or you want to draw it again from scratch. If you need to change the entire board shape: 1. Select Design» Board Shape» Redefine Board Shape. The cursor will change to a large cross, the background will change to black and the original board shape will be displayed in green. 2. Click (or press ENTER) to create the corners of the new board shape. Press the SPACEBAR to change the corner style while you are defining the board shape. The Status bar at the bottom of the design window helps to locate the co-ordinates of the corners. 3. When you have defined the board shape, right-click or press ESC to finish. There is no need to fully close the polygon as DXP will automatically complete the shape by joining the first point to the last point placed. The visible grid will be drawn to fill the area defined by the new board outline. Defining the board shape from selected objects You can define an enclosed boundary, using lines and arcs, on a mechanical layer (or any layer) and use these objects to define the board shape. To define a board shape from selected objects: 1. Create an enclosed boundary on a mechanical layer that will define the board shape you require. Use the placement commands such as Place» Line or Place» Arc to create your new board shape. 9-2

167 Board Shape & Sheet tutorial 2. Select the new board shape boundary only. 3. Select Design» Board Shape» Define from Selected Objects and the board shape will be redisplayed to fit the selected boundary objects. Moving board vertices When modifying a board shape, e.g. resizing it, moving the board vertices will save you from having to redefine the entire board shape. 1. Select Design» Board Shape» Move Board Vertices. The board outline displays with editing handles and the cursor changes to a large cross, ready to select and move vertices. 2. Click on the vertex that you want to move and drag it to its new location. 3. You can create new vertices by clicking on the small crosses that appear midway along the line segments and dragging the new vertex into position. 4. Right-click or press ESC to finish your board shape. Moving the board shape Using the Move Board Shape command to reposition the board shape will move the board outline only. Any components and connections already placed will not be affected. If you need to reposition the board shape in relation to the design sheet, make sure the sheet is visible by enabling the Display Sheet option in the Board Options dialog (Design» Board Options). See Using PCB sheets in this tutorial for more information about using sheets in DXP. To move a board shape only: 1. Select Design» Board Shape» Move Board Shape and the outline will appear floating on the cursor. 2. Drag the board shape to its new location and click to place. To move a board shape along with any components and connections already placed: 1. Select all (Ctrl+A) or select the objects you need to move, including the board shape. 2. Click directly on a selected object and the cursor changes to a large arrow. Drag the selection bounding box to the new location on the sheet. Alternatively, select the objects required and select Edit» Move» Move Selection. Click within the selection to define a reference point, move the selection and click to place. 9-3

168 Board Shape & Sheet tutorial Using PCB sheets Sheets in the PCB Editor are a special drawing feature, controlled using the options in the Board Options dialog. When you create a new PCB file, a default sheet is automatically created with the default size of x 8000 mil. It is not shown initially but, when displayed, it appears as the white shape behind the board outline. Most of the PCB example files supplied with DXP (C:\Program Files\Altium\Examples) display the board on a white sheet which includes a border, grid reference and title block that have been drawn on one of the mechanical layers, Mechanical16. By placing objects on mechanical layers and then linking those layers to the sheet, you can create your own drawing templates which can be displayed or hidden. Sheets that include a border, grid reference and title block can be added to PCB files by copying from the existing PCB templates (C:\Program Files\Altium\Templates). The sheet size and location of the sheet can be defined manually, or the sheet can be resized automatically to fit the objects on the linked mechanical layer when you select View» Fit Sheet. Displaying the sheet To make the sheet is visible in the PCB Editor: 1. Select Design» Board Options and select the Display Sheet option in the Sheet Position section of the Board Options dialog. Click OK. 9-4

169 Board Shape & Sheet tutorial The sheet can be hidden at any time by disabling the Display Sheet option. All linked mechanical layers will also be hidden. 2. Select View» Fit Sheet to display the sheet. Alternatively, use the shortcut keys, V, H (View Sheet) or Z, S (Zoom Sheet). A white space appears around the board shape with the default size of x 8000 mil. 9-5

170 Board Shape & Sheet tutorial 3. You can change the color of the sheet by selecting Design» Board Layers & Colors (shortcut key L) and selecting a new color for the Sheet Area and Sheet Line in the System Colors section of the Board Layers and Colors dialog. Adding a new sheet from a PCB template You can add a new sheet, including the sheet border, reference grid and title block, at any time by copying the objects from the supplied DXP PCB template documents and pasting them into your PCB design document. DXP includes a set of pre-defined PCB templates located at C:\Program Files\Altium\Templates. Use the sheet size templates only, i.e. A.pcbdoc through to A0.pcbdoc. 1. Open the PCB document that you want to add the new sheet size to. Make sure that the existing default sheet is displayed to help you place the new sheet by pressing V, H (view sheet) or Z, S (zoom sheet). 2. Open an existing PCB sheet template that will fit all the objects on your PCB, e.g. A2.pcbdoc. To do this, click on PCB Templates in the New from Template section of the Files panel. If this option is not visible, click on the up arrows to the right of each section in the Files panel to contract the other options. The Choose existing Document dialog displays. Navigate to the PCB templates folder (C:\Program Files\Altium\Templates) and select A2.pcbdoc (for example) and click Open. The template is opened as a new PCB design document in the design window, named PCB1.PcbDoc. 3. Select all the contents of the template file (Ctrl+A) and copy (Ctrl+C) the contents to the clipboard. Click once to set a copy reference point. Close Pcb1.pcbdoc without saving. 9-6

171 Board Shape & Sheet tutorial 4. Switch to your PCB document by clicking on its tab at the top of the design window. Paste the new sheet into the existing PCB using Ctrl+V. The contents of the template are pasted onto Mechanical16 layer. 5. Now we need to show the Mechanical16 layer and link it to the sheet. Select Design» Board Layers & Colors to display the Board Layers and Colors dialog. Click on Show, Enable and Linked to Sheet. 6. Also turn on Single Layer Mode to always show the sheet regardless of the status of Single Layer Mode as enabled in the Display tab of the Preferences dialog (Tools» Preferences). Click OK to close the dialog. 7. Finally we can size the sheet to include the sheet border. Press V, H (to view sheet) or Z, S (to zoom sheet). The sheet fits to the extents of the objects on the layer linked to the sheet, i.e. it fits to include the sheet border defined on the Mechanical16 layer. 8. You can now modify the title block, for example, by switching to Mechanical16 layer and adding or deleting objects. The sheet will resize to include all objects when you press V, H (view sheet) or Z, S (zoom sheet) again. Keepouts The keepout is a separate entity to the board shape. A keepout shape, usually made up of placed keepout tracks, is required on the PCB Keepout layer if you intend to run the autorouter or autoplace 9-7

172 Board Shape & Sheet tutorial components. A keepout track is simply a track placed on the Keepout layer with the Keepout attribute enabled. A keepout is automatically generated if you create the PCB by using the PCB Board Wizard where you can nominate the distance of the keepout from the edge of the board shape. The dimensions generated by the PCB Board Wizard measure the keepout not the board shape size. The diagram below shows an example of a keepout outline generated on the Keepout layer by the PCB Board Wizard, indented 100mil from the edge of the board shape of 2000 x 2000 mil. A board keepout is also automatically included when using a PCB manufacturers template to create a new PCB, e.g. AT or Eurocard. The sheet size templates, e.g. A2.pcbdoc, do not include keepouts. Creating a keepout Since a keepout is required if you wish to autoplace components or autoroute the board, you will need to add the keepout yourself if you create a new PCB in the following ways: selecting File» New» PCB from the menus, or clicking on PCB File in the New section of the Files panel, using the PCB sheet size templates, e.g. A2.pcbdoc, by choosing PCB Templates from the New from Template section of the Files panel. Only a default board shape is created by these commands, so the keepout has to be added once the board shape has been defined. To create a keepout by placing keepout tracks: 1. Click on the Keep-Out layer tab so you will be placing the keepout tracks on this layer only. 2. Select Place» Keepout» Track. Click to define the vertex points of the keepout and create a closed polygon. 3. When you have finished placing the keepout tracks, right-click or press ESC to exit track placement mode. Now you have created your board shape, sheet and keepout, set the grids, layers and design rules and you are ready to start designing your board. Track placement modes are available when placing a keepout. Press SHIFT+ SPACEBAR to cycle through the modes. Press SPACEBAR to toggle between Start and End modes. Use BACKSPACE to remove the last placed track segment. Press TAB to display the Line Constraints dialog and change properties. 9-8

173 Editing multiple objects tutorial 10 Editing multiple objects Filtering, Selecting and Editing Multiple Objects The Basic Approach Finding Objects using the Navigator Panel Finding Objects using the Find Similar Objects dialog Modifying the Selected Objects Schematic Examples Changing the footprint for all capacitors of a certain value Changing the style of GND power ports Changing the length of pins in the schematic library Changing part of a net name on all schematic sheets PCB Examples Hiding all component comments Setting the font style for all component designators Changing the width of certain track segments in two routed nets (routed at multiple widths) Changing the size of a specific sized pad in all footprints in a library Using a Query to Edit Multiple Objects Selecting schematic components based on a parameter value and a footprint, then changing the component symbol Selecting the designator string for PCB components with a specific footprint Changing the width of certain track segments in two routed nets (routed at multiple widths) Finding all components with a specific footprint at a certain rotation Tips for Writing Queries Filtering, Selecting and Editing Multiple Objects PCB design is the process of capturing a logical design in the schematic, then representing them as a set of objects in the PCB workspace. Even for a small circuit, the schematic can include many components, each with numerous parameters, and the PCB workspace will end up containing a large number of design objects that make up the board. During the course of the design process, the properties of these objects will need to be changed as the designer works to balance out the design requirements, the fabrication requirements and the assembly requirements. The need to find, choose and modify objects is delivered using the new DXP data editing system. Using this system, you filter the design data to find what you want, you select it for editing, then edit it. This 10-1

174 Editing multiple objects tutorial document demonstrates how to perform filtering, selecting and editing of multiple objects in the workspace. The Basic Approach Finding objects in a densely packed workspace is not a trivial process. The DXP schematic and PCB editors includes a feature specifically designed for this task, called filtering. There are two basic approaches to finding the objects you want to edit in a densely packed design workspace. You can either start with all objects and filter down (using the Navigator or by writing a query), or start with one object and then find similar objects. The result for both is the same a view of just the objects you want to edit. In fact, both approaches can be used to find the same set of objects; the way you choose will be driven by which is more efficient in a given situation, and by personal preference. This tutorial first covers multiple object editing using the Navigator panel and the Find Similar Objects dialog, then explains how to do it using DXP s powerful query engine. Finding Objects using the Navigator Panel Filtering can be done in a number of ways perhaps the easiest way is to use the Navigator panel. The Navigator panel lets you browse by Components, Nets or pins. When you click on an entry in the Navigator, you filter the data in the workspace. You can also browse in the PCB panel, click on All Components to filter out everything except the Components on the board. Click on an individual component, say U1, to filter out everything except U1. There are highlight options at the top of the Navigator panel that control how the result set is highlighted you can Mask to fade out everything you don t want to edit, you can also Select and you can Zoom. There is also an option to disable automatic clearing of a previous filter only disable this when want to add the results of the current filter to the previous filter. Wait till you are familiar with how filtering works before experimenting with this option. Use the fade level of the filtered-out objects. button at the bottom of the editing window to control the Use the Navigator to quickly find objects Finding Objects using the Find Similar Objects dialog Often you will have an object visible on the screen which needs to be modified and you want to change other objects of the same kind. In this case, the best approach is to use the Find Similar Objects command. The easiest way to run this command is to right-click on the object and select Find Similar Objects from the menu. 10-2

175 Editing multiple objects tutorial The Find Similar Objects dialog will appear, displaying the properties of the object. There are two columns in this dialog the first column lists the properties of the object you clicked on, the second column you use to specify which of the properties to use to find similar objects by. Matching by Object Kind, Comment and Footprint before closing, otherwise use the OK button. Modifying the Selected Objects In the adjacent image, the dialog has been opened over a schematic component (Object Kind = Part). If you look at the find similar column, three properties are set to Same Object Kind, Comment, and Current Footprint. When the OK button is clicked, it will find all schematic Parts, with a comment string of 0.1uF and a footprint of RAD0.2, in all open schematic documents. Note that you do not have to leave the property values as they were when the dialog opened, for example if the Designator property was changed to C* and its Find option set to Same, then all objects with a designator starting with the letter C would be found. Like the Navigator panel, the dialog has highlight options, set these to control how the results will be presented. Use the Apply button when you want to test Once you ve filtered down and got the correct result set, you are ready to edit the selected objects. The easiest way to modify a set of selected objects is to use the object Inspector panel. This panel presents the properties of selected objects as a simple list; any changes you make are immediately applied to all selected objects. Use the F11 shortcut to toggle the Inspector panel on and off. When you modify a value in the Inspector, press Enter on the keyboard to apply the change. Alternatively, you can use the List view panel. This spreadsheet-like panel allows you to check the attributes of any of the objects in the Type in the new Footprint name and press Enter result set, as well as edit one or more objects. To modify a property of objects in the List view panel select them in the spreadsheet, then right-click on the column and choose Edit Selected from the menu. Again, after changing a value, press Enter on the keyboard to apply the change. Schematic Examples Following are some examples of editing multiple objects in schematics and schematic libraries. Remember to clear any existing filter before applying a new one, either by clicking the or pressing SHIFT+C. button, 10-3

176 Editing multiple objects tutorial Changing the footprint for all capacitors of a certain value 1. Right-click on the symbol of one of the capacitors being changed and select Find Similar Objects from the floating menu. 2. In the Find Similar Objects dialog, set the match by drop-down for Comment to Same, and Current Footprint to Same, as shown in the image. 3. Enable the Select Matching check box, and if the change is to apply across multiple sheets, select Open Documents in the drop down list, then click OK. Important Note: when you use the Find Similar Objects dialog to select the objects for editing, don t click on the schematic sheet or you will loose the selection. If you need to you can change documents by clicking on the document Tab at the top of the workspace. 4. Press F11 to pop up the Inspector panel, type the new footprint name in the Current Footprint field, then press Enter on the keyboard to apply the change. Finding all schematic comps with a Comment = 0.1uF and a Footprint = RAD Press SHIFT+C to clear the current filter. Changing the style of GND power ports 1. Right-click on a GND power port and select Find Similar Objects from the floating menu. 2. In the Find Similar Objects dialog, set the match by drop down for Text to Same (the Text value would be GND for this example). 3. Enable the Select Matching check box, and click OK. 4. In the object Inspector panel, change the Power Object Style to Bar. Changing the length of pins in the schematic library 1. Right-click on a component pin in the schematic library editor and select Find Similar Objects from the floating menu. 2. In the Find Similar Objects dialog, set the match by drop down for Length to Same (no need to do this if all pin lengths are already the same and you want to change all of them). 3. Enable the Select Matching check box. To apply the change across all components in the library, select All Components in the drop down list, then click OK. 4. Press F11 to pop up the Inspector panel, type in the new pin length in the Length field, then press Enter to apply the change. 10-4

177 Editing multiple objects tutorial Changing part of a net name on all schematic sheets Rather than using the Find Similar Objects dialog, or the Inspector or List panel, the easiest way to change a text string throughout a design is to use the Find and Replace Text dialog. This example changes all occurrences of the string INTERUPT, for INT. 1. Select Edit» Replace Text from the menus. 2. In the Text to Find field, type in the search text. In this example, it is INTERUPT*. Note the wildcard character has been included, that way all strings that start with INTERUPT will be found, for example INTERUPTA, INTERUPTB, etc. 3. If you want to replace each string completely with a new string, you would simply enter the new string in the Replace With field. However, if you want to perform a partial string substitution, you use the following syntax: {INTERUPT=INT} The curly braces denote string substitution, the string before the equals sign is the old string being replaced, the string after the Use the Find and Replace dialog to change strings across objects equals sign is the new string. For each string found, any characters before or after the old string are not effected by the change. For example, the string INTERUPTA becomes INTA, the string AD_INTERUPT5 becomes AD_INT5, and so on. 4. After entering {INTERUPT=INT} in the Replace With field, set the Sheet Scope to Open Documents, enable the Restrict to Net Identifiers option, and click OK to make the change. PCB Examples Following are a number of examples of editing multiple objects in PCB and PCB libraries. Hiding all component comments 1. Clear any existing filter. 2. Select Components in the drop down at the top of the Navigator panel, enable the Select check box, then click on All Components in the Component Classes field. All the components will be selected. 3. Open the Inspector panel, note that the number of selected objects is shown at the bottom of the panel. 4. Clear the Show Comment check box. Note that if there are a mixture of both visible and not visible comments you set the check box to the required state (clear in this case), then press Enter. You can use this technique to display hidden comments too. Changing the visibility of the Comment 10-5

178 Editing multiple objects tutorial Setting the font style for all component designators 1. Clear any existing filter. 2. Right-click on a component designator and select Find Similar Objects. 3. In the Find Similar Objects dialog, set the match by drop down for Designator to Same. 4. Enable the Select Matching check box, and click OK. 5. In the Inspector panel, set the Font to the required style and press Enter on the keyboard to apply the change. Changing the width of certain track segments in two routed nets (routed at multiple widths 1. Set the PCB navigation panel to Nets. 2. Select the required nets in the list. Note that you can sort the list by Net name, Node Count, or Routed length, and you can also sort by one column then subsort by another (hold the Shift key to sub-sort). 3. Right-click in the Net Items list to configure this list to only display Tracks. Then edit the width 4. Now click on Name to sort this list by the track width. It should now be straight forward to scroll through the list and select the set of track segments of the required width. 5. Display the Inspector panel, type in the new track Width and press Enter on the keyboard to apply the change. Filter and select the net segments in the panel Changing the size of a specific sized pad in all footprints in a library 1. Right-click on one of the pads to be changed in the PCB Library editor, and select Find Similar Objects from the menu. 2. In the Find Similar Objects dialog, set the match by drop-down for the Pad Shape and Pad X Size and Pad Y Size parameters to Same. 3. Enable the Select Matching and Whole Library check boxes and click OK. 4. In the Inspector panel, type in the new Pad X Size (All Layers) and press Enter, then type in the new Pad Y Size (All Layers) and press Enter. 10-6

179 Editing multiple objects tutorial Using a Query to Edit Multiple Objects Underlying DXP is a powerful query engine. This query engine allows precise targeting of design objects. As well as using it to filter and edit multiple objects, it is also used to scope design rules. Following are a number of examples of using queries to target and edit multiple objects. Selecting schematic components based on a parameter value and a footprint, then changing the component symbol Often you will want to target components (a parent object) based on one of their parameters (children). You can do this by writing a query. 1. Open the List panel (F12), and type HasParameter. 2. When you complete the keyword, a drop-down list of available parameter names will appear. Select the required parameter from the list. 3. Once the name has been selected, a list with available parameter values will appear. Select the required value (note that you can use a wildcard, make sure you enclose it in quote marks). 4. Click the Apply button to select the components. The following query finds all components that have a Voltage parameter with a value of 100V and a footprint of RAD0.2: HasParameter(Voltage,'100V') and HasModel(Pcblib,'RAD0.2',True) 5. The set of components that have both the correct voltage parameter and footprint will appear in the List panel. Select them all (Ctrl+A). 10-7

180 Editing multiple objects tutorial 6. With the components selected, right-click in the Library Reference column and choose Edit Selected from the menu. 7. One of the values will change to the edit mode, type in the new library reference and press Enter on the keyboard. Note that the component must be available from the list of available libraries in the Libraries panel. 8. The selected components will change to the new schematic symbol. Selecting the designator string for PCB components with a specific footprint The following example selects the designator string for all components that have a footprint of DIP Open the List panel (F12), enable the Mask, Select, Zoom and Clear Existing options, and type: IsDesignator And HasFootprint('DIP14') then click the Apply button, or press Enter. 2. To edit a property of the designators, say the string height, press F11 to display the Inspector panel, type in the new Text Height and press Enter to apply the change. Changing the width of certain track segments in two routed nets (routed at multiple widths Earlier in the tutorial there was an example of changing the width of certain track segments in two routed nets that had been routed at multiple widths, using the Navigator panel. This example shows 10-8

181 Editing multiple objects tutorial how to do this same edit using queries (assuming net names of +12V, -12V and an existing width of 25mils). 1. Open the List panel (F12), enable the Mask, Select, Zoom and Clear Existing options, and type: (InNet('+12V') or InNet('-12V')) and (width = 25) then click the Apply button, or press Enter. 2. To edit the width of the track segments, press F11 to display the Inspector panel, type in the new Width and press Enter to apply the change. Finding all components with a specific footprint at a certain rotation 1. To find all components with a footprint of RAD0.2, and a component rotation of 90 degrees, the following query is used: IsComponent and HasFootprint('RAD0.2') and (Rotation = 0) Tips for Writing Queries 1. Use the Query Helper to become familiar with the available keywords. Press the Helper button in the List panel to display the helper. 2. In the Query Helper, press F1 over a keyword to display on-line help. 3. Use the Mask field at the bottom of the helper to search for possible keywords and include the * wildcard character at the start of the string you are looking for. 4. Click the Check Syntax button before you close the helper. 5. Include quote marks around a variable, for example DIP14. There is an order of precedence used to resolve queries so include brackets to be sure that it is resolved in the correct sequence. 10-9

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183 Version Control System tutorial 11 Version Control System tutorial Interfacing to a Version Control System Adding projects and documents to the VCS Adding projects to the VCS Adding a document to the VCS Removing projects & documents from the VCS Removing a project from the VCS Removing a document from the VCS Refreshing the status Checking documents in and out Checking out documents from the VCS Checking in documents to the VCS Getting the latest copy Showing a document s VCS history Showing a document s properties Showing differences between documents Interfacing to a Version Control System You can interface directly between DXP and popular third party version control systems (VCS), including Visual SourceSafe. You can add or an entire project or individual documents within a project to your VCS. This tutorial looks at adding projects and documents to your VCS and then checking them out for use and checking them back in again to the VCS using the DXP menus. It uses the Visual SourceSafe version control software as an example only. For more information about your VCS, please refer to that software s documentation. When you run Version Control commands, you launch your version control software and open the database that the active project resides in. Once projects and documents have been added to the VCS, you could open your VCS from within DXP if required by selecting Project» Version Control» Run VCS. Your version control software will be started and the corresponding database and project folder for the active project will be opened. When using the other DXP Version Control commands however, you do not need your VCS open first. 11-1

184 Version Control System tutorial Adding projects and documents to the VCS Before using version control, you must add the project and related documents to your VCS. You may wish to create a storage area in your VCS first and then link to this area when adding the project and any of its associated documents, or you can create a new folder for your project files in the VCS database from within DXP. Adding projects to the VCS To add the selected project to the VCS: 1. Open the project that you wish to add to the VCS (File» Open Project). 2. Right-click on a Project name in the Project panel and select Version Control» Add Project to Version Control. 3. Log in to the VCS as applicable. The dialog below shows the login window for Visual SourceSafe. Enter the details required and click OK. 4. The Add to SourceSafeProject dialog displays. 5. Click on Create to create a new folder for the project in the VCS database. By default, the folder created for the project will have the project's name (without the extension). Alternatively, select a folder that has already been created previously using the VCS software. Click OK. The Add to Version Control dialog displays. 11-2

185 Version Control System tutorial 6. Select the documents in the project that you wish to come under version control. Click on Select All to easily select all the documents that have links to the project (as stored in the project file). Click OK. 7. The project file and selected documents are linked to the VCS and the icon [Checked in] is added to the VCS status column (second column) next to the document names in the Projects panel. Any documents that were not included in the addition will have an empty box [Not in version control] next to their names. Adding a document to the VCS Only documents that have already been added to a project in DXP can be added to the VCS. The project file has to be added (linked) to the VCS first as well. See Adding projects to the VCS above. Note that if the document you want to add is active (open), it should be saved prior to adding to the VCS, or else the last saved version of the file will be added to the VCS and not the open document. 1. Make sure that the document you wish to add to the VCS database is selected in the Projects panel. 2. Select Project» Version Control» Add to Version Control and login to the VCS as applicable. 11-3

186 Version Control System tutorial 3. The Add to Version Control dialog displays showing the document you selected from the Projects panel. 4. Click OK. The file will be added to the VCS database, in the same folder as the project file and the icon [Checked In] will appear next to the entry in the Projects panel. Note: If you have dragged the document into the VCS directly (from outside DXP), use the Refresh command (Project» Version Control» Refresh Status) and the document will appear as [Checked in] in the Projects panel. Removing projects & documents from the VCS Removing a project from the VCS By removing a project from the VCS, it will no longer be associated with version control and the link between DXP and the VCS software will be removed. Removing the project alone does not remove all associated project documents from your VCS however. They will appear as checked in again if the project is added back into the VCS and a refresh is carried out to resynchronize the system (Project» Version Control» Refresh Status). To remove a project to the VCS: 1. Right-click on the Project name that you want to remove in the Project panel and select Version Control» Remove Project from Version Control and log in to the VCS as applicable. 2. The Remove from Version Control dialog displays with the entry for the project already selected. The associated project documents are also listed and you can select any or all of these for removal from the VCS as well. 3. Click OK. The project and any other nominated documents will be removed from the VCS and the status for the all VCS entries under this project will change to an empty box [Not in version control] in the VCS status column in the Projects panel. 11-4

187 Version Control System tutorial Removing a document from the VCS To remove the selected document from your VCS: 1. Make sure that the document you wish to remove from the VCS is selected in the Projects panel. 2. Select Project» Version Control» Remove from Version Control and login to the VCS as applicable. The Remove from Version Control dialog displays with the entry for the document already selected. If the active or selected document is currently checked out, a dialog displays asking for confirmation to proceed with the removal from the VCS. This is especially important as other users may have checked out the file you want to remove from the VCS. 3. Click OK and the document will be removed from the VCS. The status for the removed document will change to an empty box [Not in version control] in the Projects panel. Refreshing the status At any time, you wish to make sure the status of your documents is up to date, use the Refresh Status command. This command can be used at any time, but is especially useful when you have performed an action, such as checking in or out, directly in the VCS software. 1. Select the Project» Version Control» Refresh Status command. 2. The link between the active project in DXP and the project that resides in the VCS is checked and the status of the project and its related documents is refreshed. The corresponding status is updated in the right-hand box next to each document's name in the Projects panel and can be one of the following: an empty box [Not in version control] - file has not been added to the VCS. [Checked in] - file is currently checked in to the VCS. [Checked out by me] - file is currently checked out by you alone. [Checked out] - file is currently checked out by more than one user (ASCII file) or another single user (binary file). [Checked out by me exclusively] - file is checked out by you alone and is a binary file. Checking documents in and out Once projects and documents have been added to the VCS, you can check them out when you wish to work on them and then check them back into the VCS when you have completed the work. 11-5

188 Version Control System tutorial Checking out documents from the VCS When you check out a document from the VCS, you actually check out the copy of the selected document that resides in your VCS. You should close and reopen the document after using this command, in order to display and work on the checked out version of the file. If the selected document is open in the main design window, you should close and reopen the document after using this command, in order to display and work on the checked out version of the file. Multiple checkouts Allowing multiple checkouts is a feature in your VCS software. For information on this feature, consult your VCS software documentation. It is not possible when working with binary files to have multiple checkouts of the same document. In this case, only one person may work on such a file at any one time. If you are the only person to check out a binary file, the Projects panel will reflect this using the icon [Checked out by me exclusively]. If a binary file is already checked out by another user, the icon will be [Checked out] and the command to check out this particular document will be unavailable. 1. Make sure that the document you wish to check out is selected in the Projects panel. 2. Select Project» Version Control» Check Out and login to the VCS as applicable. 3. The Check out file(s) dialog appears, with the document name(s) selected ready for checking out. 4. Click on the Advanced button provides access to advanced check out options for your particular version control software, as indicated below. 11-6

189 Version Control System tutorial 5. Click on OK and the version of the document stored in your VCS will be checked out to your work area. The status icon next to the document's name in the Projects panel will change to [Checked out by me exclusively], if you are the only person to currently have the file checked out. If more than one person has checked out the file, or if you have checked in your copy but it is still checked out by other users elsewhere, the status will be [Checked out]. Undoing a Checkout If you have previously checked out a document from your VCS and then wish to undo the check out, there is an Undo command for this action. If using this command and the document is still checked out by other users, the status icon for the document's entry in the Projects panel will remain as [Checked out]. The way that the local copy of the document is handled when using this command depends on the options set up in your VCS. For example, the local file may be overwritten with the previous version kept in the VCS, in which case all your changes will be lost. Consult your VCS documentation for more information. 1. Make sure that the document you wish to check out is selected in the Projects panel. 2. Select Project» Version Control» Undo Check Out and login to the VCS as applicable. 3. The Undo Check Out dialog appears, with the document name(s) selected. 4. The Advanced button provides access to advanced Undo Check Out options for your particular version control software. These could include how to treat the local copy of the file when performing the undo. 11-7

190 Version Control System tutorial 5. Click OK. The check out of the document will be cancelled and the previous version of the document will be retained in the VCS. The status icon for the document's entry in the Projects panel will change to [Checked in]. Checking in documents to the VCS When you have finished working on the document you had checked out, you need to check it back in to the VCS. Note that if the document you want to check in is active (open), it should be saved prior to checking in, or else the last saved version of the file will be checked in to the VCS and not the open document. 1. Make sure that the document you wish to check in is selected in the Projects panel. 2. Select Project» Version Control» Check In and login to the VCS as applicable. 3. The Check in file(s) dialog displays with the entry for the document selected ready for checking in. 4. Click OK. The document will be checked into the VCS, in accordance with check in options defined for your version control software. 5. The status icon for the document will change to [Checked in] in the Projects panel. If you have checked in your copy but it is still checked out by others elsewhere, the status icon for the document's entry in the Projects panel will remain as [Checked out]. Getting the latest copy You may need to get the latest copy of the selected document that resides in your VCS. The read/write status of the document copied to your work area depends on the options set in your VCS software. By default, the Get Latest feature normally places a read-only copy in your work area. Check your VCS documentation for details. 11-8

191 Version Control System tutorial 1. Make sure that the document you wish to get the latest copy of is selected in the Projects panel. If the selected document is also open, you should close and reopen the document after using this command, in order to display the latest copy of the file from the VCS. 2. Select Project» Version Control» Get Latest and login to the VCS as applicable. 3. The Get Latest Version dialog displays with the document already selected. 4. The Advanced button provides access to advanced options for your VCS software, such as how to treat a writeable copy of the file already in existence in your working folder. 5. Click OK. The latest version of the document stored in your VCS will be copied to your work area. Note that the document is not checked out. Showing a document s VCS history You may wish to view the history of the selected document with respect to its entry in your VCS. 1. Make sure that the document whose VCS history you wanted shown is selected in the Projects panel. 2. Select Project» Version Control» Show History and login to the VCS as applicable. You may get a History Option dialog prior to seeing the history of the document, such as the one below. This will depend on VCS software you are using. 3. Click OK and the history of the selected document inside the VCS will be shown. The information shown will depend on the version control software you are using. Consult your VCS software documentation for more information on these dialogs. Showing a document s properties You can display the property information about the selected document with respect to its entry in your VCS. Consult your VCS software documentation for information on these dialogs. 1. Make sure that the document you wish to show the properties of is selected in the Projects panel. 2. Select Project» Version Control» VCS Properties and login to the VCS as applicable. A dialog displays with property information relating to the selected document. This information will depend on the version control software you are using. The following dialog shows the properties displayed using Visual SourceSafe as the VCS. 11-9

192 Version Control System tutorial 3. Click on Report to print or copy the properties or save them to a file. 4. Click Close to exit the dialog. Showing differences between documents You can show the differences between the copy of the selected document in DXP and the master copy of the document in the VCS. Consult your VCS software documentation for more information on the show differences features. 1. Select the document in the Projects panel that you wish to show the differences between its copy and its master copy in the VCS. If you are showing differences between a copy of the active document in DXP and its master copy in the VCS, save the document first; otherwise the comparison is carried out on the last saved version of the file. 2. Select Project» Version Control» Show Differences. The Show Differences feature in your VCS will be launched and any dialogs that appear will depend on the VCS software you are using. The following results are expected: If the two documents being compared are identical, you will be shown that no differences exist. If the two files are ASCII files, the differences can normally be displayed. For binary files, you will only be notified that differences exist. This is because binary file differences cannot be viewed. 3. Click OK to close the dialog

193 Signal Integrity tutorial 12 Signal Integrity tutorial Signal Integrity in DXP Before running Signal Integrity Adding SI models using the Model Assignments dialog Modifying component models using the Model Assignments dialog Saving Models Manually adding Signal Integrity models to components Setting up passive components Setting up an IC Importing IBIS files Editing Pin Models Signal Integrity design rules in Schematic Signal Stimulus design rule Signal Integrity design rules in PCB Setting up the SI Setup Options Signal Integrity Setup Options in schematic only mode Using the Signal Integrity panel Viewing the screening results Setting Preferences Setting tolerances Preparing Analyses Selecting nets to analyze Setting the direction of bidirectional pins Editing Buffers Terminations Running the Analyses Using the Waveform Analysis window Choosing Source Data Working with waveforms Selecting the active chart and plot Selecting waveforms Viewing a waveform in its own wave plot Adding waveforms to a plot Editing user-defined waveforms Saving and recalling waveforms Creating new charts Creating new plots Using the SimData panel After analyzing your results

194 Signal Integrity tutorial Signal Integrity in DXP With DXP, you can analyze the Signal Integrity performance of a PCB from either the Schematic or the PCB Editors, evaluate net screening results against predefined tests, perform reflection and crosstalk analysis on selected nets and display the waveforms within the Design Explorer. This tutorial covers the following DXP Signal Integrity topics: Setting up design parameters before running a Signal Integrity analysis, such as setting up design rules, adding Signal Integrity models and checking the layer stack setup. Starting up Signal Integrity from the Schematic and PCB Editors Configuring the tests to be used in the net screening analysis Running further analysis on selected nets Terminating the signal line Preference settings Working with the resulting waveforms. Signal Integrity overview DXP includes pre-layout and post-layout Signal Integrity analysis capabilities. DXP s Signal Integrity Analyzer uses sophisticated transmission line calculations and I/O buffer macro-model information as input for simulations. Based on a fast reflection and crosstalk simulator model, the Signal Integrity Analyzer produces accurate simulations using industry-proven algorithms. Preliminary impedance and reflection simulations can be run from your source schematics prior to final board layout and routing. This allows you to address potential Signal Integrity issues, such as mismatched net impedances, before committing to board layout. Full impedance, signal reflection and crosstalk analysis can be run on your final board (or a partially routed board) to check the real-world performance of your design. Signal Integrity screening is built into the DXP design rules system, allowing you to check for Signal Integrity violations as part of the normal board DRC (Design Rule Checking) process. When Signal Integrity issues are found, DXP shows you the effects of various termination options, allowing you to find the best solution before modifying your design. Running a Signal Integrity analysis from a schematic only project You can perform a Signal Integrity analysis on the design using only a schematic whenever there is no PCB as part of the project. The schematic must be part of a project, as analyses will not run on documents opened as Free Documents. There is no crosstalk analysis available because routed nets are required for this analysis. 12-2

195 Signal Integrity tutorial When running in schematic only mode, default average track length and impedance can be defined using the SI Setup Options. The Signal Integrity Analyzer also reads the PCB design rules from the schematic for the stimulus and supply nets. These rules can be added as PCB Layout directives or Parameter Set directives on nets in the schematic. From the Schematic Editor, with the schematic open, select Tools» Signal Integrity from the menus. This will first allow you to setup any necessary signal integrity models and then show the signal integrity panel from where you can view initial results and perform further analysis. Running a Signal Integrity analysis from a PCB project When running a Signal Integrity analysis from a PCB document, the PCB must be part of a project along with the related schematics. Note that you could also run Signal Integrity from any of the schematic documents in the project and it will have the same effect as running it from the PCB. This will allow both reflection and crosstalk analysis to be performed. From the PCB Editor, select Tools» Signal Integrity which will proceed through the same process as that described above for the schematic only mode. You can now have some (or none) of the schematic components in the PCB but any that have been placed must be linked with Component Links. This can be checked by selecting Project» Component Links. Note also that any unrouted nets will use the Manhattan length between pins to calculate a track length estimate for analysis purposes. Before running Signal Integrity In order to run a successful Signal Integrity analysis of the design and obtain accurate results, the following has to be performed before running the analysis. It is important to note when simulating a net that to obtain meaningful simulation results you will need to have at least one integrated circuit (IC) with an output pin attached to that net. This pin will provide the stimulus for the net, giving the desired simulation results. Resistors, capacitors and inductors, for example, are passive components without a driving source and will therefore not provide simulation results on their own. The associated Signal Integrity model type for each component has to be correct. This is achieved via the Model Assignments dialog or by manually setting the correct entry for the Type field in the Signal Integrity Model dialog, when editing the Signal Integrity model associated to the component placed on the schematic source document. If this entry is not defined, the Model Assignments dialog will attempt to guess the type of the component based on its characteristics. For more information, see Adding Signal Integrity models to components using the Model Assignments dialog. There must be Supply Nets design rules. Generally, there should be at least two rules, one for power nets and one for ground nets. The scope for these can be either net or net class. Supply 12-3

196 Signal Integrity tutorial nets cannot be analyzed in Signal Integrity. For more information, see Signal Integrity design rules in Schematic or Signal Integrity design rules in PCB. A Signal Stimulus design rule may be set up. You only need a stimulus rule if you want to override the default stimulus, so this is generally not required. The layer stack for the PCB must be set up correctly. The Signal Integrity Analyzer requires continuous power planes. Split planes are not supported, so the net that is assigned to the plane is used. If they are not present, they are assumed, so it is far better to add them and set them up appropriately. The thickness of all Layers, Cores and Prepreg must also be set correctly for the board. Use the Design» Layer Stack Manager command to set up the layer stack in the PCB Editor. When running Signal Integrity in the schematic only mode, a default two layer board with two internal planes is used. You could create a blank PCB with a layer stack set up if more control was required. Adding SI models using the Model Assignments dialog The simplest means for adding signal integrity models to your design is to use the Model Assignments dialog. 1. Select Tools» Signal Integrity from the menus. If you are just starting signal integrity on a project and there are components which do not have signal integrity models attached, you will be prompted by the Errors or warning found dialog to set up the model assignments using the Model Assignments dialog. Alternatively, if you have clicked Continue and the Signal Integrity panel is visible, it is possible to enter the Model Assignments dialog at any time by clicking the Model Assignments button. Note that doing so will cause all results to be cleared and recalculated since any changes to model assignments invalidate any existing results. If models have been already set up for all components, the SI Setup Options dialog will display. See Setting up the SI Setup Options later in this tutorial for more information. 2. If you click on Model Assignments in the Errors or warnings found dialog, the Signal Integrity Models Assignments dialog displays. 12-4

197 Signal Integrity tutorial When run, the Model Assignments dialog attempts to make educated guesses as to the necessary signal integrity model required for each component that does not contain a signal integrity model. All components, including those with models already defined (and the model information) will be displayed in the Model Assignments dialog. Each component will be assigned a status as described below. Status No match Low confidence Medium confidence High confidence Model found User modified Model added Definition The Model Assignments dialog was unable to find any characteristics linking this component to a particular type. It will likely need modification from the user to be set up correctly. The Model Assignments dialog has selected a type for this component, but there was not strong evidence. The Model Assignments dialog has selected a type for this component and has reasonable confidence for the guess. The Model Assignments dialog has selected a type for this component and it fits most of the characteristics usually associated with this type of component. An existing model was found for this component. A component will change to this status once the user has modified it from the Model Assignments dialog s initial guess. This status is used when the user has used the Model Assignments dialog to modify the schematic document to save the new model. 12-5

198 Signal Integrity tutorial Modifying component models using the Model Assignments dialog 1. Select the component that you want to modify its model. 2. Select the correct type. There are seven types of components for Signal Integrity resistor, capacitor, inductor, diode, BJT, connector and IC. The type of each component can be selected via a dropdown in that column or by using the right-click menu. 3. Set the value for a resistor, capacitor or inductor. If possible, the Model Assignments dialog will attempt to place the correct value for the component in this column based on the comment field and parameters on the component. If this requires modification (or is not present), this should be done at this point. The special case of part arrays (such as resistor arrays) is done via a separate dialog accessed by clicking in the column (see Manually adding SI models to components for more details). 4. If the component is an IC, the choice of technology type is important as this will determine the characteristics of the pin models used in simulation. This can be selected via the dropdown list in the column or accessed through the right-click menu (Change Technology). 5. Finally, it may be necessary to specify more detail than allowed in the Model Assignments dialog, such as for IBIS models. This can be achieved by selecting Advanced from the right-click menu. See Manually adding SI models to components for more details on this process. Saving Models Once models have been chosen for any or all of the components, the schematic documents can be updated to permanently store this information. 1. Check the Update Schematic column in the Setup Signal Integrity dialog for all components that are to be updated. Then click the Update Models in Schematic button. 2. All new Signal Integrity models (or modified existing ones) for each selected component will be added to the schematic documents. The schematic documents will need to be saved later. It is not necessary to save models to proceed with the Signal Integrity analysis process. If models are not saved, the analysis will proceed with all models configured as they are currently shown in the Model Assignments dialog. However, the next time the Signal Integrity tool is used, any changes will have been lost. Manually adding Signal Integrity models to components Signal Integrity models are linked into the integrated components. Signal Integrity models can also be included in the new integrated component libraries. 1. To add a Signal Integrity model to a placed component in the Schematic Editor, open the component s Component Properties dialog by double-clicking on it. 12-6

199 Signal Integrity tutorial 2. Click Add in the Model List and select Signal Integrity as the Model Type in the Add New Model dialog. Click OK. The Signal Integrity Model dialog displays. 3. Set up your model and click OK. Setting up passive components When setting up parts such as resistors and capacitors, it is usually sufficient to enter a type and a value. The value can be entered in the Value field and can be set as a parameter for the whole component. There is also support for components like resistor arrays. This can be achieved by, after selecting the component type, clicking the Setup Part Array button in the Signal Integrity Model dialog. The Part Array Editor dialog allows the connections between pins and the value/model for those connections to be configured. 12-7

200 Signal Integrity tutorial Setting up an IC There are several alternatives when setting up an IC type model. 1. After selecting the type (IC), it is sufficient to simply choose a technology type. This will ensure that when simulating this component, the appropriate pin models for that technology will be used. 2. If more control is required, it is possible to assign specific technologies or pin models to individual pins. This can be done by selecting from the drop-down lists for the pins in the pin list at the bottom of the Signal Integrity Model dialog. Note that any changes here will override the base technology for the component. Importing IBIS files Another important option is the ability to import IBIS files. 1. To use an IBIS (Input/Output Buffer Information) file to specify an IC model s input and output characteristics, click on Import IBIS in the Signal Integrity Model dialog. Select the IBIS file from the Open IBIS File dialog and click Open. The IBIS Converter dialog displays. 2. Select the required component contained in the IBIS file. DXP will read the IBIS file and import the pin models from the IBIS file into the library of installed pin models. If a duplicate model is found, you will be asked if you wish to override the existing model. Additionally, all pins on the component will have the appropriate pin model assigned as specified in the IBIS file. 3. A report will automatically be generated stating which pins were successfully and unsuccessfully assigned. Further customization is possible by manually selecting the models for the appropriate pins as described above. 4. Click OK to complete importing the IBIS information and return to the Signal Integrity Model dialog. 12-8

201 Signal Integrity tutorial Editing Pin Models It is possible to add or edit an existing pin model by specifying various electrical characteristics of that pin. Note that this is also available for other types such as BJTs, Connectors and Diodes. 1. To modify pin models, click on the Add/Edit Model button in the Signal Integrity Model dialog, if this button is available for that type. The Pin Model Editor dialog displays. 2. Make the necessary changes and click OK. 3. If this is a new pin model, that model will now be available for selecting on the pins in this (and other) components. Signal Integrity design rules in Schematic PCB specific design rules for Signal Integrity can be defined in the schematic if they are added as parameters. For Signal Integrity analysis, we need to add a PCB rule to identify the supply nets and their voltage. We will add a PCB directive to each of the supply nets on the schematic. To add the supply nets design rule in the schematic: 1. Select Place» Directives» PCB Layout. The directive will appear floating on the cursor. 2. Press the TAB key to display the Parameters dialog with an undefined rule already added. 3. Select the undefined rule and click on Edit. The Parameter Properties dialog displays. 12-9

202 Signal Integrity tutorial 4. Click on Edit Rule Values to display the Choose Design Rule Type dialog where the rule type can be chosen. 5. Scroll down to the Signal Integrity rules and select Supply Nets. Click OK. The Edit PCB Rule (From Schematic) dialog displays. 6. Enter the voltage for this supply net and click OK. Close all the dialogs by clicking OK. 7. Now you can place the PCB Rule directive on the appropriate net. A dot will appear when the directive is properly attached. After transferring the design to PCB layout, the rule is added to the PCB design rules (available for viewing and editing in the PCB Editor using the Design» Rules command). 8. Now create another PCB Rule directive for the GND net (voltage = 0) and any other supply nets in the design. 9. Right-click to end directive placement mode. Note that in the Schematic Editor, the scope of the rule (the set of objects that the rule will target) is defined by where the parameter is added, e.g. on a wire or pin. In the PCB Editor, the scope of a rule is defined within the rule itself

203 Signal Integrity tutorial Signal Stimulus design rule The other design rule that can be set up from within the Schematic Editor is the Signal Stimulus rule. When this rule is run, the stimulus is injected at each output pin on the net being analyzed. This requires a design rule that uses a scope of all, so you need to create a sheet parameter for this rule. If you do not set up this rule, the default rule options are used. 1. Select Design» Document Options in the Schematic Editor and click on the Parameters tab in the Document Options dialog to add a sheet parameter. Click on Add as Rule to display the Parameter Properties dialog. 2. Click on Edit Rule Values to display the Choose Design Rule Type dialog, scroll down to the Signal Integrity rules and select Signal Stimulus. Click OK. The Edit PCB Rule (From Schematic) - Signal Stimulus dialog displays. 3. Choose the stimulus kind, start level and times. Close the dialogs by clicking OK. Signal Integrity design rules in PCB Signal Integrity parameters, such as overshoot, undershoot, impedance and signal slope requirements, can be specified as standard PCB design rules. Select Design» Rules in the PCB Editor to set up these rules. You can also set up these rules using parameters in the Schematic Editor and they will appear in the PCB Rules and Constraint Editor dialog after transferring the design to PCB layout

204 Signal Integrity tutorial These rules have two purposes. One is when running the standard DRC checks from within PCB; the board can be checked against these rules using the standard screening analysis. The second use for these rules is when using the Signal Integrity panel. These rules can be configured and enabled as tests and the panel will graphically display which nets have failed which tests. Setting up the SI Setup Options When you select Tools» Signal Integrity and all components have models assigned, the SI Setup Options dialog displays the first time you run this command on an open project. 1. Set the track impedance and average track length as required. These routing characteristics are only required if there are any nets not yet transferred to a PCB or unrouted nets in the PCB. Note that the Supply Nets and Stimulus tabs only display in schematic only mode. 2. Click on Analyze Design to run the initial default screening analysis and display the Signal Integrity panel from where you can further select the nets to analyze for reflection or crosstalk. Four default tolerance rules and any Signal Integrity rules set in the schematic or PCB are all enabled and run the first time the design is 12-12

205 Signal Integrity tutorial analyzed. These tolerances can be set later in the Signal Integrity panel by clicking on the Menu button and selecting Set Tolerances. Signal Integrity Setup Options in schematic only mode 1. If there is no PCB available in the project, you can change the SI Setup Options in the Signal Integrity panel at any time by clicking on the Menu button and selecting Setup Options. The SI Setup Options dialog displays. 2. The Track Setup tab allows configuration of the default length of tracks when simulating. This is not used when a PCB is present as PCB uses width rules, i.e. if the Manhattan length is not checked, PCB uses this value. Set the Track Impedance in this tab as well. 3. Click on the Supply Nets and Stimulus tabs to display and enable net and stimulus rule information. These tabs allow another interface for defining these characteristics other than the normal method of providing rules on the PCB or schematic. Using the Signal Integrity pane After performing any initial set up, the Signal Integrity panel will be loaded with data from the screening analysis that has just been run. The results of this analysis and a display of which nets have passed the various tests are displayed in the list on the left side of the panel. Note that there is only one copy of this panel in the system so running Tools» Signal Integrity again will clear the existing panel and reload it with a new set of results. This may be used to refresh the results after making changes to either the PCB or Schematic documents in the project or when starting to analyze a new project

206 Signal Integrity tutorial Viewing the screening results The initial screening analysis provides a fast simulation of many nets to enable you to get more information and identify critical nets for closer examination, such as detailed reflection and/or crosstalk analysis. The left hand side list displays the results of this analysis. Each net can be in one of three categories: Passed; Failed or Not Analyzed. A Passed net had all values inside the bounds defined by the tests. A Failed net had at least one value outside the defined tolerance levels. Any values that are failed are colored in light red. A Not Analyzed net could not be screened for some reason. To view the reason, right-click (or click on Menu), select Show/Hide Columns and enable the Analysis Errors column. Failed nets Common reasons for a failure to analyze a net in screening include containing a connector, diode or transistor, and no output pins or multiple output pins. When nets are screened which contain bidirectional pins and there is no dedicated output pin in the net, each bi-directional pin is simulated separately as an output pin. The worst-case result from these simulations is displayed. Note that even though a net could not be analyzed for screening, it may still be able to be checked in reflection and crosstalk simulations. It is possible for nets to have other errors that will lead to incorrect analysis results in both screening and further simulations. These nets are highlighted in bright red. Also, nets that have been simulated (i.e. nets that are not yet routed on a PCB) are colored in light gray. Checking Failed or Not Analyzed nets To view the cause of a Failed or Not Analyzed net: 1. If the nets are highlighted in bright red, select a net and then right-click and select Show Errors. This also adds messages to the Messages panel, which can be cross-probed to repair any issues. 2. To view all available information for a selected net, right-click and select Details. The Full Details dialog shows all the information calculated from the screening analysis and other basic information

207 Signal Integrity tutorial 3. Select Cross Probe from the right-click menu (or click on Menu) to cross probe (jump) to the selected net on either the schematic or the PCB. Use the F4 shortcut key to toggle display between the Signal Integrity panel and your design. 4. Display which nets are coupled to either a single net or a group of nets by selecting the desired nets and then right-clicking and selecting Find Coupled Nets. This will select all nets that are coupled to these selected nets. The criteria for which nets are considered coupled can be configured in the Preferences dialog (accessed by clicking the Menu button and selecting Preferences in the Signal Integrity panel). 5. Useful information can be copied to the clipboard and pasted into other applications for further processing or reporting. Select the nets required and choose Copy from the right-click menu. Additionally, the displayed information can be customized by selecting which columns will be shown using the Show/Hide Columns command from the right-click menu. 6. A report highlighting the results generated by the analysis is also available by selecting Display Report from the right-click menu in the Signal Integrity panel. This opens the report file Signal Integrity Tests Report.txt in the Text Editor and adds it to the project. Setting Preferences You can specify various preferences that apply to all the analyses that you have defined. These include general settings, integration method and accuracy thresholds. Any changes made to the preferences will apply to all projects. All preference settings are stored in the file named SignalIntegrity.ini, which is located in the C:\Documents and Settings\User_name\Application Data\Altium folder

208 Signal Integrity tutorial 1. Click on the Menu button in the Signal Integrity panel and select Preferences to open the Signal Integrity Preferences dialog. 2. Click on the related tab to set up preferences and click OK. 3. All Signal Integrity preferences can be returned to their defaults by clicking on the Defaults button in the Signal Integrity Preferences dialog. General tab Use this tab to set the error handling options that show hints and/or warnings when errors exist in the design that relate to performing a Signal Integrity analysis. Any hints or warnings encountered will be listed as messages in the Messages panel. If the Show Warnings option is enabled and warnings exist, a warning confirmation dialog will appear when trying to access the Signal Integrity panel. Additionally, you can opt to hide the Signal Integrity panel after choosing to display waveforms. You can also define the default units for Signal Integrity measurements, whether plot titles and FFT charts will be displayed when the resulting waveforms are shown in Waveform Analysis window. Configuration tab The Configuration tab defines various simulation-related thresholds, such as the maximum distance between coupled nets and the minimum length to be considered a coupled section. Integration tab This tab defines the numerical integration method used for analysis. The Trapezoidal method is relatively fast and accurate, but tends to oscillate under certain conditions. The Gear methods require 12-16

209 Signal Integrity tutorial longer analysis times, but tend to be more stable. Using a higher Gear order theoretically leads to more accurate results, but increases analysis time. The default is Trapezoidal. Accuracy tab The Accuracy tab in the Signal Integrity Preferences dialog defines tolerance thresholds and limit settings for various computational algorithms involved in the analysis. DC Analysis tab Use this tab to define tolerance thresholds and limit settings for various parameters associated with DC Analysis. Setting tolerances Four default tolerance rules and any Signal Integrity rules set in the schematic or PCB are all enabled and run the first time the design is analyzed. 1. To enable or disable these rules, click on the Menu button in the Signal Integrity panel and select Set Tolerances. The Set Screening Analysis Tolerances dialog displays. 2. Click on the Enabled checkbox next to a rule type to enable that rule to run when the design is analyzed. 3. Click on PCB Signal Integrity Rules (if not in schematic only mode) to open the PCB Rules and Constraints Editor dialog where you can add or modify any Signal Integrity rules required. Click OK until you return to the Signal Integrity panel

210 Signal Integrity tutorial Preparing Analyses Before running the analyses, we must select the nets to further analyze. We can also Edit Buffers to view or change the component part technology and pin properties, and add terminations to nets, if required. Selecting nets to analyze To perform further analysis on nets (reflection and/or crosstalk) the nets must be selected in the right hand list of the Signal Integrity panel. 1. Double-click on a net in the left hand list to select it and move it to the right hand list. Alternatively, use the arrow buttons to move nets to and from this selected state. You can multiselect nets in the left hand list by holding down the Shift or Ctrl keys. 2. Once nets are in this selected state, it is possible to perform further configuration for them before running a simulation. Setting victim and aggressor nets In the case of Crosstalk analyses, it is necessary to set a victim or an aggressor net. Note that due to the nature of the analysis, this functionality is only available when two or more nets have been selected (moved to the right hand list). 1. Select a net in the right hand list of nets, right-click and select Set Aggressor or Set Victim as required. The status of the net is updated. 2. To unset the nets, select Clear Status from the right-click menu. Setting the direction of bidirectional pins It is possible to set the direction of bidirectional pins in a given net. To set the direction: 12-18

211 Signal Integrity tutorial 1. Select the affected net in the top right hand net list. This will then display a list of pins for that net below. 2. From the list of pins, change the in/out status for each selected bidirectional pin by right-clicking and choosing a status from the right-click menu. These in/out settings will be saved with the project for the next time you use this panel. 3. You can also cross probe to the relevant schematic or PCB document by selecting the Cross Probe options from the right-click menu. Editing Buffers You may wish to view or change the component part technology and pin properties, such as input and output models and pin direction. You can only modify components that are attached to the currently selected net in the right net list. Using the Edit Buffer option under the right-click menu in the list of pins, gives access to the component s data dialog. Note that you are really editing the properties of a pin rather than the whole component, even though you can change the component s technology. Any changes you make using the Edit Buffer button will override any technology/pin model setup created when you set up the Signal Integrity model in the schematic. 1. The dialog and options that appear will depend on the type of component the pin belongs to, e.g. resistor, IC, BJT, etc. The Integrated Circuit dialog shown is for an IC component type. 2. The Part Technology, Input Model and Output Model fields are context-sensitive. When you choose a Component Part Technology, the default models of the part are taken from this technology. 3. Choosing a Pin Technology and Direction will display a list of relevant input and/or output models to select from. Changes to the technology and direction are used locally in the analysis only and these will not be saved when the panel is reset. Make any necessary changes and click OK. Terminations The oscillations apparent on a signal waveform are due to multiple reflections on the associated transmission line (trace). These reflections, or ringing, occur most often in PCB designs because of driver/receiver impedance mismatch usually where there is a low impedance driver and a high impedance receiver. Getting good signal quality at the load would ideally mean zero reflections (no ringing). The level of ringing can be reduced to an acceptable level for the design using a termination

212 Signal Integrity tutorial The Signal Integrity panel incorporates a termination advisor, which enables you to insert 'virtual terminations' into a net at a location you define. In this way, you are free to test various termination strategies, without making physical changes to your board. Termination simulations available are Series R, Parallel R to VCC, Parallel R to GND, Parallel R to VCC and GND, R and C to GND, Parallel C to GND and Parallel Schottky diodes. Each termination type can be enabled or disabled in the termination list. When a reflection or crosstalk analysis is run, each enabled termination type will be tried and produce a separate set of waveforms. When the Serial Resistor termination is used, it will be placed on all output pins in the selected net. For other termination types, the termination will be placed on all input pins in the net. To achieve the best results for the terminations, it will also be necessary to set the value of the parts involved based on the characteristics of the net. 1. When a termination is selected, a diagram showing that termination is displayed below. This diagram will allow the setting of both minimum and maximum values for the resistors and capacitors used in the terminations. 2. Minimum and maximum values are used when the sweep count (shown in the list of terminations) is set to a number greater than one. 3. For more information about a termination type, select it and click the Help (?) button. If you enable the Suggest option, suggested values will be calculated (according to the formula noted in the information popup for each termination type) and displayed in light gray. You can accept these values or disable the Suggest option and enter your own values as required. 4. If you want to set up sweeps, ensure Perform Sweep is enabled and set the number of Sweep Steps required when the analyses are run. Note that a separate set of waveforms will be generated for each sweep for comparison purposes. Placing a termination on the schematic Once the waveforms have been created and the optimum termination detected, it may be desirable to place that termination directly on the schematic sheet. This can be achieved by the right-click menu in the termination list. Note that any placement will only apply to the currently selected net. If you wish to actually place the selected termination circuit on the schematic rather than just use it as a virtual termination : 1. Right-click in the Termination section of the Signal Integrity panel and select Place on Schematic

213 Signal Integrity tutorial 2. The Place Termination dialog displays allowing the setting of various properties such as which library components to use for the termination parts, whether to use automatic or manual placement, whether to place on all applicable pins or just the selected pin and the exact values to be used for the parts. Click OK to continue. 3. The Signal Integrity Analyzer finds the source schematic document that the pin belongs to. Then, in a free space on the document, it will add the necessary parts with the correct values (resistors, capacitors or whatever is required) and the power objects. Connect this termination circuit to the appropriate pin in the schematic. Note that it will still probably be necessary after this to wire the components correctly to the pin. Additionally, if there is a PCB involved as well, these will need to be synchronized and routed in the PCB. Synchronize the PCB to add these parts as well by selecting Design» Update PCB. Running the Analyses 1. Once the nets have been configured as necessary (and any termination options chosen), click the Reflection Waveforms or the Crosstalk Waveforms button to generate the waveforms. 2. The analysis commences and a simulation waveform file (PCBDesignName.sdf) is generated. This file appears in the Projects panel under the Generated SimView Data Files folder and opens as a separate tab, displaying the results of the analyses in the Waveform Analysis window of the Simulation Data Editor. 3. For each net you have selected, a chart is generated and displays in the Waveform Analysis window

214 Signal Integrity tutorial Reflection For a Reflection analysis, one or more nets can be simulated. The number should be kept to a reasonable amount however, as analysis time will increase considerably when analyzing high numbers of nets. The Signal Integrity Analyzer calculates voltages at nodes of a net using routing and layer information from the PCB and associated driver and receiver I/O buffer models. A 2D-field solver automatically calculates the electrical characterization of the transmission lines. Modeling assumes that DC path losses are small enough to be ignored. For each net that has been selected, a chart is generated as the result of the simulation with its tab in the Waveform Analysis window marked by the name of the net. The chart will contain waveforms for all termination options

215 Signal Integrity tutorial Crosstalk For a Crosstalk analysis, at least two nets must be taken over. Two or three nets would normally be considered at any one time when performing a crosstalk analysis, usually a net and its two immediate neighbors. The level of crosstalk (or the extent of EMI) is directly proportional to the reflections on a signal line. If the signal quality conditions are achieved and reflections are brought down to a near-negligible level through correct signal termination, i.e. the signal is delivered to its destination with minimal signal stray and crosstalk will also be minimized. See Termination for more information. In a crosstalk analysis, all nets will be displayed in a chart named Crosstalk Analysis. Using the Waveform Analysis window The Simulation Data Editor's Waveform Analysis window comprises one or more tabs that correspond to the different simulation analyses performed. Each tab contains a chart that can contain multiple wave plots. A wave plot can have multiple waveforms and a waveform represents the simulation data. From this window, you can display up to four scaled plots simultaneously. Choosing Source Data The initial source data consists of all nets taken over during the Signal Integrity setup and listed in the Waveforms section of the SimData panel. You can further define the list of possible source simulation waveforms that can be used in the active chart. 1. Select Chart» Source Data, or click on the Source Data button in the Sim Data panel and the Source Data dialog displays. The dialog lists all source simulation waveforms that can be used with the active chart. 2. Clicking the Create button will open the Create New Waveform dialog, from where you can define a new waveform by entering a series of X Y value pairs for a series of data points, or create a custom sine or pulse wave

216 Signal Integrity tutorial 3. Create a new signal waveform and click on Create and the waveform will be added to the available waveform list in the SimData panel. 4. The Source Data dialog also enables you to store any of the waveforms as ASCII text files (WaveformName.wdf). These waveform files can be recalled (loaded) into the list at any time. 5. You can edit user-defined waveforms, generated using the Create button, by clicking on the Edit button. See Editing user-defined waveforms for more information. Working with waveforms Selecting the active chart and plot Select a chart by clicking on its tab name at the bottom of the Waveform Analysis window. Make a particular plot active by clicking anywhere within the area of the wave plot. Document Options If the Number of Plots Visible option is set to All in the Document Options dialog (View» Options), the active wave plot is distinguished by a black solid line around its waveform name section. If the Number of Plots Visible option is set to 1, 2, 3 or 4, the active wave plot is distinguished by a black arrow at the left hand side of its display area. Selecting waveforms A waveform is selected by clicking on its name in the Waveform Analysis window. A selected waveform will become bolder in color, a dot appears next to the name and the other waveforms will become 12-24

217 Signal Integrity tutorial masked (dimmed). Click on the Mask Level button to set the masking contrast and use the Clear button (shortcut Shift+C, or ESC) to clear any masking and display all for selection. You can also use the arrow keys or the mouse wheel to move up and down the waveform names. If there are more waveform names than can be displayed on the plot, click on the scrolling arrows that appear to see the entire list. You can highlight all waves in the same sweep if you enable the Highlight Similar Waves option in the Document Options dialog (View» Options) Zooming in on waveforms You can drag a selection box around a section of a waveform to zoom in for a closer look. To view the entire waveform again, select Fit Waveforms from the right-click menu. Moving waveforms If you wish to move a waveform from one wave plot to another, click on the waveform name and drag it to the name area of the required wave plot. Viewing a waveform in its own wave plot If you wish to view a waveform in its own wave plot 1. Make sure the Number of Plots Visible is set to All (View» Options). 2. Click on the waveform name and drag to either an existing blank wave plot or to a point beyond the last wave plot in the chart. A new wave plot is created. Adding waveforms to a plot To add a new waveform into the active wave plot of the current chart: 1. Make the wave plot that you want to add the new waveform to active in the Waveform Analysis window by clicking anywhere within the area of the wave plot. 2. Select Wave» Add Wave and the Add Wave to Plot dialog displays

218 Signal Integrity tutorial 3. Choose a waveform from the list of all available simulation waveforms. If required, you can also create a mathematical expression that uses one or more base waveforms to create a new waveform by adding functions to the expression. 4. Click Create and the waveform will be added to the active wave plot. Editing user-defined waveforms While you can edit user-defined waveforms that have been manually created using the Create New Waveform dialog, you cannot edit waveforms that have been generated as a result of design simulation. To change these waveforms, you would need to change the circuit, PCB or the setup and rerun the Signal Integrity analysis. The Edit Wave command allows you to also create new expressions from existing waveforms. 1. Make sure that the waveform you wish to edit is selected in the Waveform Analysis window by clicking on the waveform name. 2. Select Wave» Edit Wave. The Edit Waveform dialog displays. 3. Use this dialog to either create a new waveform using a mathematical expression involving the selected waveform, or change the waveform completely by choosing a new waveform from the list of all available waveforms. Saving and recalling waveforms You can save waveforms as ASCII text files by selecting Tools» Store Waveform and saving it as in the format of WaveformName.wdf. A.wdf file contains the waveform as a series of data points, each represented by an X Y value pair. Please note that once user-defined waveforms have been stored and recalled, they can no longer be edited. Recall a saved waveform by selecting Tools» Recall Waveform and choosing a.wdf file from the Recall Stored Waveform dialog. The waveform will be recalled and loaded into the list of possible source simulation data waveforms for the active chart. Creating new charts You can create new charts that are added to the current.sdf file. 1. Select Chart» New Chart. The Create New Chart dialog displays. 2. Define a name and title for the chart and also the title and units for the X-axis. You can also specify whether or not complex data can be displayed in the chart. 3. Click OK and a new blank chart will appear in the Waveform Analysis window, added as a tab after the last chart in the document

219 Signal Integrity tutorial Creating a FFT chart Performing a Fast Fourier Transform (FFT) on the active chart displays the results in a new chart. 1. Select the chart you wish to perform a Fast Fourier Transform on by clicking on the required analysis tab at the bottom of the Waveform Analysis window. 2. Select Chart» Create FFT Chart. The FFT will be performed and the results displayed in a new chart which is added as a new tab (<netname>_fft) and made the active chart in the window. Creating new plots You can add new plots to existing or new charts using the Plot Wizard.. 1. Select Plot» New Plot. The first page of the Plot Wizard displays. Give the new plot a name and click Next. 2. Set up the appearance of the plot and click Next. 3. Select the waveforms to plot by clicking on the Add button in the Add Wave to Plot dialog, select the waveform (or add an expression) and click Create. 4. Click Next to continue and click Finish to exit the wizard. The new plot displays in the Waveform Analysis window

220 Signal Integrity tutorial Using the SimData panel The SimData panel enables you to add waveforms from the available source data to the active wave plot and obtain measurement information based on the selected waveform and measurements calculated using the measurement cursors. The Waveform section at the top of the panel contains a list of all available source data signal waveforms for the simulation that you have performed. This is the same list that appears in the Source Data dialog (Chart» Source Data). Click on Source Data to open this dialog. Adding a waveform to a plot from the SimData panel Click on the Add Wave to Plot button in the Sim Data panel to add the selected waveforms to the currently selected plot in the Waveform Analysis window. Measurement cursors The Measurement Cursors section of the panel reflects the current and calculated measurements when using one or both of the measurement cursors. 1. The two measurement cursors (A and B) are available by right-clicking on a selected waveform s name in the Waveform Analysis window. Drag the cursors by their tabs to the location required. 2. For both cursors, the name of the waveform the cursor is currently assigned to is shown, as well as X and Y axis data values, dependent on the cursor's position along the waveform. 3. The calculated X and Y values appear in the Measurement Cursors section of the SimData panel. Waveform measurements The Waveform Measurements section of the dialog shows various general measurements for the waveform selected in the Waveform Analysis window, such as Rise and Fall times. After analyzing your results Once you have analyzed your results, you can experiment, for example, with various terminations to bring down any ringing on the selected nets. You may also need to make changes to your circuit or PCB and rerun your Signal Integrity analyses until the desired results are reached

221 Getting Started with FPGA tutorial 13 Getting started with FPGA Getting started with FPGA Creating an FPGA Project Setting the project options Creating a Schematic source document Setting up sheet options Before you start designing Locating the library and components Placing parts on the schematic Interfacing your design using ports Creating connections Naming the connections Using Buses Configuring your design Generating an EDIF-FPGA netlist Back-annotating your FPGA project Back-annotating your PCB project Getting started with FPGA This tutorial is designed to give you an overview of how to create an FPGA design using DXP. It will outline how to create a schematic and generate an EDIF-FPGA netlist that can be used with the third party vendor place and route tools. It also briefly covers concepts such as projects, digital schematic design, FPGA library support and back-annotating. The example used in this tutorial is a Johnson s counter, shown below. It can be found in the folder Altium\Examples\FPGA\Xilinx\Johnson Counter in your DXP installation directory. Refer to this example at any time to get further insight or skip some of the steps. It is important to note that schematic concepts for digital designs under DXP can be different to PCB design concepts. A rule that needs to be explicitly followed when designing FPGAs may not be true for PCB. 13-1

222 Getting Started with FPGA tutorial Creating an FPGA Project To start working in DXP, you first need a project. A project makes managing your source design documents and any generated outputs much easier. For digital FPGA designs, we need to create an FPGA project. To start the tutorial, create a new FPGA project: 1. Click on Create a new FPGA Design Project in the Pick a Task section of the design window. Although not necessary, it is useful not to use spaces or any illegal character in FPGA designs to avoid any possible difficulties when using external third party tools. DXP however does support all Windows legal names. Alternatively, select File» New» FPGA Project from the menus, or you could click on Blank Project (FPGA) in the New section of the Files panel. If this panel is not displayed, click on the Files tab. 2. The Projects panel displays. The new project file, FPGA Project1.PrjFpg, is listed here with no documents added. 13-2

223 Getting Started with FPGA tutorial 3. Rename the new project file (with a.prjfpg extension) by selecting File» Save Project As. Navigate to where you want to save the project on your hard disk, type the name Johnson Counter.PrjFpg in the File Name field and click on Save. As most FPGA projects involve the use of third party vendor Place and Route tools at some stage, it is often worthwhile to choose a path that conforms to their standards to avoid any unforeseen problems when running their tools. DXP supports Windows filenames, but spaces or non-alphanumeric characters are still not supported by many vendors. If you are getting unnecessary warning or error messages in your design, especially regarding buses which often are quite flexible in digital designs, it is often useful to turn them off using Project Options. Setting the project options A project in DXP has a set of options associated with it. You can set the options for Error Reporting, the Connection Matrix, Comparator, ECO Generation, General Options and Parameters. Once set, DXP remembers the generic options for the next FPGA project created. For digital designs, ports and sheet entries generally should not name the nets. For readability, uncheck Allow Ports to Name Nets and Allow Sheet Entries to Name Nets in the Options tab. 1. Display the project options by right-clicking on Johnson Counter.PrjFpg in the Projects panel and selecting Project Options. Alternatively, select Project» Project Options from the menus. The Options for Project [Johnson Counter.PrjFpg] dialog displays. 13-3

224 Getting Started with FPGA tutorial 2. Change the Nets with multiple names violation in the Violations Associated with Nets section of the Error Reporting tab from a warning to No Report, so the design compiler will not complain that ports are named differently to the nets they are attached to a feature normally desired for PCB schematic designs. However, this also means that we will not receive any errors where different net labels are attached to the same wire. The Connection Matrix tab is also very useful in digital designs to ensure that all the pins, ports and sheet entries in your designs do not have any mode conflicts. 3. In the Options tab of the Options for Project dialog, you can also specify the output directory for all your project output files. By default, all FPGA projects have an output directory already set, named ProjectOutputs. You may change this if you wish. 4. Once you are finished setting the options, click OK. Next, we will create a schematic for the design of the Johnson Counter to add to our project file. Creating a Schematic source document An FPGA project supports two types of source documents, schematic and VHDL. It can support both types of documents in a project, however, in the case of VHDL, it will only make use of structural VHDL. You can mix both types of documents in a project with the use of sheet symbols. We only need a single schematic for the Johnson Counter, so create it by completing the following steps: 1. Select File» New» Schematic, or click on Schematic Sheet in the New section of the Files panel. A blank schematic sheet named Sheet1.SchDoc displays in the design window. You can mix VHDL and Schematic documents with the use of sheet symbols. In the case of VHDL, the sheet entries correspond to the ports of the VHDL document. 13-4

225 Getting Started with FPGA tutorial 2. Rename the new schematic file (with a.schdoc extension) by selecting File» Save As. Navigate to where you wish to store the schematic on your hard disk, type the name Johnson Counter.SchDoc in the File Name field and click on Save. Setting up sheet options It is often a good idea to immediately set up the sheet options for the new document if the defaults do not suit the project. 1. Select Design» Options and the Document Options dialog displays. We will only change the sheet style to standard A4 format. In the Sheet Options tab, select A4 style from the Standard Styles drop-down list. 2. Click OK to close the dialog and update the schematic sheet. Before you start designing You are now ready to begin drawing the schematic. However, before you do, you have a very important decision to make. Which vendor do you want to use? This is important because, in general, FPGA designs are not very portable. Each vendor has their own unique set of primitive components that are generally not compatible with one another. Furthermore, some vendors have many different 13-5

226 Getting Started with FPGA tutorial architecture sets with different set of components for each of them, so changing your mind on the architecture for a vendor can also be costly. DXP provides the schematic symbols for the primitive components of all the major vendors. After deciding what the vendor and architecture of your FPGA will be, you can only use the matching integrated library provided by Altium. If you change your mind, you will need to re-place all the components from the library you used with the library of the new vendor-architecture you have chosen. For our Johnson Counter, we shall use a Xilinx Spartan II chip the XC2S200- PQ Locating the library and components As we have chosen a Xilinx Spartan II chip, we need to locate the Xilinx Spartan II primitive library to begin working on our design. 1. Click on the Libraries tab to display the Libraries panel. Alternatively, select View» Workspace Panels» Libraries from the menus. 2. To locate and install the library we want, click on the Libraries button in the Libraries panel. The Add Remove Libraries dialog displays listing all the libraries that are currently installed. 3. Remove any currently installed libraries from the list so that a component is not accidentally placed from the wrong library. Double-click on each of the libraries to remove them, or you can select them (using Shift+click) and click on Remove. 4. Click on Add Library. The Open dialog displays. Navigate to the Altium\Library folder in your DXP installation. Open the Xilinx folder and select Xilinx Spartan-II & Spartan-IIE FPGA.IntLib. Click Open. The library is added to the Ordered List of Installed Libraries. 5. Click Close to close the Add Remove Libraries dialog. The Xilinx Spartan-II & Spartan-IIE FPGA.IntLib displays in the Libraries panel. All Xilinx primitives look the same. DXP allows you to change architectures under Xilinx without having to re-place all your components provided all the primitive components you used in your design are present either as primitives or macros in both architectures. All libraries supplied by DXP intended for use in FPGA design projects end with an FPGA. So a good filter string to use is *FPGA.INTLIB to clearly distinguish these libraries from the PCB libraries. FPGA primitive libraries that come with DXP have no models associated with them. However, DXP supports the use of EDIF models and will also support VHDL synthesis and simulation models. Placing parts on the schematic Now, let s start designing the schematic for our Johnson Counter. 1. Find the component SR4CLED in the Libraries panel. You can browse the Libraries panel by either navigating through the list or typing the name SR4CLED in the Masks edit box below the library name. Select the component in the list and click the Place SR4CLED button. 13-6

227 Getting Started with FPGA tutorial DXP can automatically annotate your components during placement. If you press TAB in the process of placing a component and change the designator field to something ending with a number, the next component you place while in the same mode would have its designator automatically incremented. 2. You should notice that your cursor now has the component attached to it. Move the cursor into the schematic workspace if you don t see it. Place the component by clicking on the appropriate position on the schematic. 3. We also need to use five inverters (INV), 1 OR gate (OR2B2), 1 ground (GND) and two flip flops (FJKC) in our design. Repeat the above steps for these components and place them as shown below. 13-7

228 Getting Started with FPGA tutorial Interfacing your design using ports Now we need to add in our ports; this is generally done after wiring but for tutorial purposes, we will do it before. Each schematic document in essence is an entity, or component, and the ports define the pins of this component. However, for the top-level schematic, ports have an extra meaning as, most often than not, they get mapped directly to the pins of your actual chip. As we only have one schematic in our design, it is the top level schematic, so ports play an important part in interfacing our design to the third party place and route tools. Power Ports have no meaning in FPGA designs. Do not confuse GND and VCC power ports with GND and VCC primitive components! This Johnson counter uses five input ports and four outputs ports. The input ports are Left, Right, Stop, Load and Clk, and the output ports are Q0, Q1, Q2 and Q3. 1. To place the input ports, select Place» Port [shortcut P, R]. The cursor changes to the outline of a port. Press TAB to set the port s properties in the Port Properties dialog. Type in Left in the Name field and select Input for the I/O Type. If you want to change the port symbol s shape, change the Style to Right and click OK. These settings will remain for other ports that are placed. 2. Click to position one end of the port. Drag the mouse to set the port length and click to finish. Vendors such as Xilinx require pads to be used instead of ports in your top level design document. However, DXP will automatically generate and insert these pads for you when you generate an EDIF- FPGA netlist. So the use of ports is recommended for your top level schematic. 3. Repeat Steps 1 and 2 for all the other input ports, placed to the left of the components as shown below. 4. We have a choice here for the Q0, Q1, Q2, Q3 output ports. We can either place them as four separate ports or use a single bus port. Let s do it using a bus port, so place a port on the schematic to the right of all the components. Set its I/O Type to Output, and its Style to Right. In the Name field, type in Q[3..0] and click OK. Click to place the port. 5. Right-click or press ESC to exit port placement mode. Remember to always ensure that your ports always have an I/O Type properly set. How the port looks is just for visual reference and has no bearing on its I/O type. Note that you can just place your ports and use the List panel to quickly filter out the ports using the IsPort query. You can adjust all the properties of your ports from here without going through the tedious process of opening and closing dialogs. 13-8

229 Getting Started with FPGA tutorial Creating connections We have placed all the components and ports, so now it s time to wire them all together. There are two ways to wire your schematic, explicitly or implicitly. Explicit wiring creates a connection by having a physical wire connecting your two net objects together. Implicit wiring creates a connection from the use of wires and net labels; no physical connection is required. Instead, connection is implied if two disjoint wires share the same net label. Our design will need both wires and buses, let s do the wires first. 1. To place a wire, select Place» Wire [shortcut P, W] and click on the point on the schematic where you want to start placing (usually at a port or a component pin). Move the cursor to the next point you want your wire segment to connect to and click again. Continue until you have made a connection Remember not to confuse wires with lines! Wires are for connecting, lines are for drawing. to another port or component pin. Right-click to finish placing the wire. Right-click, or press ESC, to exit wire placement mode. 2. Wire up the schematic as shown below, taking careful note of the junctions where wires cross in this schematic. If two wires cross and a junction is present, a connection between these two wires is implied. If there is no Schematic infers buses by names. If a net label ends with a number it groups all such net labels together to form an inferred bus for digital designs. This does not apply to ports where such grouping is not desirable. Ensure your connection is valid by attaching your wires properly to other wires, component pins and ports. During wire or bus placement mode if the cursor turns to a red crosshair over the object you want to connect to then there is valid connection if you place a node of the wire there. 13-9

230 Getting Started with FPGA tutorial junction, there is no connection. In this schematic, auto junctions will occur where wires connect. Naming the connections All the wiring done above is explicit and therefore, technically, no net labels are required. However, it is always a good idea to net label all your connections as it will make your design easier to understand and makes tracking down problems and referencing easier. To net label your connections: 1. Select Place» Net Label [shortcut P, N]. A dotted box will appear floating on the cursor. 2. To edit the net label before it is placed, press the TAB key to display the Net Label dialog. Type the net name in the Net field and click OK. 3. Place the net label so that the bottom left of the net label (its hotspot ) touches the wire you want to label. The cursor will change to a red cross when the net label touches the wire. Net labels become signals in VHDL so it is often a good idea to name them according to the VHDL standard. You can then use the VHDL net list of your design to debug it using VHDL later. 4. Label the other nets. The diagram below gives an indication where the net labels should be placed. They need not be named exactly as shown, as long as they are unique. Right-click or press ESC to exit net label placement mode

231 Getting Started with FPGA tutorial We have almost completed our design but we still have not connected our bus output port Q[3..0]. Using Buses DXP supports very complex use of buses. While buses are just a collection of signals in the PCB world, they represent much more in the digital world. Buses can be used to specify not just a group of signals but how each signal in the bus is mapped to its endpoints. DXP supports powerful features like splitting a bus into various different segments, reversing bus connections and having some of its elements unconnected for its VHDL and EDIF-FPGA generation. This will not be covered in the tutorial but it is all done by the use of net labels and implicit wiring. When using buses, it is important to remember that you always need to net label any disjoint bus segment. It is also useful to note that a connection from a bus to another object is always resolved from left to right and the bus size of both objects in a connection must be the same. To connect the bus port Q[3..0] to our design: 1. Place a bus by selecting Place» Bus [shortcut P, B] and place the bus, as shown below, using the same placement technique used when placing a wire. A very common mistake is to use a bus style net label (i.e. [ ] ) on a wire. This will not work in DXP, as only buses may have bus style net labels placed on them. Always, net label your buses. A bus without a net label even when it is explicitly connected is very ambiguous because there is no net label to clearly specify how each element of the bus is connected to its endpoints

232 Getting Started with FPGA tutorial 2. Place a net label called SQ[3..0] on the bus. This implies that SQ[3] is connected to Q[3], etc. 3. Although this is optional, select Place» Bus Entry [shortcut P, U] and place the bus entries as shown. Use the Spacebar key while placing to rotate the bus entry. When mapping a bus connection, the range of a bus is read from left to right. Bus entry objects are purely visual; they are not used when determining whether a wire connects to a bus in digital designs. Configuring your design We have finished designing our Johnson counter and at this point, we could generate our EDIF-FPGA netlist and continue the design process using the Xilinx Place and Route tools. However, there still are a few parameters we need to configure in our design. This configuration can be done at a later stage but it is useful to attach these attributes to the source design for reference. The following steps are a general guide to setting up design parameters; refer to the Attributes for FPGA tutorial to learn more about placing attributes and what attributes are supported by DXP Using parameters, you can attach anything you like to any digital object. These parameters will be passed on as attributes to any VHDL or EDIF-FPGA netlist generated. External tools sometimes make use of these attributes. First, we need to specify what chip we want to use in our design. As we initially targeted our design to the Xilinx Spartan II architecture, we will use the XC2S200-5PQ208 chip. For parameters like 1. PART_NAME, PINNUM, Add a parameter to the sheet by selecting Design» Options and clicking on etc, you might want to the Parameters tab of the Document Options dialog. Click on Add to create a refer to your vendor new parameter called PART_NAME with a value of 2S200-PQ208-5 and a type of String. Alternatively, you can add this parameter in the Parameters tab of documentation to find what values are valid. For example, Xilinx the Options for Project dialog (Project» Project Options). generally number their 2. DXP will output this parameter in a format that third party vendors can recognize. pins starting with the prefix P. Once we have specified the chip, we can also fix the actual pin numbers the ports in our design are connected to. This in effect will lock the pin number assignments in the third party vendor tools (where supported). Alternatively, you can choose not to do this step and let the third party vendor

233 Getting Started with FPGA tutorial tools assign the pins for you and back-annotate your FPGA design with these assignments. This is covered briefly in a later se ction. To assign a vendor pin assignment, you need to add the PINNUM parameter to the necessary ports. Pa rameters are a dde d by clicking on Add in the Parameters tab of the Port Properties dialog. 1. Add a parameter called PIN NUM with a value of P3 with a type of String on port Left. The pin assignment for port Right is P4, Stop is P5, Load is P6 and Clk is P77. Note that P77 is a special dedicated clock input pin. 2. To add the PINNUM parameter to a bus port, use a comma to separate the pin numbers; assignments are resolved in a left to right fashion. Add the PINNUM parameter with a value of P15, P16, P17, P18 to port Q[3..0]. Since we have a clock input that is connected to every co mponent in our design, we can let Xilinx optimize this signal by treating this sign al as a global fast clock. This saves us from computing the value of the clock and using up macrocells of the FPGA. 3. Add a parameter called XILINX_BUFG to the port Clk. We have now finished configuring what we can from the schematic, so let s generate our EDIF-FPGA netlist to take it to the Place and Route tools. Generating an EDIF-FPGA netlist Most third party place and route tools support EDIF. However, the EDIF standard can vary from one vendor tool to another. Chances are EDIF accepted by one vendor tool may not be accepted by another. Each vendor also has particular parameters it recognizes and its own way of configuring them. Some vendors also require special components be placed in your design to properly interface it with its tools. In our example, Xilinx requires the top-level document to be interfaced using pads and buffers. The EDIF for FPGA netlister provided with DXP generates EDIF that can be accepted by the third party vendor tools as well as inserting any necessary logic required. You can use the EDIF- FPGA netlister to generate an EDIF model. Just don t check the Insert IO Buffer option as a model is usually never the top level entity. To generate an EDIF-FPGA netlist: 1. Select Design» Netlist for Project» EDIF for FPGA. The EDIF Netlist Properties dialog displays. 2. Select Xilinx Spartan 2 Series from the Vendor Family drop-down list. Ensure Insert IO Buffers is checked. This option changes the top-level entity s ports into pads with the appropriate buffering. Click OK to continue. Even though we placed components from the Xilinx Spartan II FPGA library, the components we used are als o valid for other Xilinx architectures. 3. You will notice in the Projects panel there is a new folder called Generated EDIF Documents with the file Johnson Counter.EDN. The file name extension is EDN, which Xilinx recognizes as EDIF files. This file is stored in the Projects Output folder that you specified earlier

234 Getting Started with FPGA tutorial 4. You should also view the Messages panel to ensure that the generation was successful and view any errors or warnings. Click on the Messages tab, or select View» Workspace Panels» Messages, to display the Messages panel. Remember you can always double-click on any message to see whether you can obtain more information. You should notice the message Copied EDIF macro... in the Messages panel. The components FJKC and SR4CLED are macros in the Xilinx Spartan II architecture. This means these components are not primitives and Xilinx will not recognize them. DXP contains all the EDIF-FPGA macro implementations for these components and copies them out to your ProjectOutputs folder so that the Xilinx tools can read and recognize them. If any EDIF models were attached to your component, these would also be copied to the ProjectOutputs folder. To view the EDIF macros for all Xilinx architectures, look in the folder Altium\Library\EDIF\Xilinx\ in your DXP installation directory. Back-annotating your FPGA project After you have placed your design through the place and route tools, you can also back-annotate the top schematic with any changed PINNUM information. As we earlier locked our pin assignments by specifying the PINNUM parameter, this should not occur. However, for the sake of demonstrating, let us say we decided to change the pin numbers of our design because we made a bad selection or wanted to use the other end of the chip. 1. Make sure you have the top-level schematic sheet open and select Tools» Import FPGA Pin-Data to Sheet. The Open FPGA Vendor PIN File dialog displays. 2. Select Xilinx UCF, Report files (*.ucf, *.pad) file as the filter from the Files of Type drop-down list, browse for the required file and click Open. This tool will prompt you when it wants to delete an invalid PINNUM parameter and it will modify any existing PINNUM parameter to its new value and add any new ones. Check the Messages panel to review what exactly was changed. Back-annotating your PCB project FPGA Schematic PCB components can get quite large and it can often be a long process to rename all the pins to match your FPGA design. Back-annotation of your PCB project is simplified in DXP by allowing you to back-annotate a part using a vendor report file. To quickly demonstrate this feature, complete the following steps: 1. Create a new PCB project called Johnson Counter.PrjPcb in a separate folder. 2. Create a new schematic sheet called LED Counter.SchDoc. 3. Add the library Xilinx Spartan-II.Intlib in the Libraries panel by selecting Design» Add/Remove Library. Click on Add Library and navigate to \Altium\Library\Xilinx

235 Getting Started with FPGA tutorial 4. From the Libraries panel, find and place the component XC2S200-5PQ208C on the schematic sheet. 5. Select Tools» Import FPGA Pin-Data to Part. When the cross hair displays, click on the component XC2S200-5PQ208C. The Open FPGA Vendor PIN File dialog displays. Select Xilinx UCF, Report files (*.ucf, *.pad) file as the filter from the Files of Type drop-down list, browse for the required file and click Open. Notice that all the pin names have changed in accordance with what was specified in the vendor file report. In some cases, the pin electrical type is also changed to reflect what the report states. This will help to obtain a clean Electrical Rules Check (ERC)

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237 VHDL & schematic capture tutorial 14 VHDL & schematic capture Multi-dimensional capture in DXP Create a new FPGA project Adding VHDL documents to the project Creating a new VHDL document Create a VHDL top level schematic Generating sheet symbols from VHDL files Placing components Placing ports on the schematic Making connections Adding buses Adding net labels Adding a VHDL testbench file Creating a new VHDL testbench document Adding VHDL models Creating a new VHDL model document Using VHDL Libraries Creating a new VHDL library document Setting up the project Compiling your design Smart compiling your design Simulating your design Debugging mode Setting breakpoints Running the simulation Adding Watches Multi-dimensional capture in DXP This tutorial shows how to create and simulate a mixed schematic and VHDL design using DXP. This tutorial presumes you have knowledge of generating VHDL code and testbench files. We will look at creating a new FPGA project, adding in the source VHDL, schematic and testbench documents required; using VHDL models and VHDL libraries and then running VHDL simulation and viewing the results in the Waveform Viewer. The example used in this tutorial is located in the \Altium\Examples\FPGA\BCD Counter folder. 14-1

238 VHDL & schematic capture tutorial Create a new FPGA project To start the tutorial, create a new FPGA project: 1. Click on Create a new FPGA Design Project in the Pick a Task section of the design window. Alternatively, select File» New» FPGA Project from the menus, or you could click on Blank Project (FPGA) in the New section of the Files panel. If this panel is not displayed, click on the Files tab. 2. The Projects panel displays. The new project file, FPGA Project1.PrjFpg, is listed here with no documents added. 3. Rename the new project file (with a.prjfpg extension) by selecting File» Save Project As. Navigate to where you want to save the project on your hard disk, type the name BCD.PrjFpg in the File Name field and click on Save. Adding VHDL documents to the project For this tutorial, we can add in the file \Altium\Examples\FPGA\BCD Counter\BCD.VHD which includes the VHDL code for a 4 bit BCD counter. 1. Add the VHDL file to the FPGA project by right-clicking over the project name in the Projects panel and selecting Add to Project. Navigate to the file and click Open. 2. The VHDL document is added to the project and listed under VHDL Documents in the Projects panel. Click on the file name to view or edit this file in the Text Editor. 3. Save the project (File» Save). Creating a new VHDL document If you need to create a new VHDL document to add to the project: 1. Select File» New» VHDL Document. A new VHDL document, VHDL1.Vhd, is added to the FPGA project under the folder name VHDL Documents in the Projects panel. The Text Editor opens ready for your input with the language option already set to VHDL. 2. Enter the code required and save the VHDL file (File» Save As) with a.vhd extension. To use non-synthesizable code in your VHDL you can encapsulate such code between the pragma s -- rtl_synthesis off -- rtl_synthesis on You can also use -- synopsys translate_off -- synopsys translate_on 3. Save the project (File» Save). Next, we will create a schematic for the design of the BCD Counter to add to our project file. 14-2

239 VHDL & schematic capture tutorial Create a VHDL top level schematic An FPGA project supports two types of source documents, schematic and VHDL. It can support both types of documents in a project, however, in the case of VHDL, it will only make use of structural VHDL. You can mix both types of documents in a project through the use of sheet symbols. We only need to create a single schematic for the BCD Counter, so we will use the schematic, BCD8.SchDoc, as our example. 1. Select File» New» Schematic, or click on Schematic Sheet in the New section of the Files panel. A blank schematic sheet named Sheet1.SchDoc displays in the design window. 2. Rename the new schematic file (with a.schdoc extension) by selecting File» Save As. Navigate to where you wish to store the schematic on your hard disk, type the name, e.g. BCD8.SchDoc, in the File Name field and click on Save. 3. Choose a template for schematic by selecting Design» Template» Select Template File Name. Navigate to a schematic template, e.g. A4.SchDot, located in the \Altium\Templates folder and click Open. Click OK until the template is set and save the schematic document. 14-3

240 VHDL & schematic capture tutorial Generating sheet symbols from VHDL files You can mix VHDL and schematic documents with the use of sheet symbols. In the case of VHDL, the sheet entries generated on the sheet symbol correspond to the ports of the VHDL document. 1. With the new schematic document displayed in the design window, select Design» Create Symbol From Sheet to generate a sheet symbol from a document. In this example, we will generate a sheet symbol named H1 for the entity BCD in the VHDL document BCD.VHD. 2. The Choose Document to Place dialog displays. Select the VHDL document BCD.VHD and click OK. 3. If the chosen VHDL document contains more than one entity, the Choose VHDL Entity dialog displays. In our case only one VHDL entity is present in the document so this dialog is not displayed. The sheet symbol appears floating on the cursor. The VHDLEntity parameter always needs to be present on a sheet symbol to properly link to the source entity inside a VHDL file. This is because a VHDL file can contain multiple entities. 4. Before placing the sheet symbol on the schematic sheet, press the TAB key to set up the properties of this sheet symbol, e.g. set the Designator to H1. Click on the Parameters tab to check the VHDLENTITY parameter that has been automatically generated and add any other parameters you might require, e.g. a description. 14-4

241 VHDL & schematic capture tutorial 5. Place the sheet symbol on the schematic. Modify the position of the sheet entries and text as required so the sheet symbol looks similar to the one below. Sheet symbols should be used when the target file is considered a source document of your design. Models and Library files should be used when the target VHDL file is considered to be a library document of your design. 6. Repeat steps 1 to 5 for the second instance of the BCD Counter and assign its designator to H2. Save the schematic. Placing components You can also use schematic symbols in your design. However, in doing so, you must have the simulation behavior described in VHDL for these components in a model file or VHDL library document. We will demonstrate the use of both in this example, but first we must place the components down. A schematic library, which contains the components we wish to use in our design, is included with this example located in \Altium\Examples\FPGA\BCD Counter\SCH Library\BCD.SchLib 14-5

242 VHDL & schematic capture tutorial 1. A schematic library is included with this example. Right-click on BCD.PrjFpg in the Projects panel and select Add To Project and select BCD.SCHLIB and click Open. 2. We need to place two components. Select Place» Part [shortcut P, P] to bring up the Place Part dialog, type BUFGS in the Lib Ref field, and place the buffer component as shown. Also type in PARITYC in the Lib Ref field and place the parity component as shown in the schematic. Placing ports on the schematic To place an input port, e.g. the Clock input port: Integrated libraries support VHDL models either as one large file containing all the models or separate files each containing one entity. 1. Select Place» Port [shortcut P, R]. The cursor changes to the outline of a port. Press TAB to set the port s properties in the Port Properties dialog. Type in Clock in the Name field and select Input for the I/O Type. If you want to change the port symbol s shape, change the Style to Right and click OK. These settings will remain for other ports that are placed. 2. Click to position one end of the port. Drag the mouse to set the port length and click to finish. 3. Repeat Steps 1 and 2 for the other input ports. 4. Create a single bus port for Lower[3..0]. Place a port on the schematic and set its I/O Type to Output and its Style to Left. In the Name field, type in LOWER[3..0] and click OK. Click to place the port. 5. Right-click or press ESC to exit port placement mode. Making connections Now you can wire up your schematic. 14-6

243 VHDL & schematic capture tutorial 1. To place a wire, select Place» Wire [shortcut P, W] and click on the point on the schematic where you want to start placing (usually at a port or a component pin). Move the cursor to the next point you want your wire segment to connect to and click again. Continue until you have made a connection to another port or component pin. Right-click to finish placing the wire. Right-click, or press ESC, to exit wire placement mode. 2. Wire up the schematic as shown in the file BCD8.SchDoc, taking careful note of the junctions where wires cross in this schematic. If two wires cross and a junction is present, a connection between these two wires is implied. If there is no junction, there is no connection. In this schematic, auto junctions will occur where wires connect. Adding buses A connection from a bus to another object is always resolved from left to right and the bus size of both objects in a connection must be the same. To connect the bus port LOWER[3..0] to our design: 1. Place a bus by selecting Place» Bus [shortcut P, B]. A bus should always have a net label in DXP to always ensure proper connectivity. 2. Using the same placement technique used when placing a wire, place the bus between the bus port LOWER[3..0] and the OCD[3..0] sheet entry. Adding net labels It is a good idea to always net label connections to make it easier to debug in the future. Otherwise, DXP will create net labels for you. In this example, we only need to place the net label for net LRCO. 1. Select Place» Net Label [shortcut P, N]. A dotted box will appear floating on the cursor. 2. To edit the net label before it is placed, press the TAB key to display the Net Label dialog. Type the net name in the Net field, e.g. LRCO, and click OK. 3. Place the net label so that the bottom left of the net label (its hotspot ) touches the wire you want to label. The cursor will change to a red cross when the net label touches the wire. Click to place. 4. Right-click or press ESC to exit net label placement mode. 5. Save the schematic by selecting File» Save. You can quickly declare and instantiate a component in a VHDL file in another sheet by using Design» Declare Component at Cursor, and Design» Instantiate Component at Cursor. Adding a VHDL testbench file Testbench files are VHDL source files that describe the sequence of tests to be run on your design. Testbench files are not considered to be part of the core design and thus are not included in the design hierarchy or any netlist. Testbenches should be the top-level of a design being simulated. For this tutorial, we can add in the testbench file \Altium\Examples\FPGA\BCD Counter\BCD.VHDTST which includes the testbench code for this project. 14-7

244 VHDL & schematic capture tutorial 1. Add the VHDL file to the FPGA project by right-clicking over the project name in the Projects panel and selecting Add to Project. Navigate to the file and click Open. 2. The VHDL testbench document is added to the project and listed under VHDL Testbenches in the Projects panel. Click on the file name to view or edit this file in the Text Editor. 3. Save the project (File» Save). Creating a new VHDL testbench document If you need to create a new VHDL testbench document to add to the project: 1. From the files panel select Other Document» VHDL Testbench. 2. Save the file as <name>.vhdtst, e.g. BCD.VHDTST. The file will be listed under VHDL Testbenches folder in the Projects panel. 3. Open testbench file, enter your testbench code and save the file. Adding VHDL models We have almost completed our design but we have two components left that do not have any simulation behavioral code attached to them. We shall make use of a model for the BUFGS component. For this tutorial, we can add in the VHDL model file \Altium\Examples\FPGA\BCD Counter\VHDL Models\BUFGS.VHDMDL which includes the VHDL behavioral code for the BUFGS component. 1. Add the VHDL file to the FPGA project by right-clicking over the project name in the Projects panel and selecting Add to Project. Navigate to the file and click Open. 2. The VHDL model document is added to the project and listed under VHDL Model Libraries in the Projects panel. Click on the file name to view or edit this file in the Text Editor. 3. Save the project using File» Save. Creating a new VHDL model document If you need to create a new VHDL model document to add to the project: 1. From the Files panel, select Other Document» VHDL Testbench. 2. Save the file as <name>.vhdmdl, e.g. BUFGS.VHDMDL. The file will be listed under VHDL Model Libraries folder in the Projects panel. 3. Open the VHDL model file, enter the entity and architecture code for your component and save the file. We now need to attach this VHDL model to the BUFGS component. The simulator will automatically detect such models on components and include them in the compilation process. To do this: 14-8

245 VHDL & schematic capture tutorial 1. Double-click on the BUFGS component on the schematic to display the Component Properties dialog. 2. Click the Add button on the bottom right in the Models section to bring up the Add New Model dialog. Select VHDL and click OK to bring up the VHDL Model Properties dialog. 3. The name of the model has to be the same as the name of the entity in the VHDL Model file, so type in BUFGS. As this component did not originate from an integrated library, the From integrated library radio button should be grayed out. As we have already added the model file to the FPGA project, we do not need to specify its location. Alternatively, you could enter the full path or set up your search paths in the Search Paths tab of the Options for Project dialog (Project» Project Options) using this directory: Altium\Examples\FPGA\BCD Counter\VHDL Models\. 4. In the Description field, type BUFGS. This particular model can be used for both simulation and synthesis, so ensure that the Simulation/Synthesis box shows Simulation and Synthesis. Click OK to close the dialog. Using VHDL Libraries For the PARITY component, we shall make use of a VHDL library. A VHDL library is a collection of VHDL documents containing various components, packages, types and constants, etc. These files are all mapped to a single logical name that is equal to the name of the VHDL library file. By using the Library and Use statements in the VHDL code, you can make use of all the constructs exported in all the VHDL files in this library. The simulator compiles all VHDL libraries first, followed by any model files and finally the source documents of the project. For this tutorial, we can add in the VHDL Library file \Altium\Examples\FPGA\BCD Counter\VHDL Library\BCD_LIB.VHDLIB which exports the VHDL behavioral code for the Parity component. 1. Add the VHDL Library to the FPGA project by right-clicking over the project name in the Projects panel and selecting Add to Project. Navigate to the file and click Open. 2. The VHDL library document is added to the project and listed under VHDL Library Files in the Projects panel. Click on the file name to view or edit this file in the Text Editor. 3. Save the project (File» Save). Creating a new VHDL library document If you need to create a new VHDL library document to add to the project: 1. From the Files panel, select Other Document» VHDL Library. The keywords to place VHDL code inside a schematic are.vhdl_entity_header.vhdl_entity_generic.vhdl_entity_declaration.vhdl_entity_statement.vhdl_arch_header.vhdl_arch_declaration.vhdl_statement 14-9

246 VHDL & schematic capture tutorial 2. Save the file as <name>.vhdlib, e.g. BCD_LIB.VHDLIB. The file will be listed under VHDL Libraries folder in the Projects panel. 3. Select VHDL» Edit Library to open up the Edit VHDL Library dialog where you can add documents to your library. Whether you created a new VHDL library, or used the existing one, do the following: 1. Ensure the BCD_LIB.VHDLIB document is open and select VHDL» Edit Library. The Edit VHDL Library dialog will appear. You ll notice two files in this library, PARITY.VHD and UTILITY.VHD. The first file contains the entity declaration for the Parity component, while the second file contains a package called Utility which contains a parity function. The compile order for this library follows a bottom-up order, so UTILITY.VHD is compiled before PARITY.VHD. 2. Ensure the files are in the proper order as shown and click OK. 3. Select VHDL» Edit Library to open up the Edit VHDL Library dialog where you can add documents to your library. We have added the BCD.VHDLIB library document to our project but we still need to properly reference it in our design. For a VHDL file you can make use of the Library and Uses statements to do this. However as we are using the components in a schematic we need to do the following: 1. Ensure the BCD8.SchDoc document is open and select Place» Text Frame. Go to the bottom left of the schematic and place the text frame there. Double-click on it to display the Text Frame dialog and click the Change button next to Text to bring up the TextFrame Text dialog. 2. You can use special headers to insert VHDL code into your schematic. In this case, because we want to insert the library statement, we shall use.vhdl_entity_header. Type in the text as shown and click OK

247 VHDL & schematic capture tutorial Setting up the project Now that we have the top level schematic and VHDL files added to the project, we need to set up the options for the project. 1. Open any VHDL or schematic file added to the FPGA project, e.g. BCD.VHD. 2. Select Design» FPGA Options to make a configuration. The VHDL Project Options dialog displays. 3. The Design Documents tab contains the list of source documents in the project. The documents are compiled from bottom to top, so in this case, the BCD.VHD file is compiled first, then the schematic and finally the testbench file. You can use drag and drop or use Compile Sooner and Compile Later (accessed by clicking on the Menu button) to position the selected document in the correct order, as shown above. The numbers next to the documents in the Projects panel reflect this ordering if you have selected them to be displayed. 4. The VHDL Project Libraries tab contains the list of VHDL libraries in the project. In this example there is only one library but the libraries get built from bottom up, so the last library on the list gets compiled first while the You can set the Projects panel to display the files in the compile order by selecting DXP» System Preferences, clicking on the Projects Panel tab and selecting Project Order in the Sort By section. first library on the list gets compiled last. Click on the Menu or right-click on a library to view more commands you can use with libraries. 5. Click on the Simulation tab and type an entity name into Top Level Entity Configuration field. In this example, the top level entity is TestBCD, as defined in the testbench file BCD.VHDTST

248 VHDL & schematic capture tutorial Compiling your design Now we are ready to compile our design. First all the library files are compiled, then all the model files and finally the source files in your design. Any schematic file is converted to VHDL and its corresponding VHDL file is compiled by the simulator. 1. With any source document of the project open select Simulator» Compile. In the Project Outputs folder, the file BCD8.VHD is created which is the VHDL file for the schematic document. It is added to the Projects panel in the Generated VHDL Documents folder. 2. Open the Messages panel to view any errors that may have occurred during compilation by selecting View» Workspace Panels» Messages or clicking on the Messages tab. If any error or warning messages appear in a Messages panel, you can double-click on it and you will jump to the appropriate line of the VHDL code or the correct place on a schematic. 3. Correct any errors in your VHDL files and/or schematics. Save your project files. Smart compiling your design The compiler also has an option to automatically determine the correct order to compile the files. This option is called Smart Compile and can be enabled by selecting the Smart recursive compile option in the FPGA Preferences dialog (Tools» FPGA Preferences). It goes through the files in the project in the bottom-up order and keeps compiling them recursively until either the design is fully compiled or no further files can be compiled. At the end of the process, it will allow you to set or adjust the compile order of the project

249 VHDL & schematic capture tutorial Simulating your design Optionally we can just start simulating our design. Before simulating depending on your preferences setting a compilation may occur, especially if any of the source or library documents were modified. 1. Open your testbench file, <name>.vhdtst, e.g. BCD.VHDTST. 2. Check or change any settings in the VHDL Project Options dialog by selecting Design» FPGA Options. 3. Select Tools» FPGA Preferences to check or change settings in FPGA Preferences dialog. The Waveform Viewer will be automatically opened when you select the Wave Options such as Show Waveform and Add top level signals to Waveform. Click OK. 4. Open the Simulation panel to view the data by clicking on the Simulation tab. 5. Select Simulator» Simulate to initialize the simulation. The Edit Simulation Signals dialog displays

250 VHDL & schematic capture tutorial 6. Select which waves you wish to be displayed and enabled for simulation. Enabling keeps track of what happens with the signal or variable, whereas only selecting Show Wave will display the wave but not save any associated history. Click Done and a blank.so file is created and opened in the Waveform Viewer. Click on its document tab to view. Note that the value U means Undefined at this stage. These values will change when you run the simulation. 7. After the simulation has been initialized, you can run your simulation to the end of simulation time as specified in your testbench file or you can use a debugging mode

251 VHDL & schematic capture tutorial Debugging mode When in debugging mode, you can use various step-by-step simulation options from the VHDL menu, such as Custom step (Simulator» Custom Step), Step Time, Delta Step, Step Into or Step Over. Ensure you have the Show Execution Point enabled in the VHDL Preferences dialog if you wish to see the current execution point. Setting breakpoints You can set breakpoints when the VHDL file is opened. Lines where you can set a breakpoint have small blue points visible in the left margin. 1. Click on the left margin next to the appropriate line of code to set a breakpoint. A red crossed circle appears to mark the breakpoint. 2. To remove a breakpoint, click on the breakpoint mark again. 3. You can open the Breakpoints panel to view the data by clicking on the Breakpoints tab. Running the simulation Once the simulation has been set up, all the Run options are available from the Simulator menu. 1. Select the appropriate run command, e.g. Simulator» Run. The Enter Time Step dialog displays. Enter a time period for the simulation to run and click OK. This time period will become the default time for the Simulator» Run for <time step> command. 2. The simulation is run. You can use the VHDL menu commands, Stop, End and Restart, during the simulation. 3. You can see your simulation results in the Simulation panel, Waveform Viewer and the Messages panel. The Simulation panel shows you a structure of a VHDL design and the signals or variables available, as well as the type and value of a current simulation time

252 VHDL & schematic capture tutorial In the Waveform Viewer, you can measure a time between events (Edit» Measure Time), set and jump to transitions or time marks (Edit» Jump), create a group of signal (Insert» Signal Group) or compare signals (Insert» Comparison). Adding Watches You can also add your own watches by displaying the Watches panel. 1. You can drag and drop any signal from the Simulation panel to the Watches panel as well as drag and drop into the waveform. You can also use the right-click menu to operate these features. 2. Open the Watches panel to view the watches by clicking on the VHDL Watches tab

253 Attributes for FPGA tutorial 15 Attributes for FPGA tutorial Attributes for FPGA Devices Placing Attributes Common Attributes PIN Locking Attribute Target Device Attribute Advanced Attributes Macrocell Attribute Critical Path Attribute Inhibit_buf Attribute FPGA_GSR Attribute Clock_Buffer Attribute Technology Specific Attributes Attributes for Xilinx Flavor EDIF output Other Attributes Attributes for FPGA Devices FPGA attributes are special directives that are used during the placement and routing of a FPGA design. They are used to control the linking of specialized components and utilize advanced features found on FPGAs. Typically attributes are placed in VHDL code or user constraint files and bear no meaning to any simulation outcome. DXP uses a unique way of placing attributes in your design by allowing users to directly place parameters in an intuitive design capture environment. Once placed, attribute information is automatically passed to the EDIF file allowing for easier integration and more rapid development of a system design using downstream tools. Attributes listed here are dedicated for the DXP design capture system, however almost all attribute information from third party FPGA vendors can be used. More information on specialized attributes used on ports and components can be obtained from your FPGA vendors. Placing Attributes Attributes are placed on components and ports by using the Parameters tab found in the Component Properties and Port Properties dialogs respectively. To place FPGA attributes, follow the steps below. 15-1

254 Attributes for FPGA tutorial 1. Display the Properties dialog by double-clicking on a port or schematic symbol and click on the Parameters tab. The project Parameters tab for adding FPGA target device information parameters is invoked by selecting Project» Project Options and selecting the Parameters tab. A schematic document s Parameters tab is accessed by invoking Design» Options and selecting the Parameters tab. For wire or bus attributes, for example the Critical Path attribute, the information is placed through a Parameter Set object found by selecting Place» Directive» Parameter Set. Its Parameters dialog can be accessed by double-clicking on the placed Parameter Set object. 2. To add the attribute in the Parameters section, click on the Add button. This will bring up the Parameters Properties dialog. 3. In the Name and Value fields, provide the name and value of the attribute respectively. Change the Type to correspond with the attribute type. Common Attributes The common attributes are almost always used in the FPGA design flow. They are used to fix the target FPGA device and its pin locking information on a FPGA project. 15-2

255 Attributes for FPGA tutorial PIN Locking Attribute The pin-locking attribute is used to lock the target device pins that are desired for signal and data processing. It is applied on ports in the top-level design unit. Syntax for parameter properties: Name: Type: Value: PINNUM STRING see below. Bus port pins can be allocated the value of its FPGA pin by using (, ) as a deliminator. These values are assigned to the elements of the port in a left to right order. For example: MY_BUSPORT[7..0] bus port can have PINNUM attribute Value: P1,P2,P3 The port is in descending order and any extra slices will be ignored. In this case MY_BUSPORT7 port slice gets P1. Another example is below: MY_BUSPORT[0..5] port can have PINNUM attribute value: P1,P2,P3,P4,P5 This time the port is in ascending order so MY_BUSPORT0 port slice gets P1 pin of the target device. Target Device Attribute The target device attribute can be used to pass information for some place and route tool. The place and route tool automatically selects the target device part name from its own selection menu. The attribute can be placed to avoid manual selection of target device name each time the EDIF file is loaded for compiling into the FPGA vendor s place and route tool. Syntax for parameter properties: Name: Type: Value: PART_NAME STRING see below. For example, the heart monitor project s top-level unit would have the value: 2S200PQ208-5 The value of the particular target device can be obtained from the manufacturer s place and route tool. 15-3

256 Attributes for FPGA tutorial Advanced Attributes The advanced attributes are used for optimizing the final outcome of the EDIF file. They also allow you to add information on selected ports and components. Advanced attributes include macrocell, critical path, inhibit_buf, FPGA_GSR and clock_buffer attributes. Macrocell Attribute The macrocell attribute is used on components that have EDIF macro files. It implies that the component is essentially a black box and should not be synthesized. It allows for the proper linking of the parent EDIF netlist output with the netlist from some other synthesis tools. By default, all components are assumed to be Macrocell, so this parameter is not generally required. Syntax for parameter properties: Name: Type: Value: MACROCELL BOOLEAN TRUE Critical Path Attribute The critical path attribute allows the user to select a wire on the schematic whose timing is critical. Since the synthesis tools add factoring on signals (wires), this causes time delay. The use of this attribute allows you to have control on factoring of signals (wires) in your design. To place this 15-4

257 Attributes for FPGA tutorial attribute, select Place» Directive» Parameter Set menu and add the attribute parameter as described in the Placing Attributes section of this tutorial. Syntax for parameter properties: Name: Type: Value: CRITICAL BOOLEAN TRUE Inhibit_buf Attribute The inhibit_buf attribute is used on selected ports to disable the insertion of I/O buffers if the EDIF for FPGA" generators Insert I/O Buffers is turned on. Syntax for parameter properties: Name: Type: Value: INHIBIT_BUF BOOLEAN TRUE FPGA_GSR Attribute If a FPGA design is compiled in several parts (and the EDIF linked later to another design) then the toplevel must have a STARTUP (or equivalent) symbol and the other levels must have a FPGA_GSR attribute attached to their RESET port. When used, the marked port is disconnected from any flip-flop preset or clear and for Xilinx the flipflop has an INIT properties added since some FPGAs have an active low GSR and require the appropriate signal in the VHDL be coded as active low. A STARTUP for Xilinx device or equivalent for other vendor s symbol must be placed in the top level and connecting its GSR input to a port. If the whole design is compiled in one pass (regardless of the number of entities) then no FPGA_GSR attribute is required. Syntax for parameter properties: Name: Type: Value: FPGA_GSR BOOLEAN TRUE Clock_Buffer Attribute This attribute causes a clock buffer to be added in place of an input buffer when the EDIF for FPGA generators Insert I/O Buffers is selected. If buffers are not being inserted, the user may simply place a technology specific clock buffer symbol before the system clock port. 15-5

258 Attributes for FPGA tutorial Syntax for parameter properties: Name: Type: Value: CLOCK_BUFFER BOOLEAN TRUE Technology Specific Attributes Attributes for Xilinx Flavor EDIF output 1. Xilinx_GSR attribute Same as FPGA_GSR but specific for Xilinx technology. Syntax for parameter properties: Name: Type: Value: Xilinx_GSR BOOLEAN TRUE 2. Xilinx_BUFG attribute This attribute adds a dedicated component on a system clock port. It also is used to override insertion of a general pad on a selected port when Insert I/O Buffers is ticked on. This attribute must be used only on global system clock ports. Syntax for parameter properties: Name: Type: Xilinx_BUFG BOOLEAN Other Attributes The DXP design capture system supports almost all attribute information provided by FPGA vendors and these attributes can be placed in the exact same manner. For example, the attributes for Xilinx FPGA technology, such as INIT (component initialization attribute used on LUT, ROM, FF, etc.) or RLOC (RLOC attribute constraint groups logic elements into discrete sets), can be placed following the steps described in the Placing Attributes section of this tutorial. The Type must be chosen to match as described in vendor-provided attribute or VHDL directive documents. 15-6

259 DXP & Altera Interface tutorial 16 DXP & Altera Interface Introduction Altera Integrated FPGA Library Altera Integrated PCB Library Supported Libraries Placing Common Attributes Importing EDIF Importing EDIF in Max+Plus-II Importing EDIF in Quartus Introduction Altera FPGA programming design can now be created easily using the schematic entry method and the Altera integrated schematic FPGA library. This tutorial will guide you with the necessary steps needed to start creating FPGA designs for programming Altera FPGA devices. By using the EDIF for FPGA schematic translator and the Altera library mapping file (LMF), your design can be routed and successfully downloaded on to a chip using the placement and routing tools available from Altera. Altera Integrated FPGA Library The Altera integrated schematic library includes the most common primitives and old style TTL macro components ready for placement in your design. The components in the library are grouped by functionality and type. Common functions can easily be found using sort by source. The integrated schematic library package includes the library-mapping file (LMF). This is provided for integrating and routing the generated EDIF file with the Altera placement and routing tools. Altera Integrated PCB Library There is a range of schematic PCB design libraries available to support your PCB design needs using Altera devices. 16-1

260 DXP & Altera Interface tutorial Supported Libraries This table shows the supported items that are included in DXP. For update information and library needs, please contact your ATS representative. Technology EDIF Support FPGA Library PCB Library Stratix Yes Altera FPGA PLD Stratix Apex 20K Yes Altera FPGA PLD Apex 20K Apex 20KE Yes Altera FPGA PLD Apex 20K Flex 10K/A/B/E Yes Altera FPGA PLD Flex Flex 6000 Yes Altera FPGA PLD Flex Flex 8000 Yes Altera FPGA PLD Flex Acex 1k Yes Altera FPGA PLD Acex 1k Max 3000A Yes Altera FPGA PLD Max 3000 Max 5000/A Yes Altera FPGA PLD Max 5000 Max 7000/A/E/S/AE Yes Altera FPGA PLD Max 7000 Max 9000/A Yes Altera FPGA PLD Max 9000 Classic Yes Altera FPGA PLD Classic EP Apex II Yes Altera FPGA Contact Altium Apex 20KC Yes Altera FPGA Contact Altium Mercury Yes Altera FPGA PLD Mercury Placing Common Attributes Common attributes can be placed for recognition by the Altera s placement and routing tools. Placing common attributes will eliminate extra time required to configure the placement and routing tools each time your design is compiled. To place pin lock information, use the values defined in the data sheet of your target device. For example use type 1, 2, 3 in the value field when you define the pinnum attribute. The attributes are automatically passed to the ACF and the TCL files used during compilation in Max+Plus-II and Quartus place and routing environments respectively. 16-2

261 DXP & Altera Interface tutorial Importing EDIF To download your design on to a chip, more advanced tutorials and documents are available from Altera. These steps are provided to get you quickly started with routing and downloading your design on to an FPGA device. Once you have created your design using the Altera FPGA library and have invoked the EDIF for FPGA netlister, check your project output folder that must contain EDF, ACF and TCL files. These files must be present in the directory where you wish to import and compile your design using the placement and routing tools. To compile your EDIF file for downloading onto the chip, you must use the LMF file available in the Program Files\Altium\Library\EDIF\ folder and use the Custom EDA/Tool Vendor setting. Importing EDIF in Max+Plus-II The Max+Plus-II package allows you to exploit the power of MAX, FLEX and ACEX devices. Following these steps will enable you to quickly get started with importing your EDIF with Max+Plus-II routing solution. 1. Insure that your compilation folder contains the EDF and the ACF file. Open the EDIF file by selecting File» Open from the menus. Browse and select the top-level EDIF file from your project output directory. Insure that there is no space in the design path to avoid potential errors during loading and routing. 2. Select File» Project from the menus and then select Set Project to Current File. 3. Select MAX+Plus-II» Compiler from the left hand side of the menu bar. This will change the menu bar to now include compiler drop down menus. 4. To set the LMF, click on Interfaces and select EDIF Netlist Reader Settings. For the Vendor, choose Custom and click on Customize >>. In the Customize section, place the net name you used in your schematic environment to define GND and VCC levels. In the Library Mapping Files section, tick on LMF#1 or LMF#2 and set directory path to the Protel_to_Altera.lmf file. 5. Choose the device and pin location from the Assign menu if not already set as attributes in the DXP environment. 6. Click on Start to compile your design. 7. Insure that you have installed the system drivers for your download hardware type. 16-3

262 DXP & Altera Interface tutorial 8. Bring up the programming menu by selecting MAX+Plus II» Programming. Configure your Hardware Setup and download the program onto the chip. Importing EDIF in Quartus The Quartus routing solution allows you to exploit the power of APEX devices. Following these steps will enable you to quickly get started with routing and downloading your design. 1. Select File» New and from the dialog and the Project Files tab, choose Project File. 2. In the New Project dialog, indicate the Project directory by opening the EDIF file in your planned compilation directory. The TCL file must be present in this directory. For the project name and Top-level design entity fields, values should be automatically inserted after opening the EDIF file. 3. Bring up the TCL Console window by selecting View» Auxiliary Windows. 16-4

263 DXP & Altera Interface tutorial 4. In the Quartus TCL console window, type source <design_name>.tcl. The design_name is the same as the name of the EDIF file generated from DXP environment. 5. To set the LMF file, select Project» EDA Tool Settings. Go to the Design entry/synthesis tool: pull-down menu and select Custom. Click on Settings to bring up the EDA Tool Input Settings dialog. Set Data format to EDIF and place your defined power net names if used in your schematic design. In the Library Mapping File section, set the path to the LMF file. 6. Select Processing» Compiler Settings. Set your FPGA device and other options from the various tabs available. 7. Select Processing» Start Analysis & Elaboration. 8. Select Processing» Start Compilation. Note any important information generated in the message output box. 16-5

264 DXP & Altera Interface tutorial 9. Analyze the information available from the Compilation Report hierarchy tree and re-set options as needed. 10. Select Processing» Open Programmer. Configure your desired mode and set your Programming Hardware type. Add your programming file and device. Initiate downloading by clicking on Start. Note that jam and jvc files can be generated from the Tools menu. 16-6

265 DXP & Xilinx Interface tutorial 17 DXP & Xilinx Interface Introduction Xilinx Integrated Architecture FPGA Library Xilinx LogiBLOX and Corelib FPGA Library Xilinx PCB Library Supported Libraries Xilinx Attributes Importing EDIF Introduction This tutorial explains the Xilinx FPGA schematic library and other important information that will enable you to start using DXP for programming Xilinx FPGA device with placement and routing tools. Instructions here will get you started with importing your design EDIF file into the Xilinx Design Manager Placement and routing tool. The Xilinx FPGA integrated library and tutorial here are based on the Xilinx Libraries Guide, available in ISE 4.1 and 4.2 place and route tools. DXP comes with range of libraries and features that enable you to begin programming FPGAs in an intuitive schematic environment. Xilinx Integrated Architecture FPGA Library Xilinx FPGA integrated library package includes all the necessary symbols used for schematic design entry. The integrated libraries contain both the Unisim and Macro types of components. Unisim libraries are a set of supported components that are pre-built on FPGA devices. Typically gate level components are available in all FPGA devices; however, some devices support more advanced level components. Some FPGA devices do not come with many of the pre-built components and therefore, to support such components, they are defined using gate level components. These types of elements are called macro components. Sometimes macro components are also used to define other higher-level function circuits. The uses of these macro components in your design allow efficient use of onboard FPGA device resources. The macro component design file is delivered in EDIF. If they are used in your schematic design, their respective EDIF file must be present in your placement and routing directory to successfully download on to the chip. 17-1

266 DXP & Xilinx Interface tutorial Architecture specific integrated libraries are packaged according to the selection guide provided in the Xilinx Libraries Guide. This insures that only specific components that are available with your target device are used in your design. Specific notes on some specialized components are also available in Component Properties dialog. The libraries include: Xilinx Spartan FPGA.INTLIB This library is used for programming Spartan family XC2S* devices. Xilinx Spartan-XL FPGA.INTLIB This library is used for programming Spartan family XCS*XL devices. Xilinx Spartan-II & Spartan-IIE FPGA.INTLIB This library is used for programming Spartan-II and Spartan-IIE family of devices. Xilinx Virtex & VirtexE FPGA.INTLIB This library is used for programming Virtex family XCV*, Virtex-E and Virtex-EM families XCV*E devices. Xilinx Virtex-II & Virtex-II PRO FPGA.INTLIB This library is used for programming Virtex-II and Virtex-II PRO families XC2V* devices. Xilinx CoolRunner-II FPGA.INTLIB This library is used for programming CoolRunner-II family of devices. Xilinx CoolRunner-XPLA3 FPGA.INTLIB This library is used for programming CoolRunner-XPLA3 family of devices. Xilinx XC4000E FPGA.INTLIB This library is used for programming XC4000E and XC4000L family of devices Xilinx XC4000X FPGA.INTLIB This library is used for programming XC4000EX, XC4000XL and XC4000XLA family of devices. Xilinx XC9500 FPGA.INTLIB This library is used for programming XC9500, XC9500XL and XC9500XV family of devices. See the support table below for information on how these libraries are relevant to your Xilinx target device. 17-2

267 DXP & Xilinx Interface tutorial Xilinx LogiBLOX and Corelib FPGA Library LogiBLOX is available as an accessory from Xilinx and allows you to generate your own specified component from a selection of common design module type. They are optimized for a particular FPGA architecture and are ready for instantiation in your design. The LogiBLOX integrated schematic library contains most useful schematic symbols of components ready to be added into your schematic design. For more information, refer to the LogiBLOX Guide. The CORE Generator System allows you to generate more complex IP modules such as Memory, Networking and Communication, and DSP core components. The generated EDIF files are also optimized for particular FPGA architectures. For more information, refer to the CORE Generator System User Guide. Corelib integrated libraries contain parameterized schematic symbols of IP cores available from the CORE Generator System. To use them, you will need to modify their Library Ref and Comment fields from the Component Properties dialog and the Display Name and Designator fields from Pin Properties dialog. To generate modules using LogiBLOX and Core Generator System, choose Other from the Vendor Name option and select B<1> from Bus Notation option. Xilinx PCB Library There is a range of schematic PCB design libraries available to support your PCB design needs using Xilinx devices. Supported Libraries This table shows the supported items that are included in DXP release. For update information and library needs, please contact your ATS representative. Technology EDIF Support FPGA Library PCB Library Spartan II E Yes Spartan-II & Spartan-IIE Spartan-IIE Spartan II Yes Spartan-II & Spartan-IIE Spartan-II Virtex II Pro Yes Virtex-II & Virtex-II PRO Virtex II Pro Virtex II Yes Virtex-II & Virtex-II PRO Virtex-II Spartan Yes Spartan Spartan Spartan XL Yes Spartan-XL Spartan XL Virtex Yes Virtex & VirtexE Virtex 17-3

268 DXP & Xilinx Interface tutorial Technology EDIF Support FPGA Library PCB Library Virtex E Yes Virtex & VirtexE Virtex-E CoolRunner II Yes CoolRunner-II Contact ATS CoolRunner XPLA3 Yes CoolRunner-XPLA3 CoolRunner-XPLA3 XC9500 Yes XC9500 PLD XC9500 XC9500XV Yes XC9500 PLD XC9500XV XC9500XL Yes XC9500 PLD XC9500XL XC4000E Yes XC4000 E XC4000 XC4000EX Yes XC4000 X Contact Altium XC4000L Yes XC4000 E Contact Altium XC4000XL Yes XC4000 X Contact Altium XC4000XLA Yes XC4000 X Contact Altium XC4000XV Yes XC4000 X Contact Altium Xilinx Attributes Xilinx FPGA attributes can be placed the same way as other attributes described in the Attributes for FPGA Devices document. For more detail information on Xilinx attributes, refer to the Xilinx Libraries Guide. To place pin locking information, use the pin designator character found in your target device pin table documentation. For example, use P<pin_number> format to define pin location for a PQ208 package. Importing EDIF To import your EDIF file for placement and routing, use Design Manager available from Xilinx. This program can be invoked from Program» Xilinx» Xilinx ISE4» Accessories. To download your program file on to the device, use Impact invoked from Program» Xilinx» Xilinx ISE4» Accessories. The instructions below describe how to import your EDIF file for routing and downloading on to a chip. 1. Select File» New Project from the menus. 2. In the New Project dialog, browse and open your top-level design EDIF file. Change the working directory or add a comment as necessary. 17-4

269 DXP & Xilinx Interface tutorial 3. In the New Version dialog, note the Part information that may have been added in the schematic project using the Target Device Attribute. Correct Part information if necessary. In the Copy Persistent Data section, you can also specify your UCF (User Constraint File). UCFs can be used to specify timing and other advanced attribute data to control your FPGA device. For more information on how to create a UCF file, refer to the Xilinx Libraries Guide. 4. Select Design» Options to add extra information or extracted simulation data during placement and routing of your design. Close the Options dialog and select Design» Implement. Note the new pop-up Flow Engine window that shows you the report and stage of your placement and route. This information is also available in the log report file. 5. Check you log file to see how much chip resources your design has taken. The log file also indicates warnings and errors that may have occurred during the routing process. 6. To establish connection with your FPGA device, run the program Impact from Programs» Xilinx ISE 4» Accessories. From the Configuration Mode Selection dialog, select the configuration mode to match your FPGA development board download configuration. 17-5

270 DXP & Xilinx Interface tutorial 7. Add the device configuration file by opening the BIT file. This is the Xilinx proprietary binary stream file that will get downloaded on to the chip for configuration. The file has the same toplevel design name and it should be present in the directory where your EDIF file was loaded or the working directory. 8. Initiate the download by right-clicking on the chip symbol and selecting Program. 9. Your design is now downloaded on to the FPGA device. 17-6

271 Making Electronics Design Easier article 18 Making Electronics Design Easier Abstract One Stop for Electronics Designers Dual Projects Schematic Capture Component Libraries Connectivity Verifying the Design PCB Preparation Comparing Documents Design Rules Placement Pre-Route Work Auto-Routing Splitting Power Planes Design Rule Check CAM Outputs Fabrication FPGA Design Pre-Assembly Tests Assembly Evaluation Abstract This article describes an entire design from the Engineer s perspective: dividing the job between PCB and FPGA design, then using DXP tools to complete both. The PCB project includes schematic capture across a hierarchy of sheets, components placement from integrated libraries, connectivity with net identifiers, ERC and simulation, PCB directives, synchronization with a PCB document, design rules, footprint placement, manual routing and auto-routing, splitting internal planes, DRC, fabrication and assembly outputs. The FPGA project includes simulation and synthesis for a specific target chip. Mention is made of op-code programming and debugging with TASKING tools. The article describes the finished product, and the successful completion of the job. 18-1

272 Making Electronics Design Easier article One Stop for Electronics Designers A medical research firm recently hired me to evaluate a microcontroller for SOPC (System on a Programmable Chip). This microcontroller was soft-core; rather than being an off-the-shelf component, it would be delivered as a set of VHDL source code to be implemented by the client on a chip of their choice. My job was to see if the core worked as advertised: that it could be installed upon an FPGA of my choice, and that it was op-code compatible with established microcontrollers of similar capabilities. To test such an FPGA, I had to design a circuit board capable of downloading application code to the chip. This board would also need an IO interface to test the microcontroller s response to diverse inputs. My evaluation required nothing elaborate; a simple four-function calculator application would be sufficiently robust, and would only require a numeric keypad and an LCD for testing. The bottom line is that I was able to do all the design work for this job in DXP. All of my front-end capture was done in nvisage DXP both for the FPGA and for the PCB. Because I used Protel DXP for the back-end routing and outputs the process from beginning to end was seamless. Dual Projects Each design you create in DXP gets its own project. What type of project it gets depends upon the implementation. So I created a PCB Project for my layout-bound schematics, and an FPGA project for my chip-bound schematic/vhdl design. I then saved them both in the same project group, so I could see all of my design documents together, and even work on both projects at the same time. My first priority was the board, since it would take the longest to get prepare. I knew I would have time to simulate and synthesize the source code for the microcontroller after I sent my CAM files to the board fab house. If everything went according to plan, I would have the FPGA routed and ready by the time the board was returned for assembly. All of the design documents that would be included in my projects had to be accessed through the company s version control system. DXP made this easy; the Projects panel not only displays each document, but also its status. Special icons beside each document will cue you visually as to whether it has been checked out from a storage database, and whether it has been compiled, opened or modified. Schematic Capture On a notepad, I sketched a block diagram for my design. The processor components (FPGA and PROM) would connect with a timer, keypad and parallel interface. Another block represented the power supply nets across the board. 18-2

273 Making Electronics Design Easier article DXP provides an intuitive link between block diagrams and project hierarchy. My top schematic sheet looked just like the diagram I sketched, with each block being a sheet symbol, pointing to an individual sheet or a set of sheets. Signals were carried between the sheet symbols along wires or buses, then down through the sheet symbols to ports on the subsheets. Component Libraries I proceeded to populate each sub-sheet with components from my prepared libraries. I have spent a considerable portion of my career developing and maintaining component libraries, and now with the introduction of DXP s integrated libraries I can package my Signals are carried between sheet symbols with wires or buses. signal integrity, simulation and footprint models together with the component symbol right from the start. Altium s library development center gave me a head start, providing over sixty thousand components (mostly integrated with models) with my installation. But that was simply the beginning. Over time I have developed my libraries to reflect my specific work requirements, matching appropriate symbols to models that I know are available through my suppliers. In fact, I have developed an elaborate system of library control outside of DXP. This has become a massive component database with a separate table for each component family, and an array of fields within each table. For example, my table for ceramic capacitors includes part number, manufacturer, capacitance and tolerance values, voltage rating, package and price. DXP allows me to link my projects to these external database tables, and then to precisely oversee updates to my libraries or design documents directly. I searched through DXP s libraries for the components I needed but didn t have in my database, then added its findings to the Libraries panel. A handful of components had to be created from scratch. Most were very basic, done in a few moments within DXP s library editor. Creating the symbol for the 208-pin FPGA was more complicated, but not burdensome thanks to the automatic incrementation and paste array features in DXP. I wouldn t know how the FPGA pins would actually be arranged until later, so at this point I arrayed them in a generic order, reassured knowing that I could rearrange them directly in the schematic design when I needed to. 18-3

274 Making Electronics Design Easier article Connectivity I m not going to describe the details of my pin-to-pin connections, except to say that DXP provides net identifiers and controls that allow me to hook up my design practically any way I can imagine. I like the hierarchy method, which only required that I use appropriate net identifiers at the sheet level and scope instructions at the project level. Other tools helped me arrange and connect my schematics, including snap-grids for placement and connectivity. One thing that happens when you compile your project in DXP is that your connections come alive. The sheet-level hierarchy is displayed in the Navigator panel, as are the components and nets/buses detected in your design, along with all of their associated elements. So no longer do engineers need to scrutinize netlists to review design connectivity. You may jump through each element of each net right at the schematic level. The Browser actually lets you do this from inside the schematic, as if you were walking down the connection lines yourself. But even after doing so, I still wasn t finished with these navigation tools. I would later return, when my board was synchronized with the schematic information, and use the crossprobing tools they offer. Verifying the Design Holding down the Alt key as you click in either the Navigator panel or the Browser, will highlight corresponding elements in both source and target documents. The current document remains active, so both must be displayed for this to have any visible effect. The other result of compiling a project in DXP is an electrical rule check. This is highly configurable, as you may stipulate which scenarios you want to flag, and how serious you consider them to be. Even when time is tight, I am a stickler about producing a clean ERC before sending information over to the PCB. I carefully set No-ERC directives on every unused pin, thus detecting unconnected input pins when I compiled. The messages that appear upon compile are more than just descriptive, they re interactive. Double-clicking on a specific message will list relevant primitives in a floating panel as links, which will let you jump between them in the workspace. This lets you discern and resolve each error quickly. Recompiling the project will show if your previous errors have been fixed, and if any new ones have been created. After running a clean ERC, I simulated the timer portion of my design. I ran two signals (trigger input and clock output) through a transient analysis to make sure that the required signal would be generated as expected. Of course, a simulation requires that each contributing component has a valid SPICE model that is appropriately mapped to the symbol s pins. This can be done either at the library level or within the captured schematic. Signal integrity tests are not as stringent (having a formally established protocol), and allow generic models to be substituted where no specific model is indicated Simulation results may be displayed individually or superimposed upon the same graph.

275 Making Electronics Design Easier article PCB Preparation Satisfied (for the time being) with my schematic design, I turned my attention to board layout. Before leaving the schematic editor, however, I had to make sure that my schematic design would send all the necessary information to my PCB design. I already mentioned that I had used an integrated library for this project. This means that the schematic parts I used were already associated with the PCB footprints I wanted to use before I even placed them in the schematic design. You get an integrated library when you compile the package that contains all the source schematic libraries documents as well as the models. Should any mismatches exist between pins and pads, or model names, these will flag as errors in the Messages panel when the integrated library package is compiled. So most of the correlation between PCB and schematic was done before I even created a blank PCB file. had already been done at this point. If I hadn t made use of integrated libraries, I would have had to take special care that each footprint referenced within my schematic design was available to the synchronizer. Any mismatches between symbol pins and footprint pads would be flagged upon performing the board updates. The Layer Stack Manager shows a cross-section segment of the board. Layers may be added or redefined in this dialog. I generated a PCB file using the template wizard, measuring its outline according to my specifications, and giving it two signal layers plus two internal planes. Once the bare board was saved and added to my PCB project, I could update it with the components, nets and directives indicated in the schematics. Comparing Documents When you have DXP show the differences between two documents, it assumes you ll want to update one from the other. Of course, you don t have to. If you are simply trying to document the differences between two, as you would within a version control system, you could create a report then cancel the update process before executing anything. 18-5

276 Making Electronics Design Easier article My board held no footprints as of yet, so I didn t have to manually match schematics with PCB components. I simply applied all the detected differences towards the PCB, sending all footprints, component classes, nets, net classes, and room definitions to the bare board. Because my library panel contained the same integrated library from which I had populated the schematic, and because each schematic symbol I used had a valid footprint matching pads to pins, I was confident that I could proceed without much to worry about. Still, as a matter of course, I ran a check to validate each of the proposed changes before executing them. As the board was updated, footprints were arranged alongside the board, each within a room as I had retained the default setting of grouping components from each schematic sheet together. While schematic-based rooms don t make sense on every board I design, such cases are becoming rarer, as I have begun designing my schematics with the PCB in mind, grouping symbols much the same way as they should be arranged on the board. Each electrical pad in my design is linked to at least one net companion by a connection line. This ratsnest of From-To s will be my primary aid in the big job ahead: component placement. Design Rules I always establish design rules (at least a preliminary set) before even so much as dragging a resistor across my board outline. In fact, many of my rules came from the schematics themselves. For example, I knew when I was wiring up my schematic that I would want some extra clearance around my power and ground signals, so I placed a PCB directive on each of these nets, and defined the width rule right there. When I went to set up the rest of my PCB design rules, I could see that my schematic-driven rules were all included just as I had defined them they even included unique identifiers in case I made any modifications on the PCB side. It always makes the best sense to spend time right up front crafting a complete set of design rules. Not only will the online DRC flag you immediately when violations occur, but DXP will actually prevent you from creating violations in the first place. So specific design rules will serve as reminders and guides as you place and route your board. The autorouter, too, will look to the design rules you have established to know where and how to run tracks. I have developed a set of rules that I keep using in similar projects, such as preferred track widths for signal and power nets, and minimum clearance between components. Instead of starting each set of design rules from scratch, I can import ones I ve already created in similar designs. Another trick I have learned is to save a read-only copy of a blank board with all the design rules set just so, then referencing that board in a template project. Creating new PCB projects from such templates not only gives me all my customized project settings, but also the board file with my preset design rules. Right-clicking in the Design Rule tree allows you to import and export individual rules. This project required some slight modifications to my preset rules. Having the luxury of power planes on this board, I could disable width rules for power nets. I modified the clearance rule for the keypad button components, as I wanted them on a very specific grid to give a clean user-interface. 18-6

277 Making Electronics Design Easier article The design process is highly iterative between the schematic design and the PCB, and my set of design rules always continues to develop throughout the whole process. But I have both seen the benefits of preparing an elaborate set of design rules before layout, and suffered the effects of hastily bypassing this step. Placement I reserved the board s lower half for the numeric keypad. The LCD, FPGA and the parallel port took up much of the remaining space, leaving me little room to fit the remaining 70 components. This was challenging, to be sure, but nothing out of the ordinary. Place, not space, is the name of the game during board layout. I chose not to use any auto-placement tools for this board, relying instead on the basic ones: snap-grids and connection lines. By setting high values for the placement grid, I dragged the keypad buttons and other major components directly into alignment. Then, after lowering the grid, I began arranging components individually, using the connection lines as my primary guide. I watched these lines with the care of a puppeteer as I positioned the remaining footprints, knowing that the quality of route will follow the quality of placement. This process was simplified by the choice I explained earlier of having a room generated automatically to contain the components of each schematic sheet. I had designed my schematics with the board real estate in mind, trying to keep components that should be placed near to one another on the same sheet. That way they started the board process together, and I had less of a jigsaw puzzle to sort out once the Careful attention to the ratsnest of connection lines will yield better placement, and therefore easier routing. footprints were transferred to the board. Instead, I was able to spend most of my time on the finetuning. Pre-Route Work Because this was a prototype board, I indulged myself with two internal planes one for power and another for ground. Had I planned to produce this board in high volume, I couldn t justify the additional cost of a four layer board that could easily have been two. Without planes, I would have had to do more pre-route work, laying tracks around the board to make power and ground nets more accessible to nodes in crowded areas. As it turned out, my only task prior to routing the board was to place keepout areas where I didn t want any routing to occur. Specifically, I wanted no signal tracks or vias to run beneath the keypad buttons or the FPGA. I was reserving the area under the FPGA for a polygon fill, which I would later stitch to the ground plane by a 18-7

278 Making Electronics Design Easier article grid of vias. This provides a ground current return path that matches the current flow on the FPGA, reducing RF emissions. Autorouting Instead of auto-routing the entire board, I decided to do it in two stages. First, I ran the router with only the fan-out pass enabled. This extended tracks from the active pads on my FPGA. Once the fan-outs looked good, I locked down all my pre-routes and vias, then ran the router again, this time with all passes turned on. Some clean-up work is always required after running the auto-router although powerful re-routing tools help by removing loops, straightening connections and cleaning pad entries. Fortunately, Protel DXP s push-and-shove capabilities helped me re-route tangled areas while preventing me from violating my own design rules. Splitting Power Planes Although I had dedicated an entire internal plane for my power nodes, not all of these nets were of equal voltage. The PCB editor allows internal planes to be sub-divided for different nets sharing the same physical layer. First I assigned 5V as the default net for the plane. Then I ran the split-plane option, carving an area around all the 3.3V nodes, then another around all the 2.5V nodes. Internal planes may be sub-divided for different voltage nets. 18-8

279 Making Electronics Design Easier article Design Rule Check With the online DRC enabled, I had monitored my design for violations from the start. In addition, all of my design rules fell within the auto-router s scope, so I didn t expect to see many errors at this point. I had, however, done some manual placement and post-route clean-up work, so I knew that there had been some room for mistakes to be made. In any case, I have long since learned not to skip the step of checking my design for errors before generating final artwork. The DRC listed errors categorically; for example, unrouted nets were listed as broken, and connections between nets were listed as short circuits. Browsing through the list of violations, I could zoom in on each error, discover what caused it and decide what to do about it. Each error disappeared from the list as soon as it was resolved. CAM Outputs Once my layout passed all of my design rules, I was ready to generate the artwork for both fabrication and assembly. I required Gerber files for both signal and plane layers, as well as three mechanical layers. A fourth mechanical layer included basic board dimensions, as well as my company s signature logo, so I wanted to merge its contents all of the other Gerber files. I also needed to include an NC Drill file, a Bill of Materials report, and a Pick-and-Place file for assembly. Instead of configuring each of these outputs separately, I added an output jobs file to my design, which analyzed my design and offered pull-down lists showing the PCB s and schematics in my project. Every output job I needed could be defined here, and configured with specific settings and precision. The best thing about the output jobs file is that it offers one-button generation for the whole lot (printed and CAM files alike). On the other hand, you still have the option to create individual or selected output jobs instead. All CAM outputs were saved on my hard drive, where I could make copies to to the board house. Before doing so, however, I followed my career-long policy of checking the Gerbers myself. Protel DXP includes CAMtastic, an editor for viewing and manipulating Gerber data, and with it I scrutinized each layer of information that my board house would see. I also reviewed the NC Drill file, which automatically detected duplicate hole references and stripped them from the file. It also included a report to show me where to eliminate the culprits in the original design. Once the files all checked out, I ed them to the board house. Fabrication Having used the same board house for five years, I knew exactly what four things they would require: board dimensions around each of the Gerber layers, a symbol legend alongside a drill map, an NC Drill file, and a phone call. In this case, however, my contact at the fab house called me, having discovered some untented vias on the design. My policy is to tent all through-hole vias; my board house uses a liquid photo-imagable 18-9

280 Making Electronics Design Easier article soldermask which actually produces half-tents, meaning that the copper is covered but the hole remains open. This is, in fact, my preferred solution, as it both shields the vias from solder-bridge shorts and avoids the acid pits that can fester under fully tented vias. I was surprised to learn that I had left the tenting option unchecked on a group of vias. My contact made the changes on my approval, and I updated my design to keep it in sync with production. FPGA Design While the board was being fabricated, I finished the FPGA design. Delaying this until now was a little tricky, since the footprint decal was already being etched across town a bit like pouring a foundation before designing the house to go on top. But the Xilinx series I had chosen offered a range of FPGAs that would fit on the same footprint. Knowing the approximate number of gates required for this evaluation, I had pre-selected a land pattern that could accommodate parts with up to 150,000 gates, far more than I would need. The microcontroller in question had been provided as a series of VHDL entities, architectures and test benches, which I added to my FPGA project in DXP, where I would analyze and optimize the core for the FPGA family I had targeted. First, I ran simulations to make sure that the design was sound. Once satisfied, I ran it through the synthesis engine, which optimized the routing (minimized the gate count), and verified that my design would indeed fit on the FPGA I had chosen. The place-and-route image produced by DXP could then be fed into the chip vendor s software for burning the FPGA. I used another Altium product for programming sample op-code for my evaluation. TASKING is a tool for writing, compiling and debugging code that can be uploaded onto specific processing chips or FPGAs that use compatible cores. Although these programs could have been burned into the FPGA along with the microcontroller, I preferred to wait. I wanted to use the COM port interface to test the field-programmable features of the FPGA after the board was assembled. In the meantime, these codes were burned onto PROM chips that would feed instructions to the FPGA externally. My timing was nearly perfect. I received the boards back one day before finishing the SOPC. Pre-Assembly Tests My board house has a general policy of testing every board it sends out either with a bed-of-nails, which requires a jig to be generated for the board, or with a flying-probe, which is slower but more economical for fewer boards. Because mine was a prototype board, however, I arranged for them to make two boards and let me do the testing myself. I started at the superficial level: visual checks matching the printed board to the original artwork. I eyeballed the track widths and hole sizes across the board, and verified that the holes were all centered on their pads. I checked that each designation could be clearly distinguished during assembly. I had recessed my power planes on this board, but I still scanned the edges for any glimpses of exposed metal that would short my planes

281 Making Electronics Design Easier article Visually checking the planes, of course, was not enough. Connecting distinct planes with a multimeter indicated infinite resistance, confirming that there were sufficiently isolated from one another. Similarly, the multimeter showed zero resistance between connected nodes, confirming continuity. Assembly I took the bare boards down to the lab, where we have some assembly equipment nothing really fancy, but enough to put my two prototypes together. If we had been mounting a large number of boards, we would have sent them to a proper assembly house with paste-mask dispensers, pick-andplace machines, wave solder apparatus and heat ovens. My two boards, however, were assembled the old-fashioned way, with an iron in one hand, and a coil of solder in the other. Perhaps old-fashioned isn t the right term. Because of the dense pitch of my 208-pin FPGA, I needed precise (if not automatic) instruments. Under the magnification of a 10X stereo microscope, I touched each pin with a 0.4 mm solder tip on a temperature-controlled iron, and 0.25 mm rosin core solder. I tacked each corner of the main chip before proceeding to the inner pins, as uneven surface tension can pull components off center. Once the FPGA and all other surface-mount components were fixed to the board, I moved on to the larger, through-hole elements, using an assembly drawing as a guide. Lacking the density of the surface-mount devices, each through-hole component could be soldered without using the microscope. Even at this point, I found I was not done designing. Throughout the processes of fabrication and assembly, I had noted changes and clarifications that I wished to update in my PCB project. For example, I made some minor design modifications on the silkscreen layer where a designator was obscured by overlapping lines. I also included a readme file describing the assembly process I followed for the prototype. Evaluation Once the boards were assembled, I ran some electrical tests. Using a CRO, I tested each rail for the proper voltage, each oscillator for the proper frequency, and each switch on the keypad for the proper signal. I also ran down my bench supply to ensure that the boards would shut off at an appropriate level. In addition to the calculator and timer applications, I had written some code to strobe the LCD display characters and the individual switches on the keypad. Once both ends of the user interface checked out, I was ready to load my application software. My circuit was designed with an emulation ROM capability, which allowed me to download software instructions over the parallel port cable. The software programs I uploaded turned each board into the four-function calculator with a timer. I then turned the two boards over to a testing teams, who verified that the microcontroller worked as expected

282 Making Electronics Design Easier article Once we were happy with the application, I re-routed the FPGA so that the microcontroller automatically booted with the software

283 Tips for Design Capture article 19 Tips for Design Capture Abstract Grids Placement Stages TAB key Control Re-entrant Editing Arrays Copy and Paste Post-placement Edits Annotation and Re-Annotation Dragging Objects Default Attributes Abstract This article summarizes the basic concepts of design editing in DXP, emphasizing concepts that are consistent between the schematic and PCB editors. Grids DXP offers three grid types: visible grids for navigation; snap grids for placement and electrical grids for aiding the creation of connections. Grids are document options, meaning that they are saved with the individual design, so grid settings may differ between one design document and the next. Designers will find more grid options in PCB documents than in schematics, due to the greater need for precise placement in PCB. Visible grids appear whenever the zoom level will allow them to be sufficiently spaced. PCB documents can present a major and a minor grid. Schematic documents, on the other hand, offer only a single visible grid. Both PCB and schematic support displaying the grids as either lines or dots. Visible grids may be disabled in either editor. The snap grid in schematic as always square, while in a PCB document the X and Y values can be modified individually. The PCB editor further differentiates between primitives and components, allowing you to have a separate grid for each. Typically these PCB grids are set to either a multiple of the component pin pitch, or a fraction of it. For example, while placing components with a pin pitch of 100 mil, a component grid of 50 or 100 mil could be used. To route one track between the pins of these components, a primitive snap grid of 25 mil could be used. Working with appropriate grids will assist in orderly component placement and provide the maximum amount of routing channels. 19-1

284 Tips for Design Capture article Overriding snap grids are electrical grids, which allow connections to be made to off-grid parts and footprints. If enabled, electrical hotspots in the design will emanate a pull like a gravity field, attracting the hotspots of any new routable object that hover within its range. Imagine you are moving an electrical object in the workspace. When it falls within the electrical grid range of another electrical object that you could connect to it will snap to the fixed object, and a Hot Spot or highlight dot will appear. The electrical grid should be set slightly lower than the current snap grid or else it becomes difficult to position electrical objects one snap grid apart. Grids can be quickly modified, or toggled between enabled and disabled, through keyboard or mouse shortcuts. Placement Stages All objects in your design must undergo two placement stages. The first is when you activate the placement procedure for any object. At this point, the object hangs upon the cursor, waiting for stage two, which is setting the object down. It is important to consider these placement stages separately because a window of opportunity has been built between them. TAB key Control If you press the TAB key after you initiate placement (stage one) but before you choose the location (stage two), the object s properties dialog will appear, allowing you to modify the default settings for any of these fields. Since placement is a round-robin, returning you to stage one after you finish stage two (this cycle is only broken by pressing the Esc key or right-clicking the mouse), this TAB-key control of object properties has particular importance. Any attributes you modify in one instance will be remembered for the next, until you break the placement cycle. The only fields that will be different with each sequential placement of an object are those which can increment automatically (such as Designator fields), if the active value of such fields ends with a number. Actually, not only are the changes you make remembered during this placement cycle, they also become the defaults for that object (unless the Permanent option is enabled for the Default Primitives more on this later). Re-entrant Editing Thanks to DXP s concept of re-entrant editing, keyboard shortcuts remain active while you are placing objects. For example, pressing the Spacebar when placement has been activated will rotate the object. Doing so will not disrupt the placement process. Once you set the object within your design, another part will appear ready upon your cursor now rotated. Arrays Arrays of objects can be placed in both schematic and PCB (circular arrays are available in PCB only). These, too, will copy the properties of the original object, with the reference designator s numeric suffix incrementing upon each iteration. 19-2

285 Tips for Design Capture article Copy and Paste Another way to place new objects is by copying and pasting existing ones. This process (available in all DXP editors) is also sensitive to object properties. Single or multiple objects may be copied then pasted, with the exact same results as described above. Selections may be pasted as an array, allowing many iterations with a single command, and affording otherwise unavailable features, such as text increments beyond just one. So instead of having U1, U2, U3, you could paste a numeric array such as U10, U20, U30 (by setting the text increment to 10), or an alphabetic series such as U1A, U1C, U1E (by setting the text increment to B). You can also enter a multiple paste mode using the Rubber Stamp option, here you can paste the clipboard contents over and over, until you escape. Post-placement Edits Multiple tools are available for attributes you choose not to finalize during placement. The most obvious is that any object can be edited by simply double-clicking on it, which opens its Properties dialog box. Several other useful tools will help you work with groups of objects at a time, including the Find Similar Objects dialog, the List panel, and the Inspector panel. Annotation and Re-Annotation Both the schematic editor and the PCB editor offer a positional annotation option. Also, the schematic annotation feature allows you to match components by parameters, and offers designator index control and suffix options for project sheets. Transferring annotation information between schematic and PCB is normally done through ECO s (engineering change orders). Otherwise, schematic designs may be back-annotated through the Was-Is file created when the PCB was reannotated, which loads via the schematic Annotate dialog. Dragging Objects Once items are placed, they may be connected together. The basic form of connectivity in the schematic is the wire, and the basic form of connectivity in the PCB is the track. While many other options are available, such as net labels and ports in schematics, or fills and planes in the PCB, these two forms of connectivity are so common to designs that a certain common design philosophy has been applied to both. DXP uses this philosophy to distinguish between the verbs: to move and to drag. To move an object is to reposition it without regard to objects in contact with it. Moving a component, for example, will not 19-3

286 Tips for Design Capture article move any of the wires or tracks connected to it. Dragging the component, on the other hand, stretches the wires or tracks out after it, maintaining connectivity. The default option is to move rather than drag. You will discover this if you try the most intuitive method, which is to grab a component with the cursor by holding down the left mouse button, then move the mouse. This will not bring any connectivity along with it. The Drag process is accessed via the Move submenu, which then may be applied to primitives or components alike. This, like other processes, may be accessed through special keyboard and mouse shortcuts, and may apply to single or multiple objects at once. Default Attributes Any object you set down into your design has certain attributes. If you are placing an object from a library document, then the properties assigned in the library will determine what is placed by default in each field upon placement into your design document. Primitives, on the other hand, are objects created directly within the design document, and contain default values that may be modified before they are placed. This is done in the Preferences dialog, under the Default Primitives tab. Modifications may be saved or loaded. System defaults are remembered and may be restored singly or for all primitives. A Permanent checkbox allows you to control how persistent these defaults should remain during placement. 19-4

287 Project Essentials article 20 Project Essentials Abstract Project Paradigm Project Power Project Templates Abstract This article describes projects, which embody the most powerful features of DXP. These include hierarchical and even multi-channel schematic design with interactive error-checking and net navigation tools, a bi-directional comparator between schematic and PCB components and database linking. Many settings are stored at the project level, which template files may incorporate for future projects. Project Paradigm DXP has introduced the concept of projects. Don t get caught thinking that a project is like a database file, which Protel 99 SE users have known. The most obvious difference is their size. A database file actually contained all of the design documents, and would sometimes grow to an immense size. Project files, on the other hand, are simple text files. They do not contain any files, but simply reference them, like an index. So when we talk about adding documents to projects, we re simply talking about creating links. If these links point to documents on the same drive, the link path will be saved in relation to the project file. That means that project files are very vulnerable. Try moving one from one place to another, and you will see that all of its links (except those to documents on separate drives) are discarded when you next open the project in DXP. For this reason, we recommend that you save each of your projects in its own folder, and save all of the project documents there too, or within subfolders there. This will allow you to move or copy the project (top) folder to another location without disrupting any of the links. Think of projects as an association of documents, which may be stored in various locations across networks and/or disk drives, thus opening the door to external version control and library management systems for DXP users. And, because documents exists externally to projects, users may include the same document within multiple projects. Note: Related projects can be packaged together in a single project group file. This references projects the way projects reference design documents. 20-1

288 Project Essentials article Project Power But a project does much more than assemble documents; it makes them interactive. After all, documents may be opened directly in DXP, bypassing the project altogether. But compiled projects offer many features that do not apply to free documents. These include multi-sheet design and connectivity navigation tools, multi-channel support, multiple implementation documents, and even variants within each individual implementation document. When output job or database link files are added to a project, they will interact with the design documents. When a schematic hierarchy is synchronized with a PCB document, all components can receive unique identification tags to facilitate future updates in a reliable and flexible manner. Compiling a project will discern a hierarchy of schematic documents, and submit them to ERC checks as stipulated in the Project Options dialog. Errors and warnings will all appear in the Messages panel, which is itself an interactive tool with double-click and right-click functions to cross-probe the design for additional information on specific compile errors. The Navigation panel and the Browser also come alive when your project is compiled, allowing you to follow individual component, pin, net and bus connections between sheets. Other settings which are saved at the project level include the kinds of differences that should be detected and/or updated in documents you compare, the general behavior of your navigation tools, and the naming conventions for multi-channel designs. All of these are highly configurable. You may even assign system or user-defined parameters at the project level. Project Templates If you have specific project settings you like to use that differ from the default DXP projects, you may want to remove the design documents and save a copy of the project in the Altium\Templates folder. This will allow your future projects to inherit the settings you have crafted. Some documents, like the output job and database link files discussed earlier, may be appropriate for inclusion in a project template. If you have certain libraries which should only apply to certain projects, rather than everything you work on in DXP, you could also include them in the template file for similar projects. But you should remember that any documents you include in the template project file will link to the actual document, rather than creating a set of new documents. If you really have design documents you wish to use as templates within a project template, you should set them to read-only status, which will prevent you from saving modifications over the originals. Notice that you don t have to invoke the New Project from Template command from the Files panel if you don t want to. You may create a new process launcher with WorkspaceManager:OpenObject in the Process field and with the ObjectKind=Project OpenMode=NewFromTemplate in the Parameter field. This will open the Templates folder, and display project documents. After you select one, it will then create a new project based on this template. 20-2

289 Component, Model & Library Concepts article 21 Component, Model and Library Concepts Abstract Component, Model and Library Concepts Definitions Fundamentals Library Types Component to Model File Linking Valid Search Locations for Model Libraries General Search Order Abstract This article defines components, models and libraries, then explains their relationships. Readers will learn how to arrange and configure their libraries to provide valid links between components and models. The search sequence for matching models is explained, as well as options that will make this search more restrictive for specific models. Component, Model and Library Concepts Components are the basic building blocks of an electronic product. During the design capture and implementation processes, components need to be represented in different ways: as logical symbols on the schematic, as footprints (decals) on the PCB, as SPICE definitions for simulation, as code for VHDL simulation and synthesis, as EDIF netlists for place-and-route, and as generic or IBIS models for signal integrity analysis. Not all of these representations are necessary for every component, but the logical one is the starting point. Every component must be defined, at the very least, with its own name in a schematic library. It may contain pins and graphic symbols in single- or multi-part fashion, and even have alternative display options. As such, it may be placed in any schematic design. But until models have been added to the component, it cannot be implemented in any practical sense. Definitions Component: an object which can be placed into a design. Model: a representation of the component which is useful in some practical domain. 21-1

290 Component, Model & Library Concepts article Domain: type, group, or area of representation. In DXP the valid domains include PCB layout, SPICE simulation, EDIF netlisting, and Signal Integrity analysis. Library: a file containing a collection of components, or a collection of models, or both. Model Library: a file containing a collection of component models. Component Library: a file containing a collection of schematic components. Integrated Library: a file containing a collection of schematic components, and their associated models. Fundamentals At the schematic stage, the design is a collection of components which have been connected logically. To test or implement the design, it needs to be transferred to another modeling domain, such as simulation, PCB layout, signal integrity analysis, EDIF, and so on. Each domain needs some information about each component, and also some way to map that information to the pins of the schematic component. Some of this domain information resides in model files, the format of which is typically pre-defined, examples of these include IBIS, MDL and CKT. Some of the information does not reside in the model files, for example the SPICE pin-mapping and netlisting data must be stored and managed by the system. All of the necessary domain information, including pin mapping, is contained within the schematic component, which stores a separate interface to each model that has been added to it. In effect, the complete model is the combination of the model mapping information stored in the component, and the domain modeling information stored in the model library. Components may have models for multiple domains, and can also have multiple models per-domain, one of which will be the set as the current model. Library Types There are three types of libraries in DXP. 1. Model libraries the models for each domain are stored in model containers, typically called model libraries. In some domains, such as SPICE, where the storage is typically one model per file, they are also referred to as model files. In other domains the models are normally grouped into library files according to a user-defined categorization, such as PCB footprints grouped into package-type libraries. 2. Schematic libraries these contain schematic components and their model interface definitions. Each model interface definition contains a link to its respective model library. 3. Integrated libraries these are a set of schematic libraries, which, together with their linked model libraries, are 'compiled' into one file the integrated library. The advantage of compiling into an 21-2

291 Component, Model & Library Concepts article integrated library is that all component information is available in a single portable file. Integrated libraries cannot be edited without extracting the sources, and recompiling. Component to Model File Linking There are various levels of rigor that can be applied when specifying the link to the model file. Although they vary slightly from one model type to another, they generally include these options: Any searches all valid libraries for a matching model. Library name only searches valid libraries of this name for a matching model. Library path only searches valid libraries in this location for a matching model. Integrated library draws the model directly from the integrated library used to place this component, assuming the library is still in a valid location. This option is enabled automatically when you compile an integrated library. This matching only applies when the link is being resolved at the schematic sheet; it does not apply at the library creation stage. Valid Search Locations for Model Libraries The valid search locations when resolving the link from the component to the model information depends on where the search is being performed. There are two distinct environments where searching occurs during library creation, or during schematic editing / design transfer. The search order is the same for both. General Search Order The rule is to stop searching for a model as soon as a match is found. For all models not tied to an integrated library, the search will proceed in this order: Project Libraries PCB libraries (not integrated libraries) in the currently Installed Libraries list Search Paths If you are using the Libraries panel, you will notice that this order is followed from left to right through the Available Libraries dialog. In fact, since the available libraries can be ordered within this dialog from top to bottom, the entire search sequence is intuitive and easy to set up. While DXP offers flexibility and control over your model locations, it does require you to use the correct file extension for each model type. For example, a footprint cannot be found unless it is in a file with a *.lib or *.pcblib extension. Similarly, a SPICE.subckt will not be found unless it is in a *.ckt file, nor will a SPICE.model if it is not in a *.mdl file. Whenever a model search does not yield a match, an interactive error will appear in the Messages panel. 21-3

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293 Enhanced Library Management using Integrated Libraries article 22 Library Management using Integrated Libraries Abstract The World without Integrated Libraries The Benefits of Integrated Libraries Creating an Integrated Library The Libraries Panel Placing from an Integrated Library Keeping Integrated Libraries Available Abstract This article introduces integrated libraries, describing how they are created, what they contain, and how they can be used. The World without Integrated Libraries Schematic libraries allow you to attach footprint, simulation and other models to components. Usually, each of these models is contained in a file somewhere outside of the schematic library. PCB footprints will be found in PCB library files; simulation models (with some exceptions) are contained in model or subcircuit files. So the schematic library saves a link, that is, instructions on where to find each model you attach. Periodically, DXP will need to locate these models when you run a board update, for example, the linking instructions will be followed for all current footprints in your design. The search sequence for matching models starts with libraries in the current project, then installed PCB libraries, then any files found on the project search path. The library management is left entirely in your hands, meaning that DXP cannot offer any guarantees that your models will find matches. These links in schematic libraries are brittle, and easily broken. To make matters worse, you won t find out about broken links until you need them. The Benefits of Integrated Libraries DXP has introduced a solution: the integrated library. This is a set of schematic libraries with all associated model libraries bundled in. If a component came from an integrated library, DXP is guaranteed to find the right model if it can simply locate the integrated library it came from. 22-1

294 Enhanced Library Management using Integrated Libraries article Because the components and models are entirely contained within a single.intlib file, these libraries offer portability to designers who divide their work among different workstations, or who want to share their designs with others. Simply installing the same, single file in the Libraries panel of any PC running DXP will mean that component-to-model links will remain secure (assuming, again, that components were placed in the design from that integrated library). These libraries are also checked for integrity when they are compiled. That means they are not only checked for availability, but for correct pin mappings. Even designers who want to stay with discrete library files should compile their schematics in an integrated library package, if only to ensure that the source components will map correctly to the target models. Once satisfied, they can ignore the integrated library they created, and keep placing directly from their schematic libraries. Creating an Integrated Library There is no document editor for integrated libraries. They are a by-product of compiling an integrated library package, which is analogous to PCB or FPGA projects. Add library files to the integrated library package, as you would add documents to any other project. The only documents that must be added to the integrated library package are the schematic libraries you wish to include. The model files may be located in any valid search location (within the project, within PCB files in the Installed Libraries list, or down the search path(s) specified for the package. That is the search order as well: left-to-right and top-to-bottom if your are viewing the lists in the Library panel. Whether you prefer to gather your libraries into your project or to locate them by search paths depends on your particular working style. If you are checking and editing models as you prepare the integrated library package, you may want to have the model libraries right at your fingertips, and so add them to the package itself. If you are continually adding model libraries to specific folders on your hard drive or network, then you may prefer to use the search paths, letting the compiler detect newly added libraries automatically. Like any other project, the compiler for an integrated library package will generate a list of warning and error messages. You will be warned of any models that were not found, meaning that no matching names were found in the package or on the search paths. Additionally, you will be warned of any mapping errors, such as mapping instructions to pads 1 and 2 when the actual footprint contains pads A and K. The integrated library file is created when the package is compiled. Remember, what you have been working on until this point is the integrated library package (.libpkg), not the actual integrated library file (.intlib). No integrated library exists until the package is compiled. The Libraries Panel Opening an.intlib file in DXP will let you do one of two things. Either you can extract the source documents of the integrated library in a new integrated library package, or you can add the integrated library to the Libraries panel. This panel offers the only direct view into the integrated library file itself. 22-2

295 Enhanced Library Management using Integrated Libraries article In fact, this panel was built for integrated libraries. Notice that you can browse schematic libraries only by component, and PCB libraries only by footprints. Integrated libraries, however, can be browsed by either, and browsing them by component will let you see the component to model relationship. All models attached to a component are listed in this view of the Libraries panel. Only found models are included in this list; you should refer to the Messages panel to make sure that all of the models you attached to your components were found and validated. Notice, however, that no editing buttons are available in the Libraries panel. Again, this is only a window for viewing the integrated library; it is not a door through which you may enter and change the things inside. This is because integrated libraries are solid once they re generated, there s no changing them. In fact, to update an integrated library really means to replace it altogether you must pull up the original library package, update the source documents, then recompile. If you have not changed the package name or output path, then the new integrated library will replace the old. This is all part of the plan. An integrated library is a purposely controlled environment, and so we force you to return to the source documents to make any changes. The alternative is an exercise in juggling, where symbols and models can be modified independently at any time, without giving you any warning that they will no longer match up until you go to generate a graph or update a board. Placing from an Integrated Library The Libraries panel contains a Place button. As this panel may contain assorted schematic, PCB and integrated libraries, you may use it in either the schematic or the PCB editor. Any components placed from an integrated library is branded with information that will help locate the integrated library it came from later on. So while a schematic library and an integrated library may contain the same component (with all the same model links), the placed components from each of these libraries will behave differently when their model information is retrieved. Those components placed from integrated libraries will go back home to get their models, while those components placed from schematic libraries will have no access to models stored in integrated libraries. 22-3

296 Enhanced Library Management using Integrated Libraries article Keeping Integrated Libraries Available Since integrated libraries are automatically added to the Libraries panel when they are created, and also because the Libraries panel is the only platform from which integrated components may be placed, the Libraries panel is the one and only place to be searched when integrated library model files are required. If you have uninstalled the source integrated library since placing, you will see errors in the Messages panel explaining which models couldn t be found. This restriction to look only in the source integrated library is a setting kept at the model level, and as such, it can be changed on a model-by-model basis. In conclusion, integrated libraries are a means of protecting the links between components and their models. Their components receive privileged status at model retrieval time, looking to the integrated library for associated models rather than embarking on a more general search. In addition, integrated libraries offer portability and protection. They don t just maintain links; they contain the model libraries themselves. An integrated library may be taken from one design station to another, letting you sidestep the confusion of having to change your search paths from location to location. And finally, should any damage occur to the original package, including any if its links becoming broken, then DXP will allow you to regenerate source documents from the integrated library. 22-4

297 Multi-channel design concepts article 23 Multi-channel design concepts Abstract Multi-Channel Design Concepts Multi-Channel Connectivity Channel Designations Room for PCB Designers Abstract This article introduces the true multi-channel design functionality introduced with DXP. It specifically discusses handling of common and distributed nets among channels, naming conventions, and PCB rooms and classes for each channel. Multi-channel Design Concepts DXP introduces a robust multi-channel design system that even supports channels nested within other channels. Many designs contain repeated circuitry. One board might duplicate the same section thirty-two times, or perhaps contain four identical banks with eight sub-channels each. Designers have long endured the difficulties of flattening such designs at the schematic level to correlate perfectly with the PCB layout. While the initial chore of copying-and-pasting schematic sections is relatively easy, correcting or updating the schematic project afterwards can quickly escalate into a heavy burden. DXP offers true multi-channel design, meaning that you can reference single sheets in your project repeatedly. Required changes need only be made once; recompiling the project then propagates the changes through each instantiation. And DXP not only supports multiple channels, it allows them to be nested. Consider the following schematic representation of a sixteen-button keypad. This design can be captured and wired up in DXP s schematic editor in just a couple of minutes. But suppose that you wanted to use a different symbol for the button? What if you wanted to add a parameter to each one? Or what if you wanted to expand the design from four by four to ten by twenty? Even with the help of group editing tools, these tasks are tedious and error-prone. Suppose, however, that you represented the entire circuit with just two 23-1

298 Multi-channel design concepts article components, one resistor and one switch, each on its own schematic page. A Repeat statement made within a sheet symbol instructs DXP s compiler to create virtual clones (channels) from a single sheet. The resistor page could refer to the same switch sheet four times to create a row, then a top page could refer to the resistor s page four times, making four rows. Multiple channels are nested within multiple channels, and the matrix of connectivity is established accordingly. Now the designer s tasks are made easy. Any modifications to the switches or resistors in this design would only need to be made once, instead of over and over again. Any expansion of the connection grid may be done by simply modifying the Repeat statements within the sheet symbols. Getting up to speed with multi-channel design means first learning how DXP establishes connectivity across such projects. Multi-Channel Connectivity Unlike other multi-sheet design projects, you have no choice when it comes to your Net Identifier scope; you must use the Hierarchical (sheet symbol <-> port) method. Leaving this setting at Automatic in the Project Options dialog will be fine, but it supposes that you understand that the only way to communicate signals to a repeated sheet is from sheet entries on the parent down to matching ports on the child. The reason for this restriction is that sheet entries, unlike ports or net labels, have been designed to handle the channel instantiations created through Repeat statements. There are two types of sheet-to-sheet connectivity available in multi-channel design: nets that are common to all channels, and nets that are unique to each. Both of these types are demonstrated in our keypad example above. The repeated switch in each row has one pin that connects directly to the resistor. This is a common net, meaning that the same node in each channel is tied to a single node on the parent sheet, and therefore to one another. Visually, it could be flattened like this: This is the simplest method of net distribution in DXP s multi-channel design. It is made intuitively by matching ports on the channel design with the sheet entries above. The other node on the switch, however, is not common on the switch level, but rather on the next level up (the row level). To convey unique connections up from multiple channels, a second Repeat statement is required, this time on the specific sheet entry. This picture demonstrates both types of connectivity Notice the difference between the two sheet entries. The first one (Res) matches the name of its corresponding port exactly, the other (COL) applies a Repeat

299 Multi-channel design concepts article command to its corresponding port s name. This allows four individual nets to be extracted from the four repeated sheets, first by a labeled wire, then by a labeled bus. At that point, the signals are free to be connected to separate nodes as necessary, or (as in this case), to be sent further up the hierarchical ladder through ports. Once you have built up your multi-channel project in accordance with DXP s connectivity structure, you may turn your attention to the way names are assigned to channels and their components. Channel Designations Channels are virtual sheets, and so DXP s synchronizer will infer a rooms from each channel, just as it would for any other sheet. Before it can do so, however, the compiler must generate unique names for all channels and for all of their constituent components. These names are driven through the Multi- Channel tab in the Project Options dialog, where an interactive diagram shows how your choices will affect component and room designations if you are using nested channels. Basically, you have two choices to make. The first is whether to use a flattened or a hierarchical naming convention for your rooms and components. (Hierarchical here refers to the hierarchy of channels, so this decision only matters if your design contains nested channels.) The second is whether the instantiation index should be numeric or alphabetic. (One option actually allows for both, but, once again, this only becomes apparent in the naming of nested channels.) The format you specify for your component designators may include the channel/room name you have stylized, but it doesn t have to. Usually, your designator format should include both a prefix and a suffix reference for both components and channels. Two of the seven reserved keywords do this automatically: $Component and $RoomName. $Component is the concatenated form of $ComponentPrefix $ComponentIndex. For example, a component part designated U3A consists of a prefix (U) and an index (3A). Similarly, $RoomName is also a concatenated form of a channel prefix and suffix, but its exact form will vary depending upon your design and the room naming style you have chosen. If your design does not include nested channels, then the hierarchical portion of the style is irrelevant, and only the numeric or alphabetic portion of the style will alter how $RoomName describes your channel notations. But if you do have nested channels in your design, and you use a hierarchical room naming style, $RoomName cannot simply be replaced by $ChannelPrefix and either $ChannelAlpha or $ChannelIndex. This is because it builds a special, multi-level prefix from the channel names used in the Repeat statements in your design. Suppose that, in our keyboard project, we had selected Numeric Name Path in the Room Naming Style, a comma for the Level Separator, and for the Designator Format we had simply 23-3

300 Multi-channel design concepts article written $RoomName. The sixteen instantiated buttons after compiling the design would be annotated like this: Had we chosen instead to use the Alpha Name Path, our designators would have been RowA,PBA; RowA,PBB, etc. Had we chosen the Mixed Name Path, they would have been RowA,PB1; RowA,PB2, and so on. But if we had chosen a flat alternative, the reference to the Row channel would be ignored, and the designators would simply range between PB1 and PB16, or PBA and PBP (numeric or alphabetic). Of course, it is not usual practice to leave out any reference to the component itself in the Designator Format field, and is only acceptable in this case because each channel contains just one component. You need not be overly concerned about your designators growing too long to fit on your PCB, as you will always have the option to display logical rather than physical designators across your board. With that impediment removed, you should make sure that the physical designators contain all the information you want in the format you want it. Room for PCB Designers Multi-channel design benefits everybody, not just schematic designers. The benefits to the PCB designer extend far beyond the initial grouping of channeled components into their respective rooms alongside the Board Outline. Powerful new room-based tools will be particularly appreciated during multi-channel design layout. DXP s Situs autorouter has a single-room setting, whereby it can route all connections wholly contained within a room. Conversely, the unrouting tool has a room option. Corresponding components in each channel are all assigned the same Channel Offset value, meaning that they may be targeted together for selection or group edits. More impressive than all these, however, is the ability to copy formatting from one room to another. This allows you to make changes to one room, then copy the room s formatting others. If the source and destination rooms belong to the same channel class (meaning that they were cloned from the same schematic strand), then the updates can be extended to all class members at once. What information you copy can be limited to the room s size and shape, or can be extended to footprint arrangement and even routing. Additional controls let you determine how far the routes previously present in such room will be ripped up. Numerous other tools have been added to the PCB editor which will allow board designers to get the most out of multi-channel design. While using the Move command in the Design» Rooms submenu, for instance, you may press the L key, which flips whatever is being moved to the opposite side of the board. You will find that the whole room, including relative placement and routing, remains intact after the move. The ultimate promise of multi-channel design is the same for the board designer as it is for the schematic engineer: you no longer have to spend your time do the same thing twice or thirty two times, for that matter. To learn more about the benefits of nested multi-channel design, study the PCB project in your Altium\Examples\Peak Detector folder. 23-4

301 Net Connectivity & Navigation article 24 Net Connectivity & Navigation Abstract Abstract Net Connectivity Multi-Sheet Design Hierarchical Considerations Flat vs. True Hierarchy Grouped Sheets Net Identification Scope Reference for Net Identifiers Navigation This article explains the different ways of establishing multi-sheet connectivity, and the different browsing tools that let you verify net connectivity within DXP. Net Connectivity The simplest unit of net connectivity in schematic capture is a wire placed between pins. Visually, you can see that the nodes are joined, and, once the schematic is compiled, you may browse from a specific net to each of the nodes it joins. The basic net identifier is a net label. One of its functions, not surprisingly, is to help you identify which net you re looking at. Certain project options will let you allow specific net identifiers to actually name nets, making it easier to recognize specific nets when you re navigating through the design or scrutinizing the generated netlist. But naming nets is just a sideshow for net identifiers. Their real magic is in the way that they can actually create connectivity across your design. This will happen whenever they are properly placed and matched to one another, creating the same connectivity you would get from a wire. In fact, using net identifiers instead of wires offers two advantages: it can alleviate the congestion of wires in busy areas of your circuit design, and it frees you to explore multi-sheet design. Multi-Sheet Design The need for different kinds of net identifiers is most evident in multi-sheet design. For example, if you were to tidy up a single design with net labels and perhaps a bus line showing where wires would 24-1

302 Net Connectivity & Navigation article normally transfer a series of signals between components, you would expect those signals to remain within the local sheet. In contrast, when you wanted to run signals to ground, you would probably want a net identifier that would work globally across all of the sheets in your project. Similarly, you would want to be able to place components with hidden pins that would always connect to the same power or ground nets, no matter what sheet they were placed on. There should never be any question about which net identifiers to use in DXP. You simply need to consider the scope of connectivity you want to create, and your particular arrangement of sheet symbols (hierarchy). The local sheet level is the narrowest scope of connectivity, and the whole project is the most expansive. As described, net labels are provided for the former, and power ports/hidden pins are provided for the latter. In between are an assortment of net identifiers for relaying signals between a specific subset of sheets within your project. Hierarchical Considerations All multi-sheet designs are hierarchical as far as the compiler is concerned. When your multi-sheet design is compiled, all sheets are arranged in the Navigator panel in a hierarchical tree. To prepare this hierarchy, you need all sub-sheets in your design referenced by a sheet symbol somewhere higher up the chain. The top sheet will be the only one in your whole project that is not represented by a sheet symbol. You are required to use sheet symbols for your multi-sheet project, but how you arrange them is up to you. How you proceed will probably depend upon your motives for exploring multi-sheet design in the first place. Perhaps your circuit simply grew too large to fit on a single sheet. Or maybe you have divided your project into logical blocks, each represented by a sheet or a group of sheets. Or you may be repeating certain sheets for a multi-channel design. A clear understanding of what you want to achieve in your multi-sheet design will help you decide how to arrange your sheet symbols. Flat vs. True Hierarchy While net labels are designed primarily for local sheet connectivity, ports are made for relaying signals between sheets. If you have created a flat hierarchy (no sheet entries in your design), then ports can connect with matching ports across your entire project, much the same way that power ports and hidden pins make global connections. 24-2

303 Net Connectivity & Navigation article But the optimal use of ports is in a true hierarchy, where each port on a sub-sheet will match a sheet entry on the sheet-symbol above. This is the same for single or bused signals. The result is a vertical connection from this schematic twig to its parent branch, which may be passed upwards again, or passed horizontally to other sheet symbols, then back down their branches. In effect, true hierarchy allows you to control precisely how far a signal will be carried in your multi-channel design. By the time a signal is delivered up to a sheet entry, net and bus names become arbitrary, and may be connected to other sheet entries or ports with different names. This allows project engineers to receive separate schematic sub-projects from different places, and connect them together without worrying about shorts caused by name overlaps. The final benefit of true hierarchy is that it allows multi-channel design, in which a single sheet is channeled by inserting a Repeat command in the sheet symbol s Designator field. Grouped Sheets As mentioned, logical divisions and Repeat functionality are not the only reasons that you may use multi-sheet design. When a logical branch of your design has simply outgrown the space available on a single sheet, you may be forced to divide it among two or more sheets. You want these sheets to behave as they were one, but net labels can t create this connectivity, halted by the local sheet s border control. A new net identifier has been introduced to handle this special case, to combine with new functionality for sheet symbols. In a single sheet symbol, you may reference multiple sheets in the Filename field, separating them with semicolons. Now, instead of net labels, place off-sheet connectors for those signals that must be carried between these grouped sheets. Off-sheet connectors will connect with matching off-sheet connectors, but only within those sheets grouped together on the parent sheet symbol. If only one sub-sheet is designated by a sheet symbol, then its off-sheet connectors will not connect to matching ones that may exist elsewhere in your project. Net Identification Scope By default, new PCB projects are set to automatically detect which net identification scope to apply, whether it be a truly hierarchical or a flat design. 24-3

304 Net Connectivity & Navigation article If there are any sheet entries present in your schematic project, the automatic detection will select the hierarchical scope described above. Net labels will always operate locally, as will any ports that do not have a matching sheet entry on the parent sheet symbol. This is to say ports and net labels on one sheet will not connect directly with matching net identifiers on other sheets. If your schematic project contains ports, but no sheet entries anywhere, then the automatic detection assumes that you want ports to connect globally, and leaves net labels to operate locally. Finally, if your schematic project is devoid of both sheet entries and ports, then net labels will automatically be elevated to global status. Notice that in the Project Options dialog, you may override the automatic settings and force a specific net identification scope across to your entire project, regardless of its contents. This also offers a scope where both net labels and ports will make global connections across your project, accommodating legacy designs prepared in this way. Off-sheet connectors will always operate the same way, regardless of the Net Identification Scope you select. Reference for Net Identifiers Sheet Entry Port Net label always connects vertically down to a port on the sheet referenced by the symbol. connects vertically if it is matched to a sheet entry on the parent sheet symbol and either the Hierarchical or Automatic scope is applied. It connects horizontally to all matching ports when either the Flat or Ports Global scope is applied. connects vertically if used in conjunction with ports and sheet symbols and either the Hierarchical or Automatic scope is applied. It connects horizontally to all matching net labels when the Flat scope is applied. Off-Sheet Connector Hidden Pin Power Port connects horizontally to matching off-sheet connectors, but is limited to sheets referenced within a single, sub-divided sheet symbol. connects horizontally to all hidden pins in your project that have a matching Connect To value. connects horizontally to all matching power ports across your entire project. 24-4

305 Net Connectivity & Navigation article Navigation You don t need to labor through netlists to see if you have achieved the connectivity you desired. When a project is compiled, the infrastructure of connectivity comes alive in DXP. Navigation tools let you physically follow nets through your schematic design, then over to your PCB document. The Navigator panel lets you view components and nets by individual sheets or hierarchical groups (use the flattened hierarchy to see all the components and nets in your design). The highlighting options you enable at the top of this panel will determine what happens when you click on individual design elements. The scope of objects that appear in the Navigator panel and the Browser can be configured in the Project Options dialog. The Browser, which corresponds with the Navigator panel, gives you a different perspective. It places you within the design, and describes the connections in your vicinity like a GPS map. If you have navigated to a component, the Browser will display this component name at its center. Above you will see the nets connecting to this component, and below you will see the pins within it. Now you may step in any direction, and the Browser will change its focus to the new location, and give new options. If you choose a net, then you will have a list of all connected components above you, and all connected pins below. If a connected element appears in grey, it simply means that it exists on a different sheet in your design. You can still browse to it by clicking, just like same-sheet connections. Initially, this first-person navigating may cause you to feel a little disoriented. Navigation history (forward and back) buttons will let you retrace your steps through your design, while clicking on the Navigate button will let you select a new point of reference. Additionally, you will the Shift key will help you keep your bearings. Try holding it down while you click on an object in the Browser. The schematic design will highlight the new object as usual (according to the navigation options), but the Browser does not move its focus to that object. It remains centered on the original object. This is analogous to standing at a crossroads, and peering down the different roads you might take without committing to them with your feet. If you have already implemented your schematic project in a PCB design, you may also use these navigation panels for cross-probing. First make sure that your schematic and layout documents are visible, then hold down the Alt key as you click on elements listed in the Navigator panel or the Browser. Both schematic and PCB documents will respond to the highlighting options specified in the Navigator panel. 24-5

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307 Working with Simulation Waveforms article 25 Working with Simulation Waveforms Abstract Simulation Waveforms Chart and Plots Resizing the Waveforms Editing Plots and Waveforms Display Options Measurement Cursors Default Settings Abstract This article describes how simulation charts and plots may be arranged and manipulated in DXP. Simulation Waveforms The simulator displays simulation data and waveforms using a multi-tabbed Waveform analysis window, through which you can quickly and easily analyze the simulation results. When you run a simulation, the status bar at the base of the screen displays the progress as the circuit is first netlisted, then the netlist is passed to the simulation engine. If the circuit simulates successfully, you will have a variety of options as to how you will display the waveform results. Chart and Plots A chart is created for each type of simulation specified in the Analysis Setup dialog. Each chart is indicated and activated by a tab at the base of the SimView window. A chart may hold any number of waveform-containing graphs, called plots. While plots may differ in their Y-axis range of values or even units all plots within a chart will share the same X-axis. If a chart shows three plots, for instance, and the user zooms in to a portion of one plot, the other two plots will keep their previous Y- axis view, but their X-axis will change to will reflect the same scale as the magnified plot. This scale 25-1

308 Working with Simulation Waveforms article may be linear or logarithmic (base two or ten). A plot may be arranged in many ways. Any number of waveforms may be combined in a single plot, and any number of plots may be added to a chart. When you view these plots all at once, however, the Y-axis cannot be rescaled, and will not display any minor gridlines. This view is usually considered to be a draft mode, a zone where waveforms can be overviewed and rearranged. When you are ready to make detailed analyses of the waveforms, you should move from viewing all plots to a specific number of them (between one and four). The screen will then fill with as many plots as you have indicated, assuming you have created at least that many. If you have created more, you may still scroll up or down through additional plots. In this more detailed view, the Y-axis for a plot may be resized as readily as the X-axis. Additional Y- axes, if they have been applied for specific waveforms, will also be displayed in this view. This feature is particularly useful if you are contrasting different types of values, for example, current and voltage, upon a single plot. Resizing the Waveforms The waveforms are automatically scaled when they are first displayed. In the Y direction all the waveforms are scaled by the same amount, such that all the waveforms are visible, and the largest waveform almost fills the window. The X direction will be scaled according to setting for that type of analysis. For example, the total range of the X-axis in a Transient Analysis chart is defined by Start Time Stop Time. Resizing the X-axis can be done by either dragging the mouse over a section of the current graph, or more precisely by altering values in the Chart Options. You should note that resizing the X-axis applies to the entire chart, rather than individual plots within the chart. This is because each plot in a chart must be displayed along identical X-axes. Waveforms may be refreshed within a chart simply by choosing Fit Waveforms, available in the right-click menu. The Y-axis for any plot may be resized by dragging the mouse over a section of the plot, or more precisely by altering values in the Plot Options. Resizing the Y-axis for any individual plot will not affect any other plots on the same chart. Editing Plots and Waveforms When you first simulate a circuit, each active waveform is assigned its own plot. Drag the waveform s name to any other visible plot, and that waveform will join whatever waveforms were in that plot already. As both the source plot and target plot must be visible when dragging and dropping, displaying all plots within a chart is the most reliable view for rearranging waveforms. The same signal may be viewed in a multiple ways. The same AC signal, for example, may be displayed both in Db and in degrees (showing phase). These variations can be displayed on the same plot (with individual Y-axes, should you desire), or on separate plots. 25-2

309 Working with Simulation Waveforms article As part of the analysis of your design you may want to perform a mathematical operation on one or more of the simulation signals, and view the resultant waveform. This feature is an integral part of the simulator s waveform viewer, you can construct a mathematical expression based on any signal available in the simulated circuit. In the Transient Analysis, for example, over thirty mainly trigonometric operations are available. These may be combined in a complex expression, and assigned a name with which the resulting waveform will be referenced in the plot. Display Options If you are unsure about the accuracy of the waveforms perhaps they look sharp and jagged instead of smooth and curved you can turn on the simulation data points to check if the results have been calculated often enough. Should you need to identify separate waveforms on a single color printout, you may enable designation symbols along each wave. The first waveform in any plot will be represented with squares; a different symbol will be assigned to each additional wave. In this example, two waves with different Y-axis scales are overlaid. This functionality lets you compare attributes shared along the X-axis, which will always remain the same for all plots within a chart. It is not required that you display each Y-axis separately. Measurement Cursors Two measurement cursors let you take measurements directly from the waveforms. 25-3

310 Working with Simulation Waveforms article To add a cursor for a particular wave, you must first select that wave within a plot (if the plot contains multiple waveforms). This is done by clicking upon the wave s name alongside the plot. Right-clicking on that name offers a shortcut to measurement cursors, as opposed to using the Wave menu. You take measurements of time and amplitude from the transient analysis results, or find the frequency of the 3dB point from the AC small signal analysis results. You can use the two cursors together to take difference measurements from two points on the same waveform, or two points on different waveforms. Measurement functions are available in the SimData panel, where results are immediately displayed. Default Settings When you close the Simulation Data File (.SDF), the setup information is saved with the file. By default the display setup is retained, so that you can re-open a simulation data file and the results will be as you left them. If you re-run the simulation and you want it to display the Analyses and nodes that you have just setup, change the SimView Setup from Keep last setup, to Show active signals. You may, in turn, apply your current display settings to become the default for future simulations. 25-4

311 Design Updates & ECOs article 26 Design Updates & ECOs Abstract Design Updates and ECOs Annotate Parameter Manager Update from Library Update from Database Schematic PCB Update Abstract This article describes the Engineering Change Order(ECO) process in DXP. This process is invoked at critical stages of design updates, and allows heightened controls and reporting tools. These stages are schematic annotation, parameter management, updates from libraries, database linking and schematic- PCB synchronization, each of which are reviewed in some detail. Design Updates and ECOs There are different levels of design changes. The most basic level is by direct editing. Higher up is editing a group of selected objects all together. The highest level is updating one cohesive data set with another. The update tools offered in DXP give you precise control in administering these updates, allowing you all the control and documentation you need to drive the appropriate set of changes, and, if necessary, retrace your steps later on. Updates are executed through an Engineering Change Order dialog. This shows you the entire list of proposed changes. This list cannot be modified, so if you see anything proposed changes that should not be there, you will need to close the dialog before executing anything. Then you can revise your preliminary steps, making sure that your list of changes will be complete and accurate. In the ECO dialog, you can validate changes before you make them. If any of the changes you propose fail validation, corresponding flags will appear in the Messages panel. This is another time that you may step out of the update sequence to make sure that your changes will occur as you expect. Also, the ECO dialog allows you to print and/or save a report documenting the changes. This will not include information about changes that could not be executed, so you should wait until you can see that all your changes are valid before generating the report. 26-1

312 Design Updates & ECOs article There are five times that you will encounter the ECO dialog: when you are re-annotating your schematic project; using the Parameter Manager; or updating from Libraries, Databases, or between schematic and PCB documents. Annotate The Annotation dialog allows you to determine: which project documents to update how component families will be placed in order a starting index, if desired, for all component sets on a sheet a suffix, if desired, for all components on a sheet You are shown two columns: current and proposed annotations for each component. These will be identical to start with, until you update the list with the pattern and/or matching configuration of your choice. But the only changes that will take place are those components waiting in an un-designated, but ready, state. That means their designator currently ends with a question mark. If, on the other hand, you want to entirely reannotate one or more sheets, you must first reset the current annotation, then apply the new patterns and other settings that you have made in this dialog. Notice, however, that no changes are made in your design itself until you move into the ECO dialog, and execute the changes. This is the bottom-line truth for all of these update sequences: if you leave the dialogs without proceeding through the ECO and executing changes, your design documents will remain unmodified. Parameter Manager A Parameter Manager has been put into place to let you view and edit groups of parameters across your project at once. This dialog will display each parameter in a dedicated columns, with parameterowning objects each in their own row. To prevent this dialog from becoming unwieldy, you should narrow the Parameter Manager s scope from the whole project to the specific subset you really wish to manage. When you invoke this dialog, you are first presented with a series of options that will help you weed out irrelevant parameters. If, for instance, your goal is to simply add Manufacturing Numbers to all of your schematic components, you could exclude system parameters, and all owners besides parts (the six other entities that can own parameters are schematic sheets, sheet symbols, ports, pins, nets and models). You could also exclude specific sheets or components from the Parameter Manager. Once the Parameter Manager generates a table of owners and parameter names, you can see three types boxes within this matrix. Either they will contain data, appear completely blank, or have a generic hatching pattern. Data in a field means that the parameter (column) is owned by the object (row), and that it contains a value (data). Blank means that it is owned, but its value field is empty. Hatching means that no such parameter has been added to the object. 26-2

313 Design Updates & ECOs article If a parameter exists for an object (the field is empty or contains data), then you may edit its value directly, either by typing a new value, or selecting from a drop-down list any of the values already entered somewhere in this column. This is not the case for parameters which an object doesn t have yet (the field is hatched). These must be accessed more deliberately, which can be done through the right-click menu. This will let you add an existing parameter to new objects of your choice. A new parameter may be added (Add Column), and its value may be assigned and applied to all displayed objects at once. Similarly, a parameter may be deleted across all displayed objects. Group edits operate in a similar way to the List panel: select the objects using the Shift or Control keys, then right-click on a specific field to have the edits you make apply to the whole selection. To help you monitor what changes have been made, altered fields will carry a temporary badge while in this dialog. Deleted parameters will receive a red mark, newly added parameters get a green one, and modified parameter values get a blue one. The right-click menu will also let you revert a field s state to what it was before. Still, like all dialogs described in this article, none of the changes you make here become effective until you execute them in the ECO. Update from Library Schematics may be updated from libraries. On a component-by-component basis, this may be done from the schematic library editor, but this will only update components in Open or Hidden (compiled but not open) documents. Also, it will not offer any controls for parameter or model differences; a full replace of all graphics, parameter, and model attributes will occur. For precise control between library documents and project sheets, use the Update from Library dialog. This dialog lets you determine: which project documents to update which specific components, indicated by name or selection status, whether updates should include graphics, parameters, or models By default, all documents are chosen, along with all components, with instructions to fully replace the symbols on your design sheets with those from the corresponding library. If you de-select this final option, however, you can further control how both parameters and models will be handled. How would you want the update to behave, for example, if a component parameter had a certain value in the sheet, but a different value in the library? Or what if the library s value was blank? These, and similar controls for model updates, can all be manipulated for the entire group of changes. If you know that this will update the design how you want it, you jump directly into the ECO, where you may review, validate and execute the resultant changes. If not, you can step forward in this multi-step dialog. You Every parameter has an option to be excluded when updating from libraries or databases. will see all the affected components listed, and you can make the same decisions about graphics, parameters and models on a component-by-component basis. In fact, you can more precisely edit the parameter and model updates that will occur beyond the basic paradigm you have set. So while the 26-3

314 Design Updates & ECOs article overall settings are the rule, you can make exceptions on a case-by-case basis. You will notice that the controls here correspond with those available in the Parameter Manager, and have the same group editing features. Update from Database Like library updates, you may prepare default settings for adding, changing and removing parameters from your schematic documents, then override those defaults for particular instances. Any ODBC-compliant database can be accessed for tabular information for parameter or field updates. You will need to create a new Database Link file within DXP, and configure it to connect to your database file. Once connected, the database link document will have two tabs available: Table Links and Database Links. The Table Links is simply a display of field values within DXP, where the displayed list may be filtered, but the actual values may not be edited. The whole idea is that any changes are to take place within the database, then be propagated through your schematic designs. The Database Links view lets you correlate the table headings in your database with the parameters in your design project. You must select one key pair that will be different from all the rest. The values in these fields will not be used for updates, but rather for matching the table rows in your database with parameter-owning objects in your design. Additional controls allow you to indicate what data to transfer and when. For example, you may want to always update the values of a specific parameter, as long as the value in the database is not blank. Similarly, you may wish to remove a parameter from your design if it is not found or its value is blank in the database. Schematic PCB Update The Ctrl+D shortcut allows you to set entire rows to the default settings, as defined in the Database Options dialog. Synchronization between schematic project documents and the implementation PCB offers some tools that are not available in other update sequences. It has two dedicated tabs in the Project Options dialog, one letting you customize the types of differences you want to detect, and another letting you decide which detected differences you want to figure into the ECO. The changes you make here allow you to ignore irrelevant differences for the long term in your project. Notice that if you jump straight to the ECO dialog by using the Update PCB from the schematic editor, or the Update Schematics or Import from Schematic commands in the PCB editor, you will be taken directly to the ECO dialog. There will be no preliminary dialogs like those described for other update processes allowing you to narrow the scope for your ECO. This is simply a shortcut to the ECO dialog, whenever you are sure you want to execute a change for each difference as you have set them up to be detected and carried out in the Project Options dialog. If, however, you want to review a list of proposed changes, and choose which ones you want to update (and perhaps which direction you want to send each update), you need to open the Differences dialog. When you invoke the Show Differences command (Project menu), you are first shown the documents 26-4

315 Design Updates & ECOs article you wish to compare. By default, this is the first PCB document in your project with the project schematics, but an Advanced mode will let you choose more specific comparison/update scenarios. In fact, you will notice that you re not constrained to compare a schematic set with an implementation PCB. You would use this feature, for example, whenever you need to build PCB from a netlist rather than a schematic project. Before comparing documents, DXP scans your project designs for linked components. These are components that have been previously synchronized with one another and share a UID (unique identifier). If components have not yet been synchronized between documents, a dialog will allow you to match components up either automatically by designator or by hand. If no components exist in the target document, as in the case of a blank PCB you wish to update with components, nets and parameters specified in a schematic design, then the matching step will be skipped, and corresponding UID's will be assigned to each synchronized component when you execute the updates. But even if differences are detected, you are under no obligation to include them in the ECO. When the Differences dialog is generated, No Change is the default action assigned to each entry. DXP will only synchronize the elements you specify. If you wish to sweep all changes one way or another, simply right-click anywhere in this dialog and choose the flattened project or the PCB as the recipient of all changes. Otherwise, click in the Update column for individual changes, and specify the target for that change. It is particularly important to validate these Schematic PCB updates before executing them. Not only will the logic of your proposed changes be tested, but libraries will be searched to ensure that the models are available, even to the point of checking pin-to-pad matching. As in any other ECO dialog, you should check the Messages panel to see why any changes failed verification, then delay executing the ECO until all your everything checks out. 26-5

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317 Introduction to the Query Language article 27 Introduction to the Query Language Abstract Query Overview Sample Queries Building Tools Query Helper Abstract This article introduces the query language, and points readers to the resources within DXP for understanding it. These resources include example queries in the History and Filter pop-up lists, generation tools such as the Query Builder, and the On-line help provided in the Query Helper. Query Overview Queries allow you to target specific objects within DXP s major design editors. A query is a command line that you string together using specific keywords and syntax, which will return a set of objects. What you want to do with those objects is up to you. Maybe you want to zoom in on them. Maybe you want to highlight them, dimming out all other objects. Maybe you want to browse or sort their properties, or even modify specific attributes that they all share. Or maybe you want to apply a rule that will apply only to them. All of these applications are available, but everything hinges upon your query being correct. There are a few places where you can apply your queries, but the command central is in the List panel. It offers you the ability to select the set of objects you want, zoom to them and/or highlight them by masking what remains. But most importantly, it shows you the entire set of filtered objects in a spreadsheet format. This spreadsheet is a sophisticated design tool in itself; with controls for sorting, editing or stepping from the current filter up to parent objects. But the most instructive benefit of the spreadsheet is to show you whether your query has targeted the correct set of objects. So how can you learn to write queries? The best coaching, of course, is based upon practice. Your preliminary efforts will include trial, error and some 27-1

318 Introduction to the Query Language article frustration. At the same time, DXP contains valuable resources for learning the query language. The first is a set of sample queries that are provided upon installation. The second is a group of tools that generate queries based on your input. The final (and ultimate) source in learning the query language is the online help accessible through the Query Helper. Sample Queries Each design editor comes with a set of pre-packaged queries. Ultimately, these have been provided as bookmarks which you will eventually replace with your own queries, but in the meantime they offer good case studies. A filter history list is available through the List panel. Every time you apply a query (correct or not), it is added at the top of this list. So before this list gets overloaded with your own attempts, you should review the sample queries that have been provided upon installation. Try them out on example documents to see how they filter a subset of objects from the entire group. Other prepared queries are found in the Filter popup menu. Press the Y shortcut key to view this list directly from the workspace. The actual query behind each of these commands is not immediately accessible; you will notice that clicking on any of the commands in this submenu will proceed to apply the query without ever showing it to you. But if you first open the Customize dialog, then double-click on one of these commands, you can pick through the Parameter field for the query, which will be preceded by Expr=. You should learn this parameter syntax eventually, because this is the way to hard-wire your favorite queries to menu shortcuts. Pressing Y4 is much easier than digging through the filter history list for one of the queries you use on a regular basis. Building Tools Several tools in DXP will build queries for you. The simplest one is in the PCB editor s Filter toolbar, which has thee editable fields. On the left is a drop-down listing all the nets on your board. Next is a similar drop-down for components. Finally comes a field for your query. Notice that if you select a net or a component from one of the two drop-down lists, this third field will automatically generate an appropriate query, such as InNet('CLK') or InComponent('C2'). This, of course, is a very limited form of query-building. More complex queries can be built in the Matching section of individual design rules. First, you decide if you want to apply the rule to a specific net, net class, layer, or net and layer combination. Once you have made this choice, corresponding drop-downs are made available on the left side, while a query to the same effect is created on the right. Much more powerful tools are the Find Similar Objects dialog, and the Query Builder. In fact, you may end up using these tools all the time rather than writing queries free-hand. 27-2

319 Introduction to the Query Language article The Find Similar Objects dialog appears when you right-click on any unmasked object in your design document. This will invoke memories of previous Protel versions for users who have come by that route (it was actually incorporated into DXP at their request). It allows you filter out a group of objects based on one object. Suppose for example, you wanted to change all GND pads in your design. You could right-clicking on one such pad, choose Find Similar, then change the Net field from Any (the default setting) to Same. All of the GND pads will be selected when you Apply from this dialog, if the Select Matching option is enabled then you can proceed to the Inspector or the List panel s spreadsheet to make the change across the selection. Notice, however, the Create Expression option in this dialog. Leave this checked, and the List panel will show that the query (ObjectKind = 'Pad') And (Net = 'GND') has been applied. As all attributes of the original object are displayed in the Find Similar Objects dialog, each with the option to be ignored (Any), or to be used as a matching (Same) or an antimatching (Different) attribute for the set you want to target, this query can become rather complex. Even the Object Kind attribute can be set to Any or Different, meaning that your target set is not constrained to objects of the same type something that has never been available before. The Query Builder is another interactive tool for generating queries. It populates dropdown lists with operators and the available condition values based upon your specific board. Best of all, the operators are presented in English, rather than query language. Because the actual query is being built before your eyes, you can study how the familiar descriptions correlate with the query syntax. The query is displayed in a hierarchical fashion. Brackets are inserted automatically when you indent a section of code within the hierarchy, freeing you from the chore of counting parentheses while developing your query. Single or grouped lines of code may be moved up or down, left or right within the hierarchical structure. The Query Builder may If you launch the Query Builder by right-clicking on a board object, it will work very much like the Find Similar Objects dialog, limiting its drop-down options to the attributes of the object you clicked on. Similarly, launching it from a design rule will limit its contents to applicable conditions for that rule. be launched from the List panel, design rules, View menu, right-click menu, or with the Shift+B keyboard shortcut. The Query Builder also has an option to create an expression, meaning that the finished query can be transferred to the List panel and its History list. 27-3

320 Introduction to the Query Language article Query Helper Engineers who want to master the query language will eventually learn more from the Query Helper than any other resource. It contains all available keywords, including the names of the specific objects placed in your active design document. But most importantly, it is the conduit for online help descriptions of every single query command, which provide details and examples. Browse through the different categories of available commands for the one you want. Use the Mask field if you re not sure what the precise keyword is. For example, in the schematic editor s Query Helper, entering *para* in the Mask field will show you the dozen or so commands that apply to parameters specifically, while *par* will pick up commands for both parameters and parts. Pressing F1 when highlighting a keyword in any category (or when the cursor is on a keyword you have typed in the Query Helper, will bring up an online help description for that command. This is the most valuable resource for learning the nuts and bolts of the query language. Here you will learn the nuances, such as commands that will return children objects, parent objects or both. For example, the keywords Component and InComponent differ not only in the syntax of arguments, but also in what objects they actually return; Component returns the primitives that make up the component (child objects), while InComponent returns both the primitives and the component (parent) object itself. Subtle differences like these are revealed in the online help, which is the where the Query Helper really earns its name. Queries may seem intimidating at first glance, but don t shy away from them. There has never been a more powerful or flexible tool for browsing through specific elements of your design, or for defining rule scopes. Use the samples, wizards and help files until writing your own queries becomes simple, because properly applied queries will simplify your work. 27-4

321 An Insider s Guide to the Query Language article 28 An Insider s Guide to the Query Language Introduction and Overview of queries Queries their nature and purpose Data Filtering facilitating file editing tasks Data Views and Highlighting What is displayed, and How The List Panel another data view The Inspector Panel property viewing and editing tool Masking - another highlighting option Applications of Queries (Queries in context) Finding, Presenting and Editing Objects Applying Queries Query Options Finding Similar Objects facilitating global object editing The Query Builder feature automating query generation The Query Helper Dialog support for designer-specified queries Design Rules in PCB Files Applying Queries from Resources Inside the Query Language Nature of Queries Queries using Multiple Keywords Finding Objects with particular Properties Finding Objects with calculated properties Hierarchical aspects Tricks of the Trade How to comment a query Where to now? Appendix: Examples of Useful Queries Queries to use with PCB files Queries to use with Schematic files Introduction and Overview of queries This article has been provided to de-mystify what queries are, how and why they are used, and to provide insights into how these can be specified to accomplish particular objectives. Queries can be used with Schematic Library, Schematic (document), PCB Library, and PCB (document) files; for the remainder of this article, any reference to a file refers to any of those particular types of files (unless specifically stated otherwise). 28-1

322 An Insider s Guide to the Query Language article Queries their nature and purpose In a nutshell, queries are primarily used to determine whether each object within a file is subsequently highlighted or otherwise. The thus highlighted objects are normally displayed in a manner which is distinctive in comparison with the remaining (non-highlighted) objects, which are either displayed in a less prominent manner, or else are not even displayed at all. However, although queries can be used specifically to control how a file s objects are subsequently displayed, that is not the limit of their usefulness. They can be used to determine whether any objects within a file have particular properties (or particular sets of properties), and to assist in actually locating such objects. And another very important reason for using queries is to qualify which objects have their properties modified during succeeding commands, including in particular during global editing commands. Which objects within a file are subsequently highlighted following the application of a query are determined by that query s contents, and that in turn is controlled by the designer. The designer also determines whether each of the Zoom, Select, and Mask highlighting options (described in more detail later) are selected with each query, which in turn determine the subsequent selected and masked states of each object, and how the highlighted objects and non-highlighted objects are actually subsequently displayed. Queries can be applied by various means, including from Find Similar Objects or Building Query dialogs, or from the List Panel, or from the Filter Toolbar (in the case of PCB files), or from resources (menu entries or toolbar buttons or shortcut keys). There are various ways to control the contents of a query, which consists of a string that always contains at least one recognizable keyword. Designers can directly specify that string themselves, and that method is especially recommended for all those wanting to learn how to specify their own queries. A query s contents can alternatively be selected from lists of favorite or previously used queries, or automatically generated, or pre-determined. Queries are also used for two special purposes within PCB files: they specify which objects are subject to each Design Rule that is defined, and they specify the Impedance Formulae that are to be used whenever the Characteristic Impedance Driven option is selected for any (Max-Min) Width (Design) Rule. Before queries are described in more detail, brief descriptions are provided of data filtering, data views and the associated List Panel, and of highlighting options and the associated Masking feature; these aspects all figure prominently whenever queries are used. Data Filtering facilitating file editing tasks A typical file contains a considerable number of objects, so to facilitate their tasks, designers are provided with the ability to display each of those objects in more than one manner, and a considerable degree of control over which objects are currently even displayed at all. And because some commands change the properties of multiple objects, designers are also provided with the ability to control which objects do have their properties modified at the time. 28-2

323 An Insider s Guide to the Query Language article This capability to display and modify objects on a selective basis is implemented by a sophisticated data filtering feature. Whenever it is used, the properties of each object in the target file are evaluated, and those objects having properties which comply with the specifications of the filtering operation become members of that filtering operation s result set. The combination of which highlight options were also specified for the filtering operation concerned, and whether each object is a member of that result set or otherwise, determines the subsequent selected and masked properties of each object, and the manner in which it is subsequently displayed. As one example, invoking a Zoom command then invokes the data filtering feature, producing an outcome in which the file s objects are displayed on the screen on a selective basis. The associated result set consists of those objects which are located within the updated region being displayed, and the data filtering feature causes those objects to then be displayed. Conversely, the objects which are located outside the updated region being displayed are not in the result set, and the data filtering feature causes those objects to not then be displayed 1. Another example is that invoking any command which changes the selected state of one or more objects within a file also invokes the data filtering feature, producing a result set of the now currently selected objects. Selected objects and unselected objects are displayed in different manners, so the data filtering feature also controls how each object is subsequently displayed. And when any command is invoked which is to be applied to the currently selected objects, the data filtering feature also controls whether each object has that command applied to it or otherwise. In yet another example, the data filtering feature is also used in conjunction with the newly provided masking feature (described in detail in other parts of this article). It controls how unmasked objects and masked objects are each displayed, and whether various types of commands are applied to each object within a file. The significance of queries is that the data filtering feature is also invoked whenever a query is applied. The contents of the query determine which objects within the target file become members of the associated result set, and the highlight options which were selected at the time determine the subsequent states of each object s selected and masked properties, and the manner in which each object is subsequently displayed. It is precisely this ability to specify the highlight options, and to control (with a fine degree of precision) the data filtering feature s result set, that makes queries so useful to designers. Data Views and Highlighting What is displayed and how To fully appreciate how to specify and apply queries, it is necessary to understand the concepts of the distinct data views which are now provided, and of the highlighting options which are available when queries (and other types of filtering commands) are applied. In a nutshell though, what is displayed is determined by the data view, and how different objects are displayed within each data view is 1 Even when all of the file s objects are displayed following a Zoom command, the data filtering feature has still been invoked: the associated result set then consists of all of those objects. 28-3

324 An Insider s Guide to the Query Language article determined by the available highlighting options. Each of these is described in the following subsections. Graphical View and List View two distinct Data Views During the course of designing a file, it acquires a number of objects, and of assorted types. Traditionally, a graphical view has been provided to display those objects, in which the properties of these objects are displayed in a spatial and visual manner. However, the provision of a list view now provides designers with an alternative way of viewing those objects, in which their properties are displayed in a tabular manner instead. Each row within this data view s array displays the properties of one object, and each column displays the value of one particular type of property (as indicated by the top-most Title row) for each of the currently listed objects. It is possible to control which properties (columns) are currently displayed and the sequence in which they are listed; it is also possible to sort the sequence in which the objects (rows) are listed, as determined by the values of one, or more, of their properties. As is also the case within the graphical view, selected objects are displayed in a distinctive manner relative to unselected objects, and the selected state of each object can similarly also be changed from the list view. And double-clicking on an object similarly invokes a dialog box that lists that object s properties; in general though, there is little merit in doing that, because for most types of objects, all of their properties are not just listed in the data view, but are also capable of being edited from there as well. The provision of the list view means that two distinct types of data views are now available for viewing the properties of a file s integral objects. Each type of data view displays those objects properties in different ways, but it is important to appreciate that they are both displaying the properties of the same objects. Thus any changes which are made to any object s properties from either of the data views always results in corresponding changes in how the object is displayed in the other data view. One example is an object s selected property: an unselected object is displayed as such in both data views, and a selected object is similarly displayed as such in both data views. And if the selected state of an object is toggled from either of those data views, then the updated state is displayed as such not just in that data view, but in the other data view as well. The list view is contained within the newly provided List Panel, which is capable of being re-sized and re-positioned to match the designer s personal preferences; with the default set of resources, the F12 key toggles its visible state. As described later, this Panel also incorporates various controls associated with queries; amongst other capabilities, the designer can specify and apply a query, and select the highlighting options to be used when a query is applied. Zoom, Select, and Mask three distinct Highlighting options Whenever a query is applied (or the data filtering feature is otherwise used), each object within the target file becomes a member of that filtering action s result set when so appropriate. However, how the objects in the result set, and the objects which are not in the result set, are subsequently displayed 28-4

325 An Insider s Guide to the Query Language article depends upon the Highlighting option(s) selected at the time. And in that regard, three different highlighting options are available, as described: Zoom When this option is selected, the graphical view of the target file is updated, with the updated view displaying the region occupied by all of the objects which are members of the result set. Zoom commands change the graphical view of files in a similar fashion, hence the designation for this particular option. Whether or not each remaining object is displayed in the thus updated view depends upon its location relative to that region, so each of those objects can end up being totally displayed, or partially displayed, or not even displayed at all. This option has been provided primarily for updating the target file s graphical view, which displays spatial properties and relationships in an obvious manner. But it would be incorrect to state that it has no impact upon the target file s list view; depending upon the circumstances at the time, there can also be changes to the set of objects which subsequently have their properties displayed in the list view, and which of those objects are selected. That said, it is still unlikely that any designer would select the Zoom option solely for its impact upon the target file s list view. Select When this option is selected, all of the objects which are members of the result set acquire a (true) selected state, while all of the remaining objects acquire an unselected (or false selected) state. Selected objects are displayed in a more distinctive manner than unselected objects in both the graphical view and list view, so both of those views are updated accordingly. Mask This highlighting option, which has been newly provided, determines the updated masked property of objects in the target file. When selected, all of the objects which are members of the result set acquire an unmasked (or false masked) state, while all of the remaining objects acquire a (true) masked state. The masking feature is described in more detail later, but in a nutshell, unmasked objects are displayed in an unqualified form in both the graphical view and list view. On the other hand, masked objects are displayed in a dimmed form in the list view, and are not displayed at all in the list view. The other significant aspect of masked objects is that they are not capable of being edited, or of having any of their other properties changed. Which options can be selected are totally independent of one another, so any one of those three options can be selected, or any two of them, or all three of them. (It is not impossible to alternatively select none of those options, but there would be no point in doing so, as there would be no difference between how highlighted objects and non-highlighted objects were subsequently displayed.) The purpose of applying a query determines which highlighting options should be selected with it. 28-5

326 An Insider s Guide to the Query Language article The List Panel another data view The List Panel is of particular interest as far as queries are concerned, as these can be specified and applied from this Panel. And depending upon the highlighting options (and Clear Existing option) specified at the time, the application of a query also determines which objects within a file are subsequently listed (or listed and selected) in this Panel. As previously described, this Panel incorporates the file s list view, which lists the properties of all of the file s (currently unmasked) objects in a tabular format. The list view and graphical view both display properties of the same objects, but in different forms, so while some tasks can be undertaken from either view, other tasks are better undertaken from one of these views. One example of a task that is better undertaken from the graphical view is moving one or more objects; it is easy to see where those objects are being moved to, relative to all of the other objects. And one example of a task that is better undertaken from the list view is inspecting or editing the properties of objects which are currently not displayed in the graphical view, such as currently hidden parameters in Schematic files. The List Panel incorporates the file s list view, and can thus be used to view and edit the properties of the file s objects; it can also be used to specify and apply queries. Zoom commands typically change which region of a file s graphical view is currently displayed. Those commands are not applicable to the file s list view, but the designer instead has the ability to control 28-6

327 An Insider s Guide to the Query Language article the sequence in which the objects are listed in the list view; these can be sorted by the values of one, or more, of their properties. And by applying queries while the Mask highlighting option is selected, the designer can control exactly which objects are listed in the list view. Those aspects of the list view lend themselves admirably to tasks of a searching nature. By specifying an appropriate query, the list view can thus be used to determine if there are any objects in the file having a particular property, or combination of properties. A relatively elementary example is determining if a file contains any Designator or Comment (Text) strings which are currently in a hidden state. Another important aspect of the List Panel is that (like the Inspector Panel) it supports global editing, in which the values of a particular type of property of all the currently selected objects are updated simultaneously 2. The List Panel does not provide the only way of specifying and applying queries, but it is still very useful for designers who want to learn how to specify these, as the list view provides instant feedback on the outcomes of applying various queries. And for assorted tasks, the information of interest at the time of applying a query is to be found within the list view. Clicking on the Clear button (near the top of this Panel) effectively clears or resets the target file; all of the objects within this subsequently acquire both an unselected and unmasked state. It is very useful to do this whenever the designer wants the list view to display the properties of all of the file s objects. For those who are totally new to specifying their own queries, but who want to learn how to do so, the Builder button should be clicked on, to invoke the Query Helper feature. The left hand section in the resulting Building Query dialog contains controls, whose purpose is to assist the designer in the task of specifying what properties are required for each of the file s objects to be returned by the query generated by this dialog. As each of those conditions are specified or edited, the contents of the corresponding query are updated and displayed in the dialog s right hand section. If this dialog is then closed by clicking on its OK button, those contents will then be copied back to the List Panel. That query can then be applied by clicking on the Apply button within this Panel, but that should be done only after specifying the Highlighting options wanted, for which corresponding checkbox controls have also been provided. (The additionally provided Clear Existing checkbox should be left in a checked state until after some understanding of how to use queries has been acquired.) After some understanding of how to specify queries has been acquired, the Helper button within the List Panel should then be clicked on, to invoke the Query Helper dialog. The designer is then fully responsible for specifying the contents of a query, but this dialog still provides comprehensive assistance, as it incorporates a Syntax-checking feature and a complete list of valid keywords (for the type of currently focused file); comprehensive on-line help can also be accessed, by pressing the F1 2 Important Note: The selection state property is the only property which now determines whether each object within a file has some other property updated during global editing procedures; unlike in previous versions of Protel, it is no longer possible to use the current values of other properties to specify which objects are to have their properties updated during global editing procedures. 28-7

328 An Insider s Guide to the Query Language article key while one of these keywords is highlighted. And (like the Building Query dialog) if this dialog is closed by clicking on its OK button, the contents of the query are then copied back to the List Panel. The List Panel also contains History and Favorites buttons. These both invoke the Expression Manager dialog, which contains a list of previously applied queries and a list of favorite queries. A query can be selected from either of those lists and then applied, and queries can also be copied from the former list to the latter list, as desired. In the case of PCB files, a Create Rule button is also provided in the List Panel. When the designer is satisfied that the result set of the currently applied query matches the requirements of a Design Rule, clicking on that button facilitates the creation of the Design Rule concerned. The Inspector Panel property viewing and editing tool As just described, the list view (contained within the List Panel) displays the properties of the target file s currently unmasked objects in a tabular format. The Inspector Panel also displays the properties of objects, but in a condensed and qualified form. More specifically, this Panel displays a summarized list of the properties of the target file s currently selected objects. Its left hand column lists all of the types of properties which are common to all of those objects, while its right hand column indicates whether or not all of those objects have the same value for each of those types of properties. When a particular value is displayed, all of those objects have the same (displayed) value for that particular property, while the absence of the display of any such value alternatively indicates that those objects do not all have the same value for that particular property. Even though the data displayed is of an incomplete nature (unless just one of the target file s objects is currently selected) the data that is displayed can still be very useful in various situations, and precisely because of the nature in which this is presented. The designer is able to determine, and at a glance, which property values are common to all of those objects, and which (remaining) property values are not. By its nature, this Panel can be very useful to have displayed during global editing procedures, which are also only ever applied to the target file s currently selected objects. Designers have an indication of which property values are common to all of those objects, and both before and after each type of commonly shared 28-8

329 An Insider s Guide to the Query Language article property is globally updated. It can even be used to actually update these property values, and as such, displaying the List Panel at those times can be avoided; in some situations, having that capability can be advantageous. Masking - another highlighting option Designers have long had the ability to control which objects within files are currently in a selected state. And assorted Zoom commands have similarly permitted designers to select which region of a file s graphical view is currently displayed. With DXP, designers have additionally been provided with the ability to select which objects within a file are currently in a masked state. Masked objects are not capable of being selected or of otherwise having their properties edited in any way. And unlike unmasked objects, masked objects do not have their properties displayed in the list view. In a file s graphical view, unmasked objects are always displayed in a totally undimmed form. To distinguish them from unmasked objects, masked objects can be displayed in a dimmed form, with an associated Mask Level control (invoked by clicking on the Mask Level button near the bottom right corner of the DXP window) controlling how much the display of masked objects is dimmed. (At its limits, this control either causes masked objects to be displayed in a totally undimmed manner, or else causes the display of these to be totally suppressed.) The Mask Level control is used to control how much the display of currently masked objects is dimmed. 28-9

330 An Insider s Guide to the Query Language article The masking feature can be used for a variety of purposes, and its power and usefulness is a consequence of the designer having the ability to control which objects in a file are currently masked. One example of how the masking feature can be usefully deployed is to enable a designer to edit just some objects within a file, while the remaining objects are disabled from having their properties edited, but continue to be displayed. Because the masked objects are still displayed, the designer can see where these are relative to the unmasked objects. In the previous illustration, the only unmasked objects are those on bottom side layers, but all of the objects in the file are still displayed. (In past versions of Protel, the designer would have had to have chosen between switching off (the display of) some of the layers, which would have totally suppressed the display of all of the objects on those layers, or else leaving all layers displayed, which would have left all of the objects in an editable state.) However, the masking feature is far more powerful than just enabling the designer to select which layers are masked, or which types of objects are masked. And there are many other purposes for which this feature can be deployed. For another example, because masked objects cannot be selected, designers can also control which objects within a file will be selected when the (Edit») Select» All command is invoked. The masking feature can be invoked by various means, including from queries. However, this article primarily focuses on using queries (which can also be used to control which objects in a file are selected, and which area of a file s graphical view is displayed). Applications of Queries (Queries in context) When a query is applied to a file, the properties of each of the objects within this are evaluated, to determine whether its properties comply with the specifications defined by the query s contents. The thus-compliant objects become members of that query s result set, and the combination of the highlighting options also selected at the same time, together with whether each object is a member of the result set or otherwise, determines the updated selected and masked properties of each object, and the manner in which each object is subsequently displayed in each of the file s data views. These aspects are not just academic in nature: queries are genuinely useful, and can facilitate the tasks undertaken by designers. As such, details are provided of the practical uses that queries can be put to, and the different ways that the query feature can be accessed. Finding, Presenting and Editing Objects Three distinct highlighting options are available at the time that a query is applied, and it is possible for each of these options to be selected totally independently of the others. At least one of these options is always selected in practice (as selecting none of the options would produce an outcome of no practical use), and in some situations, designers could elect to select two of the options, or even all three of them. A brief summary of the nature of each highlighting option follows

331 An Insider s Guide to the Query Language article Mask option If the Mask option is selected when the current query is applied, the objects which are not members of the result set subsequently acquire a masked state, which prevents them from being selected or otherwise edited; the objects which are members of the result set subsequently acquire an unmasked state, and so remain capable of being selected and otherwise edited. The designer also has the ability to control how masked objects are displayed in the graphical view. It is possible to display these in the same manner as unmasked objects, but alternative options have also been provided of displaying these in a dimmed state, or of totally suppressing their display all together. The Mask option can be used to prevent particular objects from having any of their properties changed, or to additionally inhibit the display of these. (As described later though, hierarchical considerations can sometimes result in some masked objects remaining in an editable and fully displayed state. However, having a comprehensive understanding of queries provides designers with the ability to specify queries which minimize the extent to which that is problematic in practice.) All of the unmasked objects are listed in the list view, whereas masked objects are not listed there 3. Another very useful reason for selecting the Mask option is to determine whether there are any objects in the file having particular properties (or combinations of properties). If any such objects do exist, they will become members of the result set of an appropriately specified query, and will thus be displayed in the list view. Furthermore, just those objects will be displayed there, as all of the remaining objects will not be members of the result set (and thus won t be displayed there as well). Select option If the Select option is selected when the current query is applied, all of the objects which are members of the result set subsequently acquire a selected state, while all of the remaining objects (which are not members of the result set) acquire an unselected state instead. This option would typically be selected just prior to global editing procedures, because only those objects which are currently selected have their properties updated at the time. But there are other occasions when the Select option can be useful, such as when particular objects are to be moved, copied or deleted. Zoom option If the Zoom option is selected when the current query is applied, the graphical view of the file is customarily updated. The updated view is one whose boundaries just enclose all of the objects which are members of the query s result set. 3 Hierarchical considerations qualify that situation (again). Some queries retain particular parent objects, while simultaneously filtering out some or all of their child objects. Although not selected by default, an option is available to restore otherwise filtered out child objects (of retained parent objects) to the list view

332 An Insider s Guide to the Query Language article This option would often be selected in conjunction with one or both of the other options; as the objects which are not members of the result set would either be unselected or masked (or both) at the time, designers would often want the graphical view of the file to be updated so that only the objects which have acquired a selected or unmasked state (or both) are displayed in the updated graphical view. If the Mask option has not been simultaneously selected, objects which are not members of the result set will still be displayed in the graphical view, if they are located within the updated boundaries of this. At first glance, selecting this option by itself might seem pointless, but there could still be times when a designer wants to update the graphical view so that this encompasses particular objects, while not changing the selected state or masked state of any of the file s objects. Applying Queries Queries can be applied from the List Panel, or from Find Similar Objects dialogs, or from Query Builder dialogs, or from the Filter Toolbar (in the case of PCB files), or from resources (menu entries or toolbar buttons or shortcut keys). When the Find Similar Objects and Query Builder dialogs are used, the contents of the associated queries are automatically generated. This is helpful for those who have yet to master how to specify queries for particular tasks, especially as it is also possible for the contents of those queries to be displayed in the List Panel. The List Panel is the primary location for designers to apply queries when they want to specify their contents. In many cases the updated contents of the list view will be of interest, which in itself is a reason for having the List Panel displayed at the time. That Panel also supports designer-specified queries in various ways, including the provision of a keyword popup feature, which facilitates the entry of recognized keywords. There is a much lower level of assistance provided for keying in queries in the Filter Toolbar, and the highlighting options it uses are fixed, but it does provide a list of most recently used queries, from which a query can be selected for re-application. The default set of resources includes some menu entries which apply queries, and designers have the ability to apply their own queries from customized resources. Details associated with applying queries from resources are provided later in this article. Query Options When a query is applied, there are assorted options that can usually be specified at the same time. Three of those options are the highlighting options, but normally at least one other option also needs to be specified at the time, as described here. Mask option This is one of the highlighting options; when specified, the objects in the result set are placed in an unmasked state, while the remaining objects are placed in a masked state. As described elsewhere, 28-12

333 An Insider s Guide to the Query Language article objects in a masked state are not displayed in the file s list view, and are typically displayed in a dimmed manner in the file s graphical view. They are also not capable of being selected or of otherwise having any of their other properties modified in any manner. Select option This is one of the highlighting options; when specified, the objects in the result set are placed in a selected state, while the remaining objects are placed in an unselected state. Objects in a selected state are displayed in a distinctive manner in both the file s graphical view and list view, and have their properties updated during global editing commands. Zoom option This is one of the highlighting options; when specified, the objects in the result set are displayed in the updated view of the file s graphical view; whether each of the remaining objects is displayed depends upon its location relative to the updated region that is displayed in the file s graphical view. And whether each object is displayed in the list view depends upon whether various other options were selected. It is possible to specify that (any) one of those outcomes be selected, or that (any) two of these be selected, or that all three of these be selected. (It is also possible to specify that none of these be selected, but then no aspect of the file would change when the query is subsequently applied.) Which outcomes are specified for a particular query will depend upon why the query is being applied, and whether the designer wants to view and edit objects from the file s graphical view or from the list view (or from both of these). Clear Existing option This option can usually 4 also be specified whenever a query is applied. When selected, the file is always cleared before the associated query is applied. (The outcome of clearing a file is that every object in the file acquires both an unselected state and an unmasked state.) When not selected, any objects which were already displayed in the manner matching how objects in the query s result set are consequently displayed are unconditionally added to the query s result set, implying that such objects remain displayed in the same manner following the query s application. As such, while the provision of this option does enhance the capabilities of queries, to not select this option typically results in outcomes which are unexpected by designers with less experience; hence such designers should always opt for selecting this option. 4 This option can be specified when the query is being applied from the List Panel or from Find Similar Objects or Building Query dialogs, or from resources. When the query is being applied from the Filter Toolbar (in the case of PCB files) though, the file is always cleared previously

334 An Insider s Guide to the Query Language article Current Component / All Components option (Schematic Library files) In the cases of Schematic Library files, designers can additionally select whether the query returns compliant objects in just the currently focused part, or whether it returns compliant objects in all of the parts contained in the target file. Whole Library option (PCB Library files) In the cases of PCB Library files, designers can additionally select whether the query returns compliant objects in just the currently focused footprint, or whether it returns compliant objects in all of the footprints contained in the target file. Current Document / Open Documents option (Schematic files) In the case of Schematic files, designers can additionally select whether the query returns compliant objects in just the target file, or whether it returns compliant objects in all Schematic (document) files which are currently open. Run Inspector ( Find Similar Objects and Query Builder dialogs) When a query is being generated from Find Similar Objects or Building Query dialogs, designers can additionally specify whether the Inspector Panel is to be consequently displayed. When this option is selected, that Panel will always consequently be displayed, and regardless of whether it was displayed previously or otherwise. When this option is not selected, the displayed state of that Panel does not change. Create Expression ( Find Similar Objects and Query Builder dialogs) When a query is being generated from Find Similar Objects or Building Query dialogs, designers can additionally specify whether an associated expression is also generated or not. When this option is selected, an expression is generated, and this is listed in the List Panel, which is also consequently displayed. When this option is not selected, no expression is generated or listed in the List Panel, and the displayed state of that Panel does not change. Finding Similar Objects facilitating global object editing A longstanding feature of DXP has been the ability to edit the properties of multiple objects simultaneously. As one example from Schematic files, designers can change the Color property of all Power Objects having a particular Text property (e.g. GND ) within a file to the same value, and from just one editing procedure. And as one example from PCB files, designers can similarly change the Hole Size property of all vias having a particular Via Diameter property (e.g. 30mil) within a file to the same value, and again from just one editing procedure. That global editing capability has been retained, but global editing procedures are now always applied to whichever objects are currently selected

335 An Insider s Guide to the Query Language article The implications are that it is first necessary to select whichever objects are to have their properties changed during the subsequent global editing procedure, and that it is also very important to select all of the correct objects, and just those objects, before undertaking that global editing procedure. In some situations, the appropriate objects could be selected by the user without having to apply any query. However, in other situations, the potential exists for some objects to incorrectly remain unselected, and / or for some objects to incorrectly be selected, and as such, it would then be desirable to apply an appropriate query, in order to insure that the correct objects are in fact subsequently selected. Designers with sufficient experience in using queries could specify an appropriate query in such circumstances, but not necessarily other designers. As such, a Find Similar Objects feature has been provided, and this automatically generates a query whose contents produce an outcome matching that desired by the designer. This feature is invoked by positioning the cursor over one of the objects that is to have its properties modified, and then selecting the Find Similar Objects item from the (right mouse button) popup menu. (Alternatively, the menu item of Edit >> Find Similar Objects could be selected, or the key sequence of Shift+F could be invoked. The cursor then acquires a busy state, and one of the objects that is to have its properties modified should then be clicked on.) A Find Similar Objects dialog is subsequently invoked, and the designer then selects which types of properties need to have same values (as the just clicked-on object). By default, the Object Kind property of the other objects has to have the same value, but typically other types of properties need to be similarly matched as well. When the objective of using this feature is to select objects for global editing purposes, the Clear Existing and Select Matching checkboxes should both be checked. And at least one of the Run Inspector and Create Expression checkboxes should also be checked, so that the List Panel and / or the Inspector Panel are subsequently displayed; one of those Panels needs to be used to implement the following global editing procedure. When the Create Expression checkbox is checked, the List Panel is subsequently displayed, and the contents of the associated query are displayed in that. And although the queries generated by the Find Similar Objects feature are relatively unsophisticated in nature, studying their contents still provides designers with insights into how to specify their own queries. Designers who have acquired all that they can from studying those queries will typically either not continue to use the Find Similar Objects feature, or else will alternatively select the options of checking the Run Inspector checkbox, but not the Create Expression checkbox. With that set of options, the query generated by the feature is no longer loaded into the List Panel, but the Inspector Panel is subsequently displayed, which facilitates implementing the succeeding global editing procedure(s)

336 An Insider s Guide to the Query Language article The Query Builder feature automating query generation Although the Find Similar Objects feature is useful in many circumstances, the power of the queries which this generates is still rather limited in nature, compared with the power available from queries of a more sophisticated nature. The most complex queries can only be specified by designers with sufficient experience in using and specifying these. However, the Query Builder feature permits queries of intermediate complexity to be automatically generated, with the contents of these based upon the options and specifications selected by the designer in the associated Building Query dialog. That dialog can be invoked by clicking on the Builder button within the List Panel. It can alternatively be invoked by selecting the menu item of Edit» Build Query, or the key sequence of Shift+B. (The checkboxes and the Apply button within this dialog are only displayed if the dialog was not invoked from the List Panel.) The Building Query dialog (part of the Query Builder feature) assists those who are less experienced in specifying queries; a query is automatically generated whose contents correspond to the conditions specified by the designer. The left hand section in this dialog contains controls, whose purpose is to assist the designer in the task of specifying what properties are required for each of the file s objects to be returned by the query generated by this dialog. As each of those conditions are specified or edited, the contents of the corresponding query are updated and displayed in the dialog s right hand section. If this dialog is then closed by clicking on its OK (or Apply) button, either the associated query will then be applied, or its contents will then be copied back to the List Panel (depending upon how this dialog was invoked in the first instance)

337 An Insider s Guide to the Query Language article The Query Helper Dialog support for designer-specified queries It is possible to enter queries directly into the List Panel, and sufficiently experienced designers can take advantage of the associated keyword popup feature, which facilitates the entry of recognized keywords. However, until designers have an in-depth understanding of the set of available keywords, it is still recommended that they use the Query Helper dialog whenever they attempt to specify their own queries. That dialog is invoked by clicking on the Helper button within the List Panel. (It can alternatively be invoked by clicking on the Query Helper button within the PCB Rules and Constraints Editor dialog, or by clicking on one of the Helper buttons within the Impedance Formula Editor dialog.) This dialog provides comprehensive assistance to the designer, as it incorporates a Syntax-checking feature and a complete list of valid keywords (for the type of currently focused file). If this dialog is closed by clicking on its OK button, the contents of the query within it are then copied back to the List Panel (or to the PCB Rules and Constraints Editor dialog, or to the Impedance Formula Editor dialog). The Query Helper dialog provides comprehensive assistance for designers who want to specify their own queries

338 An Insider s Guide to the Query Language article A brief description is provided for each keyword that is listed, but even more comprehensive online help can be accessed, by pressing the F1 key while one of these keywords is highlighted. That invokes the Online Help System dialog, which provides comprehensive details of which objects within a file are returned by the highlighted keyword, how to use that keyword, and one or more examples of its usage. The Online Help can be accessed by pressing the F1 key while the Query Helper dialog is displayed. Comprehensive details are provided on how each available keyword can be used within queries. Design Rules in PCB Files The use of queries for any other purpose is not compulsory, but queries do have to be used to specify the Scope(s) 5 of each Design Rule that is defined in a PCB file; the query s result set defines which objects within the PCB file that the Design Rule concerned applies to. However, assistance is again available to help designers in specifying these queries. The Query Helper and Building Query dialogs can both be invoked from the PCB Rules and Constraints Editor dialog, 5 Most types of Design Rules are of a Unary nature, and thus have only one associated Scope. However, Clearance, Short Circuit, Acute Angle, Parallel Segment, and Component Clearance types of Design Rules are of a Binary nature, and thus have two associated Scopes

339 An Insider s Guide to the Query Language article which also supports automatic generation of the query contents for some of the simpler (but still frequently used) Scopes. That dialog also contains a Rule Wizard button, which invokes a New Rule Wizard dialog, providing designers with yet another form of assistance when it comes to specifying Design Rule Scopes. As referred to previously, the List Panel contains a Create Rule button. The designer can evaluate the result sets of queries from this Panel, and once satisfied that the result set of the currently applied query matches the requirements of a Design Rule, then click on that button to facilitate the creation of the Design Rule concerned. It needs to be kept in mind that, in general, what counts in the result set of Design Rule queries is the primitive objects rather than the group objects. The former objects are of a fundamental or child nature, and include arcs, fills, pads, (text) strings, tracks, and vias. Conversely, the latter objects are of a parent nature, and include components, coordinates, dimensions, nets, and polygons. Thus a Clearance Rule which specifies a customized clearance between polygons and other objects actually requires a query whose result set includes the child objects of polygons, rather than of the parent polygon objects. As such, an appropriate query to specify is InPolygon or InPoly (which returns child objects of polygons), rather than IsPoly (which returns parent polygon objects). For designers wanting to specify their own queries, the Online Help System dialog documents the result set of each keyword provided. Specifying Impedance Formulae In Width Design Rules, designers can now specify either the traditional Width constraints, or alternatively specify Characteristic Impedance Driven Width constraints. When the latter option is selected, Minimum, Preferred, and Maximum Impedances are then specified, rather than Minimum, Preferred, and Maximum Widths. The Impedances thus specified are converted into corresponding Widths, with the relationships between Impedances and Widths being determined by the Impedance Formulae which have been specified. To access those formulae, and to change them if desired, the Layer Stack Manager dialog first needs to be invoked (from the menu entry of (Help» Popups») Options» Layer Stack Manager ). The Impedance Calculation button in that dialog then needs to be clicked on, which invokes the Impedance Formula Editor dialog. Each tab in that dialog contains a formula which defines the (characteristic) impedance as a function of track width, and another formula which defines the track width as a function of (characteristic) impedance. Each of those formulae are specified by query-like expressions, which can be edited by designers if desired. Clicking on either of the Helper buttons in that dialog invokes the Query Helper dialog, but in this case, all of the PCB Functions keywords listed in that dialog are listed under an Impedance section. Those keywords define assorted properties of the PCB which have an influence on these formulae, thus permitting designers to specify their own formulae. A default pair of formulae has been defined for each tab of the Impedance Formula Editor dialog, and each of those formulae can be restored by clicking on the appropriate Default button in that dialog

340 An Insider s Guide to the Query Language article Unless designers know what they are doing, and have a good reason to change them, the default formulae should in fact be used. The formulae concerned have been specified because they do model the relationships between track widths and characteristic impedances to a respectable degree of accuracy. Filter Toolbar The Filter Toolbar is (currently) only provided for PCB files. It permits the designer to mask all of the objects within a file except for those having a Net property specified by the designer, or all of the objects within a file except for those forming part of a component specified by the designer. However, designers can also specify queries of their choice, by entering these in the right hand most edit-box provided. Designers can also select a query from a drop-down list of most recently used queries. The right hand most edit-box of the Filter Toolbar is used to specify the contents of a query. Unlike when queries are applied from the List Panel, or from Find Similar Objects or Building Query dialogs, or from resources, it is not possible to specify which options are used when queries are applied from the Filter Toolbar; in all cases, any previous query is totally cleared, and the Mask and Zoom options are then used with the current query. Applying Queries from Resources As mentioned previously, it is possible to apply queries from resources (menu entries or toolbar buttons or shortcut keys). And the set of default resources for each type of file that supports the use of queries actually does incorporate such resources; these are of a menu entry nature, and are listed under the popup menu that is invoked after pressing the Y key. The Customizing DXP Resources tutorial article describes how designers can customize their resources. Thus designers have the ability to apply queries, customized for their requirements, from customized resources. There are pros and cons to applying queries from resources. The advantage is that queries can be applied faster than by any other method, because designers do not have to key in the query s contents, or select the query from the lists of favorite and previously used queries, or specify which properties of similar objects need to match or differ, nor do they have to specify which highlighting options (or any other options) are to be selected when the query is applied; all of those details are specified in the corresponding resource entry. The disadvantage is that because all of those aspects have been predetermined, designers are thus unable to change any of them at the time that the query is applied. (Hence queries should be applied from resources only when none of those aspects do need to be changed at the time.) 28-20

341 An Insider s Guide to the Query Language article To create customized resources that will apply queries in Schematic Library or Schematic files, the Process of Sch:FilterSelect should be specified (in the Process field within an Edit Command dialog). Similarly, the Process of PCB:RunQuery should be specified to create customized resources that will apply queries in PCB Library and PCB files. At least three Parameters also need to be specified. An Expr Parameter is mandatory to specify the contents (text string) of the query, and a Boolean Parameter of ClearExisting is also required. And Boolean Parameters of Mask, Select, and Zoom also need to be provided as required. (If any of the highlighting option Parameters are not specified, a False Parameter Value will be assigned for the corresponding option; thus at least one of those parameters also needs to be specified, and in conjunction with a True Parameter value.) An example of the text which should be entered into the Parameters field within an Edit Command dialog is as follows: Expr=IsComment And (Hide = ''True'') Mask=True Select=False Zoom=False ClearExisting=True As is customary for specifying (Process) Parameters, the character is used to separate distinct Parameters. Thus this Parameter entry stipulates that the contents of the query is the text string IsComment And (Hide = 'True') (which will return all Text objects which are also Designator strings of Component objects, and which are also currently in a hidden state), and that the file is to be cleared before that query is applied, and that just the Mask highlighting option is to be used. In reality, it was not necessary to additionally specify False Parameter Values for the Mask and Select highlighting options, but the example still demonstrates how five distinct Parameters can be specified in the Parameters field. Note also that any words which are quoted within a query s text string need to be doubly quoted when that string is included in the Parameters field within an Edit Command dialog. Resource files use quotation characters to define the start and end of any strings within each resource s specification, so when such strings incorporate quotation characters themselves (as is the case with the Expr Parameter value in the above example), the duplicated quotation characters specify that the current string actually incorporates a quotation character itself at that location, rather then specifying that the string starts or ends at that location. Inside the Query Language Although the contents of a query are automatically generated when this is applied from a Find Similar Objects or Building Query dialog, designers who want to derive the maximum power of queries need to learn how to define the contents of queries for themselves. The following material is intended to assist them in this regard. Nature of Queries The filtering capabilities provided by queries are not confined to any pre-defined list of filtering actions, from which the designer selects an item as required. Instead, the result set of the data filtering 28-21

342 An Insider s Guide to the Query Language article feature is determined by the contents of a query, which can properly be regarded as the leading control input of the data filtering feature. A query consists of a (text) string whose contents are of a nature that is comprehensible to the dat filtering feature s (parsing) software. A comprehensible query always contains at least one recognizable keyword, and much (and even most) of the data filtering feature s power is a consequence of the ability for comprehensible queries to contain multiple keywords. Clicking the Helper button in the List Panel (or the Query Builder button in the PCB Rules and Constraints Editor dialog) invokes the Query Helper complete list of valid keywords. A brief description is also provided for each keyword that is listed. However, the on-line Help file (invoked by the F1 key while a keyword is highlighted) should be referred to for comprehensive details of which objects within a file are returned by each available keyword, how to use each keyword, and acceptable types and values of parameters that can be used in conjunction with those keywords that can only be used in conjunction with one or more parameters. Many (but not all) of these keywords can be used by themselves to specify a valid query. One example of this is the keyword IsHorizontal (which is listed in the Attribute Checks section, in turn listed under the PCB Functions category). As the description provided for that keyword indicates (Is the object a Horizontal track), a query consisting of just that keyword returns just track objects, and furthermore just those tracks that are horizontal in nature. (Such tracks have identical Y1 and Y2 properties, and later on, another example of a query will be provided which achieves the same outcome as using that keyword by itself.) Other keywords are not recognized when used in isolation, and need to be used in tandem with recognizable parameters. One example of this is the ObjectKind keyword (which is listed in the Fields section within the PCB Functions category). A valid query which uses that keyword is ObjectKind = 'Fill', and the outcome of using that is that just Fill objects are returned. (An alternative query of IsFill (another keyword which can be used in isolation, and which is listed in the Object Type Checks section within the PCB Functions category) would also achieve the same outcome, and this is a not atypical example of how a given outcome can be achieved by different queries.) Queries using Multiple Keywords Although a considerable assortment of keywords has been provided, what really boosts the power of the Filtering feature is the ability to specify queries which contain more than one keyword. One elementary example of this is the query of IsHorizontal Or IsVertical, which returns all tracks which are horizontal, and all tracks which are vertical. Another such example is the query of IsHorizontal And OnMultiLayer, and that returns just tracks, and furthermore just those tracks which are both horizontal and on the Multi-Layer layer. Those last two examples demonstrate a general principle. The use of the special keyword Or (in conjunction with other keywords) generally increases the number of objects which are returned by a query. On the other hand, the use of the special keyword And (in conjunction with other keywords) generally decreases the number of objects which are returned by a query. (Queries can also incorporate the keyword of Not, but sometimes there are complications associated with using that, 28-22

343 An Insider s Guide to the Query Language article which will be covered in due course.) A sophisticated query typically uses a number of different keywords to produce a desired outcome, and the special keywords of And and Or are typically each used at least once. While none of the examples provided so far have required the use of brackets to be unambiguous in meaning, they are customarily required for queries of a more complex nature. And even for queries for which brackets are not strictly required, it is still good practice to use them to make them more designer-readable (not to mention sustaining the very desirable habit of using brackets in order to define queries of a totally unambiguous nature). The following example demonstrates a mix of the And and Or keywords, and why brackets must sometimes be used to avoid ambiguity: ((IsPad And OnMultiLayer) Or IsVia) And (HoleDiameter < 16) However, the use of exactly the same keywords, and in the same sequence, but with brackets in different locations, results in a query with a different meaning: (IsPad And OnMultiLayer) Or (IsVia And (HoleDiameter < 16)) (Both of those queries return all vias whose hole diameter is less than 16mil, but each of them differs in which pads are also returned. The first query returns pads on the Multi-Layer layer whose hole diameter is less than 16mil, but the second query returns all pads on the Multi-Layer layer, regardless of their hole diameters.) Finding Objects with particular Properties While queries can be used to control which objects are currently capable of being selected or edited, they can also assist in determining if any objects in the file have properties of a particular nature (or particular combinations of various properties). As one example of this, the query of (IsComment Or IsDesignator) And (Not OnSilkscreen) returns all Designator strings and Comment strings in a PCB file that are on neither of the Overlay layers. Another example is the query of IsDesignator And (Hide = 'True') which returns all Designator strings in a PCB file that are currently in a hidden state. The query of IsPolygon And OnSignal And (PolygonRemoveDeadCopper = 'True') will be very useful for anyone who has ever placed a polygon in a PCB file and then lost it. That situation can happen when a polygon is placed on a signal (or positive copper) layer and the option of removing dead copper is selected; if there are no other objects within the area occupied by the polygon which have the same Net property (as the polygon), the polygon will be invisible as a consequence of having no associated child objects. But applying that query will reveal if any such polygons do exist, and if so, the designer can then double-click on the corresponding row within the List Panel to invoke the properties dialog for the polygon concerned. (At that time, some of the properties of the polygon can then be changed so that it is no longer hidden following a subsequent repour.) 28-23

344 An Insider s Guide to the Query Language article An enhanced Padstacks feature has been newly provided for Multi-Layer pads; it is now possible to specify the dimensions and shape of such pads on each signal layer. That enhanced functionality would not normally be required, but a query of (ObjectKind = 'Pad') And (PadStackMode = 'Full Stack') would soon determine if any pads within a file are making use of that feature. Perhaps more likely are pads which are making use of the longer-provided Top-Middle-Bottom option instead. But the query of (ObjectKind = 'Pad') And (PadStackMode <> 'Simple') will return all pads which are not using the Simple option; it will return all pads using the Top-Middle-Bottom option, and any pads which are using the newly introduced Full Stack option. Finding Objects with calculated properties The examples provided so far have demonstrated that it is not difficult to specify a query which will return objects having particular properties (or combinations of properties). However, what makes queries even more powerful is their ability to return or exclude objects based upon calculated (rather than explicit) properties. The query of IsTrack And (Y1 = Y2) returns tracks which also have identical Y1 and Y2 properties. Such tracks are consequently horizontal in nature, and the query of IsHorizontal actually returns exactly the same objects. However, this example illustrates that the functionality of some of the keywords provided can alternatively be implemented by queries containing appropriate combinations of keywords of a more fundamental nature. Another example of this is that the query of ManHat > 20 can alternatively be implemented by the (somewhat more complex) query of IsTrack And ((ABS(X1 X2) + ABS(Y1-2)) > 20). An example of a filtering capability that cannot otherwise be implemented more simply by the use of any exotic keywords, but which nevertheless still can be implemented, is the following query, which returns tracks that are on an angle between 49.9 degrees and 50.1 degrees (i.e. an angle of /- 0.1 degrees): IsTrack And (ATAN((Y1 - Y2) / (X1 - X2)) Between (49.9 * PI / 180) And (50.1 * PI / 180)) (The ATAN function returns an angle (which is the inverse tangent of its parameter) measured in units of radians, and to convert such an angle to degrees, it needs to be multiplied by (π / 180). Although designers can convert angles into radians themselves, the provision of the keyword of PI, that returns a numeric value equal to π, facilitates specifying angles in degrees whenever keywords of a Trigonometric nature are being used.) In reality, it is highly desirable to avoid the use of queries with which the potential exists for dividing by zero, and such an outcome would indeed come about whenever a vertical track was being evaluated (for membership of the result set) by the above query. As such, that query should be regarded solely as an explanatory example, and a better query, which would achieve the desired outcome, and without the possibility of dividing by zero, is as follows: IsTrack And IIF(X1 <> X2, (ATAN((Y1 - Y2) / (X1 - X2)) Between (49.9 * PI / 180) And (50.1 * PI / 180)), 0) 28-24

345 An Insider s Guide to the Query Language article IIF(L,A,B) is a specialized tool kit keyword, which always requires the provision of three parameters (depicted here as L, A, and B), and with each of those being separated by commas. It can best be thought of as a command which specifies: If L is True, then return A, otherwise return B. In the above example, the parameter L is the string X1 <> X2, which returns a value of True if X1 is not equal to X2, but otherwise returns a value of False. The parameter A is the string (ATAN((Y1 - Y2) / (X1 - X2)) Between (49.9 * PI / 180) And (50.1 * PI / 180)), which is thus evaluated when L is True. When L is True though, the value of (X1 - X2) cannot possibly be zero, so the possibility of dividing by zero whenever that string is being evaluated is subsequently eliminated. The parameter B is the string 0, which is evaluated when L is False. That happens when X1 is equal to X2, but as that only happens when the track being evaluated is vertical, its associated angle is thus 90 degrees. However, that angle is outside the range of interest (of 49.9 degrees to 50.1 degrees), so returning a result of 0 (or False) results in such a track being unconditionally outside the result set (as desired in the circumstances). Hierarchical aspects A characteristic feature of both Schematic and PCB files is that some types of objects within a typical file are of a primitive nature, while the remaining types of objects are of a group nature. Group objects, by nature, customarily incorporate one or more primitive objects. On the other hand, primitive objects are either free in nature, or are otherwise owned by a group object. As such, relationships of a hierarchical nature exist between various different objects within a file. That situation facilitates the production and editing of designs; as one example, it is very useful to be able to move or edit a component object as a single entity, rather than having to process each of its child objects on an individual basis. However, these hierarchical relationships do have implications for queries, especially when the Mask option is selected during the application of a query. Parent objects and child objects are distinct entities, and it is possible for a query to mask a particular parent object, while not masking some or even all of its associated child objects. The converse is also possible; a query can assign an unmasked state to a particular parent object, while masking some or even all of its associated child objects. It is normal to edit the properties of a group object by editing the properties of its parent object, rather than by directly editing the properties of any of its child objects. In actual fact, it is often not even possible to directly edit the properties of child objects. When a query is applied and one or more parent objects subsequently acquire a masked state, any child objects of the group object(s) concerned, which have not (also) been masked by the currently applied query, often can t have any of their own properties edited at the time, and because their parent object has been masked, it is also not possible to edit the properties of that object either. The implication is that those objects are displayed in a view only state, rather than additionally being in an editable state

346 An Insider s Guide to the Query Language article However, even though it is generally not possible to directly edit the properties of child objects, changing the properties of a parent object usually does change at least some properties of at least some of its child objects. And that situation is the reason behind the policy for the graphical view to display all of the (non-hidden) child objects of an unmasked parent object, and regardless of whether each of those child objects is currently masked or otherwise. That these situations exist is a mixed blessing. Even when a particular parent object has been masked, thus preventing its properties from being viewed or modified, it is likely that for at least some of the time, designers still want to be able to view any of its child objects which are not currently masked. Conversely, whenever it is currently possible to edit a parent object s properties, there is still at least some merit in continuing to display all of its child objects in the graphical view, because in many situations changing the properties of a parent object also changes the properties of at least some of its child objects. Thus even when some (or even all) of the child objects are currently masked, the potential remains that at least some of their properties could change, because their parent object is still in an editable state. In a nutshell, the graphical view can display child objects as though these are unmasked, even though they are not displayed in the list view. And that has implications whenever queries are applied to control how objects are displayed in the target file s graphical view. As one example, a pad object in a PCB file can be a child object of a parent object and of a net object. If for whatever reason it is desired to display that pad as though it is a masked object in the file s graphical display, it would be necessary to specify a query which would assign a masked property not just to that pad itself, but additionally to its parent component object, and to its parent net object. Failure to mask all three of those objects would result in the pad being displayed in the graphical view as though it was an unmasked object. This aspect can be confusing to those who don t appreciate what is happening. But as described, it is not without reason that child objects are sometimes displayed in the file s graphical view as though they are unmasked, even though they are not also displayed in the file s list view. Tricks of the Trade How to re-filter queries There can be times when designers might want to re-filter the objects in a file, in which the objects returned by one query (and just those objects) have their properties evaluated by a following query, so that all of the objects which were not returned by the first query are all also unconditionally not returned by the second query. And to achieve that outcome, all of the objects which are to be evaluated by the second query should be placed in a selected state, and the contents of the second query should be qualified by the use of the IsSelected keyword, in conjunction with the And operator. As an example, if the contents of the second query would otherwise be IsPad, then a query of IsSelected And IsPad should be specified instead. That way, all of the Pad objects which are not in a selected state at the time that the second query is applied will still be filtered out after the second query has been applied

347 An Insider s Guide to the Query Language article How to comment a query Any text within a query s contents which is surrounded by opening and closing curly brackets is ignored by the data feature s parsing software. Thus curly brackets can be used to add comments to queries. Where to now Hopefully those who have read this article now have some comprehension of the power of the data filtering feature, and of the potential power that is available from mastering the art of how to specify queries of an appropriate nature for various objectives. It is hoped that those who have read this will have learnt enough to at least feel sufficiently confident to experiment with queries. Ultimately, that is how designers will become true masters of using queries. Although articles like this have an important role in getting designers initially acquainted with these, it is ultimately usage and experience that are more important in determining each designer s level of expertise

348 An Insider s Guide to the Query Language article Appendix: Examples of Useful Queries The following lists are examples of queries which can be used to accomplish particular objectives. Queries to use with PCB files IsComponent And (Copy(Name,1,2) Between 'C0' And 'C9') Returns Component objects whose Name property starts with C and which immediately follows with a number, e.g. C1, C22, etc. InComponent('C*') And HasFootprint('0603') And (IsDesignator Or IsComment) Returns Designator and Comment strings which belong to components which have a Footprint property of 0603 and a Name property which starts with C. InComponent('C*') And HasFootprint('0603') And IsPad Returns pads which are child objects of components, and which parent objects have a Footprint property of 0603 and a Name property which starts with C. (StringType = 'Free') And (Component <> 'Free') Returns strings which are child objects of components, but which are neither Designator strings nor Comment strings. OnTopSolderMask Or OnTopSilkscreen OnBottomSolderMask Or OnBottomSilkscreen Useful for checking whether any overlaps occur between the objects on one of the Silkscreen layers and the objects on the Solder Mask layer on the same side of the PCB. (When used, the Silkscreen layer selected should be set to be the current layer, and the Solder Mask layer being checked should also be set visible at the time.) Queries to use with Schematic files Object_Designator(Parent) Like 'R*' Returns child objects of Part objects whose (Component) Designator property starts with R. E.g. R1, R2, RA1, RV12, etc. IsParameter And (Object_Designator(Parent) Like 'R*') 28-28

349 An Insider s Guide to the Query Language article As above, but returning just those child objects which are Parameter objects. IsParameter And (Object_ObjectKind(Parent) = 'Part') Returns Parameter objects which are child objects of Part objects. IsPart And (PartId ='') Returns all single-part Part objects. PartId Like '?* ' PartId <> '' Returns all multiple-part Part objects. (PartDesignator Like 'R*') And (Copy(PartDesignator,2,1) Between '0' And '9') Copy(PartDesignator,1,2) Between 'R0' And 'R9' Returns Part objects whose (Component) Designator property starts with R and which immediately follows with a number, e.g. R1, R22, etc. ((StringText > '') And (Not IsPowerObject)) Or (ParameterValue > '') Returns all objects incorporating a string, when that string can have its Font property changed, and contains at least one character. IsParameter And OwnerName = '' IsParameter And (Object_ObjectKind(Parent) = '') Returns Sheet Parameters. OwnerName = '' Object_ObjectKind(Parent) = '' Returns Sheet Parameters, and other objects which are not child objects of any object

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351 Understanding & managing DXP panels article 29 Understanding & managing DXP panels Abstract Panel Overview General Design Panels PCB-Schematic Panels Editor-Specific Panels Panel Info Abstract This article introduces panels, which offer alternative views and tools for manipulating design documents besides the standard graphical environment. Some of these panels are system-level (transcending all editors), some are only available in the major design editors, while others can only be seen in specific editors. A brief overview is given for each of the major design panels in DXP. Panel Overview Around the workspace are panels. (If all panels have been turned off, you may re-enable them through the View menu, or by clicking on the Panel Control button below the workspace.) Panels are varied in their functionality. Some of them won t do a thing until your design enters a specific state (the Inspector panel is blank until you select at least one object in your design; the Navigator panel is empty until you at least analyze one document). Others only become available when you have their associated editors active. A panel may be docked solidly on the edge of the workspace or clipped there, only rolling out its contents when the cursor is hovered over its name. Alternatively they may be left floating above the workspace or turned off altogether. Right-clicking the panel s name will offer additional docking controls, while holding down the Control key while dragging a panel will suspend its normal docking behavior. Normally, hotkeys have either been disabled or reassigned within panels. For instance, the arrow keys within a design document will pan zoom, but the same arrow keys in the List panel s spreadsheet will move you through its rows and columns. We have introduced a new set of system-level commands that transcend the conflict between active panels and active documents, allowing you to move freely between them. The two you will find pre-packaged in the Customize dialog are a command to hide all floating panels (assigned to F4), and a command to toggle back and forth between the active document and the last-used panel (assigned to F5). 29-1

352 Understanding & managing DXP panels article General Design Panels Most panels are not confined to a single editor. The File panel is for opening new or existing documents, including project files. The Projects panel shows all open projects. Open documents that have not been invoked through a project are listed in the Project panel as free documents. The current group of projects you have collected within this panel may be saved as a project group file. The Help Advisor lets you run natural-language searches for topics. All types of help documentation is subject to these searches results may include articles, tutorials, process-based help, or even What s This help entries. A history of your searches is kept, allowing you to relocate results. The Libraries panel shows all added libraries, whether they be PCB, schematic, or integrated. These libraries may be accessed manually to place components directly into design documents, or automatically when you are updating documents with different components one way or another (or both). The Messages panel also displays automatically when a project is compiled but rather than appearing beside the workspace, it naturally docks along the base. Messages are reported according to the flags set in the Project Options dialog. Double-clicking on individual messages opens the floating Compiled Errors panel, which displays links to the primitives involved in that message. The contents of this panel simply allow you to jump between locations as you look to unravel each violation. Double-clicking on a different message in the Messages panel will refresh the Compiled Errors panel with new links. That panel, in turn, springboards information to the Compiled Object Debugger panel. You can sort, filter or clear away the data in the Messages panel at any time you want. PCB-Schematic Panels DXP s two major editors, PCB and schematic, share a series of panels that are not available elsewhere in the program. The Navigator panel lets you steer through your design documents in ways appropriate to each editor. The schematic editor, in fact is linked to a Browser that will let you move through your design along connectivity paths linking components, pins, wires and nets. If you find navigating with the Browser disconcerting, try holding down the Shift key as you click on an object. This keeps the Browser s focus on the object in question, even while the other navigation tools (highlight, select, 29-2 You can control the objects that display in the Navigator and Browser panels in the Project Options dialog. graph and zoom) let you view the connected elements. Holding down the Alt key as you click in either the Browser or the Navigation panel allows you to cross-probe between the schematic design and the target PCB, assuming the latter is also open. The List panel lets you construct filters through logical expressions. It also provides access to the Query Helper, which will tutor you in using the query language that drives DXP. Try pressing the F1 key

353 Understanding & managing DXP panels article while highlighting a specific command; the online help provides comprehensive assistance in writing commands in the right way. A Filter History allows you to browse to previously-used expressions and reapply them. Also included in the List panel is a spreadsheet view of all filtered objects in tabular format. Here you may sort and arrange columns, further narrow the filter through column masks, select items and even edit attributes directly. Selecting a group gives you the special option of making group edits at once, a feature otherwise only available in the Inspector panel. The Inspector panel displays a list of attributes shared by all selected items, and allows these objects to be edited at once. Once you have selected all the items you want to change together, this panel will first show you if this is possible, then let you make the change. Modifying any of these attributes propagates the change across the entire selection. For example, selecting some wires, buses, ports and sheet symbols together would include the Color attribute in this panel, since they all share this attribute. Adding a component to your selection, however, will eliminate the Color field from the Inspector panel, since color is not a field applicable to components. Note: In the PCB editor, the Inspector panel will only include the items selected within that particular PCB. But in the schematic editor, the Inspector panel will include the selections within all open schematic sheets. While the XA keyboard shortcut will deselect all objects in the current document, the XD shortcut has been added to deselect all items in all open schematic documents. Editor-Specific Panels A handful of panels are not shared across any editors, and so are only available when a particular document type is active. PCB and schematic library documents, for instance, each have a Library Editor panel for browsing and editing footprints or components. The PCB editor has a PCB panel that lets you browse and edit the nets, components, rules/violations, from/to s, or split planes in your design. Similarly, the Text, CAM, and Simulation editors all have their own panels. Each of these panels are designed specifically for the diverse tasks allotted to each editor. Panel Info Most of the panels you come across in DXP contain advanced features that deserve your attention. We recommend that you avail yourself of the online help that details the purpose and procedures for each panel. This can be done by activating a panel (clicking within it) and pressing the F1 key. Additional information about specific panels are included in other articles. The Libraries panel is discussed in the Enhanced Library Management Using Integrated Libraries article, the List panel is discussed in the Introduction to the Query Language article, and the Projects panel is discussed in the Transferring a Design from Protel 99 SE to DXP article. 29-3

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355 Specifying PCB Design Rules & Resolving Errors article 30 Specifying PCB design rules & resolving errors Abstract PCB Design Rules Defining PCB Rules PCB Rules and Constraints Editor Rule Scope and Constraints Recycling Rules Design Rule Checks Online DRC Batch DRC Abstract This article describes how rules are defined, edited, and checked through online or batch DRC tools. It discusses preventing errors on the one hand, and navigating and resolving violations on the other. PCB Design Rules Design rules are not a frill or an add-on for serious PCB designers they are an integral part of the design process. Accordingly, DXP s design rule checks have been developed to interact with your style of design work. Once upon a time there may have prevailed in the printed circuit board industry an attitude of design first, check later. This is absolutely not an option for modern PCB designers, who require tools to keep tabs on complex and multifarious rules as they set out and route their boards tools that will detect violations as soon as they are made. But design rules should be in place before you start designing for other reasons as well: both manual and autorouting routines will look to existing rules to know what to avoid. In fact, manual routing has been renamed interactive routing to emphasize its regard for design rules. For example, you may set the interactive router to avoid or even push around obstacles, that is, objects that would otherwise cause a design rule violation with the track you are laying down. Whatever design rules you set up will be saved with your board. In fact, a list of generic rules are generated even when you create a new board. This is DXP s way of nudging you to establish your rules before you start designing before you even move a MOSFET, so to speak. 30-1

356 Specifying PCB Design Rules & Resolving Errors article Defining PCB Rules There are three places where you may define PCB rules: in PCB directives, the PCB Rules and Constraints Editor and the PCB panel. PCB directives allow design rule constraints to be defined as parameters in the schematic editor. This allows design rules to be created before a target PCB is even created. It also assigns Unique ID values to each rule, letting you report differences and synchronize updates after the rule has been added in the PCB document. The scope of these rules, however, is defined by the placement of the PCB directive. The PCB panel lets you browse a board by rules. Here you only have access to existing rules, but you have the luxury of pressing the Cancel button if you change your mind in the middle of editing a rule. The PCB Rules and Constraints Editor, in contrast, is a live editor, with no undo or cancel options. PCB Rules and Constraints Editor The PCB Rules and Constraints Editor dialog enables you to set up new design rules or edit existing ones, for the current design. Individual rules are separated by major categories and sub-categories (types). Multiple rules of the same type will be automatically prioritized, letting DXP resolve any conflicts between them. Rules are divided into categories and sub-categories. These priorities can be redefined by the user. In the folder-tree pane on the left side of the dialog, each of the ten design rule categories are listed under the Design Rules folder. Click on a category to list all specific rules that have been defined for all associated design rule types of that category, in the main editing window of the dialog. Click on a rule type to list all specific rules that have been defined for that type. Click on the root folder to list all specific rules that have been defined for all design rule types, across all categories. In each case - whether you have clicked on the root folder, a category or a type - the main editing window of the dialog will display summary information for each defined rule, including: the rule name, the type of rule it is and the rule category it belongs to; the scope of the rule (i.e. what object(s) it applies to); the constraint attributes that have been defined and the rule's priority. You can also enable/disable a rule from within these summary list views. A report of currently defined design rules for all categories, a specific category or a specific type, can be generated. Simply right-click in the respective summary list, or over the respective entry in the folder-tree and choose the Report command in the pop-up menu. The Report Preview window will appear, with the appropriate report already loaded. Rule Scope and Constraints All rules have two basic parts: scope and constraints. The scope is the target group, and is focused the same way objects are filtered: through queries. These queries can be written free-hand, or by using intuitive pull-down lists within this editor or the more advanced tools in the Query Builder or Query Helper. Some rules, such as the clearance rule illustrated above, have two scopes. This is inherent in the rule type; a clearance rule, for example, implies two targets that must be kept a certain distance 30-2

357 Specifying PCB Design Rules & Resolving Errors article from one another. We call these binary rules, which contrasts with the more common unary (singlescope) rules. Constraints define the rule itself. A Rule Wizard can be launched from the PCB Rules and Constraints dialog. This has been introduced to assist you in specifying new constraints and scope(s) from scratch. Recycling Rules Other, less obvious tools will allow you to reuse pre-defined rules. Right-clicking in the folder-tree section of the PCB Rules and Constraints dialog will give you the option to import or export individual rules. If, on the other hand, you want to import a whole set of pre-defined design rules, you may want to prepare a blank PCB document that has all the rules set up. This document can be saved as a template for future PCB s (put it in the Altium/Template folder). Design Rule Checks All design rules, with the exception of signal integrity rules, may be checked actively during design (online) or all at once (batch). In the Design Rules Checker dialog you may designate which rule types (classes) you wish to include in the Online DRC, the Batch DRC or both. To run a batch DRC from this point, simply click on the Run button. If you simply wished to add or remove rule classes to or from the online DRC, you may simply make the changes and press the Close button. Online DRC For a rule to be subject to the online DRC (displaying violations as they occur), three requirements must be met. In addition to enabling the rule in the PCB Rules and Constraints Editor, and designating its rule class for online checking in the Design Rule Checker, you must make sure that the online DRC is turned on for the whole PCB editor, which is a system preference. Once all three are enabled for online checking, violations will be flagged as they are created. That is to say, any objects within an online rule s scope that are found in violation of that rule s constraints will change from their normal color to the color assigned to the DRC Error Layer (by default violations are painted a conspicuously bright green). Additionally, the PCB panel is refreshed immediately with violations when they are detected by the online DRC. In this way, you may see what rules have been violated, then find a resolution either by modifying the board or by tweaking the rules. Double-clicking on individually listed violations yields a more detailed description about each infraction. 30-3

358 Specifying PCB Design Rules & Resolving Errors article Batch DRC But the online DRC should never replace batch DRC entirely. In fact, you would do well to remember that the online DRC only detects new errors ones that are created after you turn it on. So while good designers know the value of the online DRC, they also know that board design should begin and end with a batch DRC. The Design Rule Checker dialog allows you to set up batch mode checking for the same individual rules covered by the online mode, with the addition of signal integrity rules. An option is also provided that allows you to specify how many violations can be found before the DRC is stopped. Another benefit of running a validation in batch mode is that it allows you to create a report. This report lists each rule type that is tested. Any violations located are listed in each case, including full details of any reference information such as the layer, net name, component designator, pad number and location coordinates. Further options in the DRC interface allow you to include internal plane violations and sub-net details. The latter can be used if checking has been enabled for the Unrouted Net rule. Whether generating a DRC report or not, it is always a good idea to enable the option that will highlight violations in the PCB workspace after running a batch DRC. As a visual aid, such highlighting can often speed up the process of resolving rule violations. 30-4

359 Impedance Controlled Routing article 31 Impedance Controlled Routing Abstract Impedance-Controlled Routing Calculating Widths for Layers Interactive Routing Abstract This article discusses the new layer-specific controls that have been added to PCB routing width rules. These may be defined manually based on the user s own impedance calculations, or they may be calculated in DXP based on the characteristic impedance value provided. Impedance-Controlled Routing New controls have been added to the routing width design rules. Now you may set a width rule that is different depending on what layer you re on. The major reason designers would want this control is that their boards have high-speed clock signals such that traces behave like transmission lines. Parasitic effects, such as ringing, losses, delays and reflections can be controlled by placing routes of just the right width. This width is a function of the characteristic impedance calculated for the signal layer and it will be different for different layers. If you ve done the calculations yourself, you can simply enter the Minimum, Maximum and Preferred widths for each layer, and have that rule apply to whatever signals fall within the scope of your rule. But you don t have to do it yourself. You can choose to have the layer widths driven by a characteristic impedance value (Z0), which you provide. Calculating Widths for Layers The preferred characteristic impedance value you enter in the width rule dialog factors into formulas defined in the Layer Stack Manager. This is an appropriate place for impedance calculations to be made, because they use the layer stackup both to determine which formula to use, and to see how far each signal layer is from the relevant plane(s). DXP makes separate calculations for Microstrips and Striplines. A microstrip refers to a signal layer that has an internal plane somewhere above or below it in the layer stackup, but not both (that s a stripline). Two keywords have been introduced into the query language to make these separate calculations: TraceToPlaneDistance for microstrips, and AboveBelowPlaneDistance for striplines. 31-1

360 Impedance Controlled Routing article Since these calculations rely upon the physical order of signal layers and planes, as well as the physical height of copper layers and dielectrics, designers interested in accurate impedance-controlled routing should finalize these board values before they begin routing affected nets. Interactive Routing If you have access to Protel DXP, you will find that the track width will jump automatically to the preferred value defined in the corresponding width rule when you move from one layer to another (currently, this applies to interactive routing, but not to autorouting). Any changes you make to the rule will not alter nets you ve already routed, but if your existing routes now fall outside the calculated width constraints, you will see errors when you run a Design Rules Check. You should also be aware that the current set of impedance controls does not account for the effect of vias, but assumes lossless transference from one signal layer to the next. Additionally, this only takes into account single-ended structures, which look at an entire layer, and determine the routing width of target nets on a whole-layer basis. 31-2

361 Transferring a design from Protel 99 SE 32 Transferring a design from Protel 99 SE Abstract Generating Projects Components Libraries Links and Unique IDs Net Identification Scope PCB Import Wizard Board Shape Split Planes Special Rule Conversions Rules Simulation Model References and Configurations Multi-Channel Designs Saving Work Notes Abstract This article outlines the steps by which Protel 99 SE designs may be converted into PCB projects in DXP. It discusses the correlation between databases and project groups, introduces new innovations for components and libraries, and describes potential conflicts on legacy designs, with information on how to resolve them. Generating Projects To convert a 99 SE database into projects for DXP, simply open the database from DXP s menu. Confirming this operation launches a two-step process. First, all of the database s contents are poured into a new Windows folder (with the same name and location as the database itself). Second, some additional files are generated and opened within DXP namely, one project group file, plus any number of individual project files. While your 99 SE database may contain any number of document types all of which are written to the hard drive in step one the automatic project-building that occurs in step two only takes into account PCBs, Schematics, Libraries and Netlists. A separate project file will be created for every folder containing at least one of these file types. The type of project depends upon each folder s contents. 32-1

362 Transferring a design from Protel 99 SE If the folder contains any schematic, netlist or PCB files, a PCB project is created (.PrjPcb), and all recognized design documents are included within it (i.e. schematic, PCB and library files). If the folder includes schematic libraries but no schematics or PCBs, a library package is created (.LibPkg) and schematic library documents in this folder are added to it. (PCB libraries are not automatically added to library packages as you may prefer to use ordered search paths for finding models). DXP identifies documents via their file extensions. Any of your PCB, schematic, library or netlist files that do not have an appropriate extension (or any extension at all) within your database will be left out when the new DXP projects are generated. Remember, however, that such files will still be written to the hard drive, and may still be included by renaming the documents with appropriate extensions, then dragging them from Windows Explorer into DXP s Project panel. Components As you examine your design documents in DXP, you will discover some changes none of which should interrupt your work flow. One is that all text fields and part fields in schematic components and libraries are converted to parameters. While 99 SE offered up to eight text fields and 16 part fields per component, DXP has imposed no limit on the number of parameters that may be added. A few specific fields in 99 SE components were reserved for simulation data. When these fields are used as such, DXP will translate their values to the Model section rather than the Parameter section. Multiple models, like parameters, may be added to a single component without limits. Unlike parameters, only one model of any given type may be enabled (current) at one time. Libraries DXP offers new innovations in the handling of libraries, but none of these are mandatory. All of your 99 SE libraries will work directly in DXP; simply add the ones you need (schematic and PCB alike) to DXP s Libraries panel, and they will work as they did before. That said, there are strong arguments for getting your feet wet in DXP s new pool of library resources. The panel s list of added libraries may be re-ordered, letting you decide which libraries take precedence in the search for matching footprints. It also allows for a third type of library to be added: Integrated Libraries. Integrated libraries allow you to associate specific models with specific components, and bind them together. Now, when the component is placed in a schematic and synchronized with a PCB document, the footprint model that appears will be the one you prepared in the library for that component. There will be no component not found errors, as the integrated library file is, in fact, a database containing 32-2