ELEC 204 Digital System Design LABORATORY MANUAL
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1 ELEC 204 Digital System Design LABORATORY MANUAL : Introductory Tutorial For Xilinx ISE Foundation v10.1 & Implementing XOR Gate College of Engineering Koç University Important Note: In order to effectively utilize the laboratory sessions, you should read the manual and prepare the experiments before the sessions.
2 1. Objectives: Become familiar with the Xilinx ISE Foundation software package o Foundation Project Navigator o Foundation ECS Schematic Editor o Foundation ModelSim Logic Simulator Become familiar with Pegasus board o Downloading your designs into your Pegasus board o Testing your designs on board Create schematics and macros within a new project Simulate your schematics Loading bit stream into Pegasus board & testing 2. Equipments: BASYS2 Board Pentium PC Cables/wires to connect them 3. Procedure: i. Read the Introductory Tutorial for Xilinx ISE Foundation v10.1 ii. Go through the steps of the tutorial and implement the given logic function. iii. Implement the XOR Gate. 4. Assessment: Write a report summarizing the exact procedure you used to test your circuit. Describe any problems you encountered, how you knew that the circuit was functioning properly. Present the schematic diagrams of your design. Make your comments and state your conclusions for the experiment.
3 Introductory Tutorial for Xilinx ISE Foundation v10.1 Step 1: Start Foundation From the Start menu, launch ISE Foundation Project Navigator From File menu, select New Project and hit OK. Name the new project Lab1 ; Select Top-Level Module Type HDL and click on Next.
4 Change the contents of the boxes as shown below and click on Next Click on New Source in the new window
5 Select VHDL Module from the list and enter the file name, then click on Next Enter the input and output names and click on Next
6 Check the summary and click on Finish Step 2: Writing the VHDL Code Write the VHDL code as follows
7 Step 3: Simulator Select Project New Source. In the dialog box, select Test Bench Waveform as the source type. Name it Lab1_tbw. Modify the following window as seen below and click on Finish:
8 Using the mouse enter some waveform for the input signals Select the Behavioral Simulation form the drop box as seen below: Double click on the Simulate Behavioral Model to start the simulation
9 You should get the results as seen below: Step 4: Specifying Pin Numbers Select Lab1.vhd and from the User Constraints select the Floorplan IO Pre Synthesis Address the input-output pins as seen below, read the LOC from the board.
10 Step 5: Implement Double click on Generate Programming File. This will create the.bit file that we are going to download to the board. Step 6: Downloading the bitstream to the Board Go to the directory that you have saved your project and copy the.bit file that you generated to an easy to access directory. Open the Digilent Adept program, browse your.bit file to load and click Program.
11 Implementing XOR Gate Problem: Create an XOR gate using Figure 1 as a guide. X Y INV AND 2 INV AND 2 OR2 Z Refer to the steps in the introductory tutorial and turn in 1. XOR gate schematic 2. XOR gate simulation results a. truth table verification b. inputs transitioned from 0s to 1s 3. Show that your implementation works properly on the FPGA board.
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