Long Term Trends for Embedded System Design

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1 Long Term Trends for Embedded System Design DSD 2004 A. A. Jerraya TIMA Laboratory 46 Avenue Felix Viallet Grenoble Cedex France Tel: Fax:

2 Some Definitions Embedded System: Application Specific Electronic Subsystem System: Appliance, instrument or vehicle Application specific: tailored to specific needs Electronic subsystem also called Embedded System Application software, also called embedded Software or Embedded System by SW Community Execution platform (SoC, board, ) Hardware Components and Interconnects Hardware dependent Software Also called Embedded Software by Semiconductor community DSD

3 Outline 1. From ASIC to SoC 2. Embedded Software vs. Hardware dependent Software 3. The key technology: HW-SW Integration 4. Long Term Trends DSD

From ASIC to SoC Design From Perfect Wires to Higher Level Interconnect Yesterday HW only Perfect interconnect How to abstract HW-SW Interfaces?

4 From ASIC to SoC Design From Perfect Wires to Higher Level Interconnect Yesterday HW only Perfect interconnect How to abstract HW-SW Interfaces? Today Tomorrow Heterogeneous HW Multiple SW stacks CPU & SW How to Non perfect interconnect interconnect heterogeneous SW HW SW HW components? SW Comm.Netw. Transistor model (t=rc) RTL SW Tasks SW adaptation (OS/drivers) SW tasks SW SW tasks OS OS MPU MPU CPU core Comm. int. int. SW adaptation HW adaptation CPU HW adaptation on-chip communication Network IPs HW adaptation How to handle imperfect interconnect? IPs DSD

5 The SoC Era Challenges SoC: put on a chip what we used to put on one or several boards (ASIC, CPU, Memories, Analog/RF, MEMS, ) Facts: 90% of new ASICs already include a CPU in 130nm. Multimedia, network processors, mobile terminals and game applications are already multiprocessors. Fundamental changes: Key issue SoC is different from ASIC SoC is different from SW SoC requires abstract HW-SW interfaces to allow fast integrations Universal SoC platform (programmable, reconfigurable, ) Application specific SoC DSD

6 Generic SoC Platform vs. Application-Specific SoC Example: The GSM History/Roadmap 1986 Rack in a van 1990 PCB 1995 Chip set in a hand-set 2002 SoC 2006 SW component on a generic platform, e.g. Nomadic (ST) Same roadmap for game computers, MP3, STB, NP, DVD DSD

7 Why SoC Design is Needed Applications Entertainment Security Networking Smart terminal Productivity enhancements Disappearing Electronics Example: MPEG2 encoding 2000x1000 frame Full motion search 128x128 search window 32 TIPS (TERA instruction per second) All software: RISC, 1Ghz DSD

8 Outline 1. From ASIC to SoC 2. Embedded Software vs. Hardware dependent Software 3. The key technology: HW-SW Integration 4. Long Term Trends DSD

9 SoC Platform vs. Embedded Software Application software Platform_API HdS CPU sub-system HW interfaces NoC HW interfaces HW components SoC Design Application SW design: Real time SW Models Platform model, e.g. Sony PlayStation, Nomadic Key Issue: Complexity (GB, ms) Platform_API: Programming model to build software Specific to application Hides HW details Hardware dependent SW (HdS) Provided by SoC designer in case of specific CPU sub-system Lower SW layers to access HW Specific SoC function (e.g. DSP SW code) Key issue: Performances (K&MB, ns) Hardware CPU sub-systems Specific hardware, Analog, memories, Network-on-Chip HW interfaces: required for application specific HW/SW interfaces DSD

10 Example: SW Debug of an MPEG4 CoDec Debug Cost for mapping a High level parallel program on a Fixed 4 CPU Hardware Platform Data dependent computation C library bug Application SW Booting is not synchronized among processors. Lost some interrupts 13 5 Bugs % 5 13 Wrong interrupt priority levels HAL Context switch does not work correctly. µ-kernel Incorrect FIFO counter value causes deadlock. Parallel Prog. Model Result of compressed video is not correct. Memory Map Abnormal execution of a portion of C code Design Environment HdS (78%) DSD

11 From Board to SoC Design Practices for Boards and SoCs SW application HdS Virtual architecture model SW designers Communication centric SoC design SW application Platform API SW Designer SW test bench HW/SW Integration ISSs, HW IP model Implementation test bench SoC designer HW/SW Integration Abstract Interfaces HW Components (RTL & Layout) SoC Designer HW designer HW Components (RTL & Layout) HW designer DSD

12 Data Base Validation Concurrent SoC Design System Specification Partitioning System Architecture Abstract HW-SW Interfaces SW SW design design Platform-API SoC Integration - HdS - design - HW - HW Integration HW Interfaces HW design TEST HW-SW interfaces are the key issues to master time-to-market, performances and complexity. DSD

13 Outline 1. From ASIC to SoC 2. Embedded Software vs. Hardware dependent Software 3. The key technology: HW-SW Integration 4. Long Term Trends DSD

14 Abstracting HW-SW Interfaces The Virtual Component Model Virtual component Component Hardware IP Software IP Functional IP Abstract Interfaces Required Services Provided Services Control Services Synchronization Parameters,. Execution Environment Component 1 Abstract Interface 1 Execution Environment Component 2 Abstract Interface 2 Abstract Platform (e.g. NoC, Cosimulation backplane, ) Heterogeneous components thanks to adaptation between different Interfaces DSD

15 SoC Integration Design Flow System specification is a virtual architecture: virtual modules using specific programming models connected through an execution environment. Architecture implementation: heterogeneous components and sophisticated communication interconnect to adapt different programming models. Automatic generation of application-specific HW/SW interfaces and CPU subsystem. Partial solutions: FlexNP, Xpipes, Æthereal, Roses, OCCN, Tensilica, ARM, Xilinx, Sonics. Virtual Virtual Processor Processor Virtual SW component Processor SW task 1 SW components (Tasks) SW interface sub-system (SW wrapper) CPU sub-system HW interface sub-system (HW wrapper) System Specification SW task 2 Virtual Virtual IP IP HW Virtual component IP HW block 1 Execution environment (e.g. AMBA bus) API SW comp. API CPU HW block 2 Basic SW interface component Basic HW interface component API HW comp. API network Communication interconnect (e.g. NoC) HW component HW interface sub-system (HW wrapper) DSD

16 SoC Design of a DivX Encoder OpenDivX Open source Mpeg4 encoder/decoder Modified to work concurrently on 1/4 th of each frame Goals Refinement of HW/SW interfaces Multi-level simulation and early validation SW debug before HW platform is ready. DSD

17 DivX Encoder: Overview INPUT : Split coming frame in 4 parts and send it to CPUs CPU_# : Treat coming data and prepare it for compression VLC : Finalize compression and prepare the whole image COMBINER : prepare for output and adjust compression parameters DMA : Direct access to local memories of processors. Data flow CPU_0 HW IP SW Node CPU_1 Video stream Input CPU_2 VLC Combiner MPEG video CPU_3 DMA DSD

18 DivX Encoder: Overview Major architecture specificities Specific Memory Controller : Switch bank service Specific Interface : Core IT + 2 Synchronization Signals Point to Point communication scheme VLC CPU 3 CPU 2 CPU 1 CPU 0 ARM ARM Core Add Dec Core RAM/ROM Interface bank0 Mem Controler bank1 bank0 bank1 INPUT DMA Combiner DSD

19 CPU Sub-system Architecture With An ARM9 Core MemCtrl MemCtrl SRAM0 SRAM1 SRAM ROM Bus Matrix Address Decoder Memory Controller AHB AMBA Link to DMA DSD

20 Programming Model for DivX (DMS) HW component Virtual IP(I/O) HW component Virtual IP(DMA) SW component SW component (P1) SW component (P2) SW component (P3) (P4) HW block 1 HW block 2 HW block 1 HW block 2 Stand by SW encoder task 1 p1 p2 SW SW task task 1 2 SW SW task task 1 2 SW task 2 RT-level channels SystemC transaction level channels Message Passing Programming Model Message passing: DMA control: p1.sram_init(base_address) p2.conn_setup (rmt_id,lch,rch) p2.send (lch,laddress,size) p2.recv (lch,laddress,size) p2.rwrite (lch,laddr,raddr,size) p2.rread (lch,laddr,raddr,size) p2.iwait (lch) p2.pwait (lch) memory_bank_struct *memory_io; // initialize message structure p1.sram_init(&mes); // loop forever while(1) { // input data p2.recv( ); p2.pwait( ); // gets the data while (mes!= end_data) { memory_io[mes.addr] = mes.data; } // calls encoding function divx_compress(&(memory_io->ins), &memory_io->outs, 1); // sends output data for ( ) { p2.send( ); p2.pwait( ); } wait(); } DSD

21 ROSES: SoC Integration Design Flow Virtual Architecture Virtual component 1... Virtual component n Abstract interface 1 Execution environment Abstract interface n communication/system services lock round-robin scheduler HAL I/O read ISR boot... Software wrapper library SW Interface generator task 1 CPU core 1... OS HAL HW wrapper HW Interface generator task n MPSoC Architecture IP core 1 HW wrapper processor adapter library CPUx CPUy protocol library SyncE HndShk HndShk+FIFO HndShk+Frames... Hardware wrapper library HW Component HW simulator Co-simulation interface sub-system (Cosim. Wrapper) Co-simulation wrapper generator Co-simulation Architecture SW Component SW simulator Co-simulation interface sub-system (Cosim. Wrapper) Functional component Co-simulation interface sub-system (Cosim. Wrapper) simulator interface library VHDL_port_IN Matlab_port_IN protocol library SyncE HndShk HndShk+FIFO HndShk+Frames... Co-simulation wrapper library Communication interconnect Co-simulation bus DSD

22 Key Technology: Composing Interfaces Component services Abstract interface services Execution environment Component interface Required/Provided services Control and Synchronization services Parameters Interface sub-system composition Services matching User-extensible library Code specialization Component Interface component library MPI channel Data conv. ARM7 boot I/O driver Scheduler Unix IPC Interface sub-system composition Works for HW, SW, and Functional adaptations send send Sched. IT ISR I/O write Execution environment DSD

23 The ROSES Environment DSD

24 Architecture Exploration for QCIF Resolution, 25 frames/s QCIF RESOLUTION, 25 frames/s DSD

25 Solution 1: QCIF using ARM7 (60MHz) Processors Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 12 Processors 16 Processors 32 Processors REAL TIME DSD

26 Solution 2: QCIF Using ARM9SE46-4kI$,4kD$ (60MHz) Processors Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 16 Processors 32 Processors REAL TIME DSD

27 Architecture Exploration for CIF Resolution, 25 frames/s DSD

28 Performance Results: CIF Using ARM7 (60MHz) Processors (+3 for VLCs) Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 12 Processors 16 Processors 20 Processors 32 Processors REAL TIME 0 DSD

29 Performance Results: CIF Using ARM9SE46-4kI$,4kD$ (60MHz) Processors (+2 for VLC) Frame clock cycles Processor 2 Processors 4 Processors 8 Processors 16 Processors 32 Processors REAL TIME DSD

30 Outline 1. From ASIC to SoC 2. Embedded Software vs. Hardware dependent Software 3. The key technology: HW-SW Integration 4. Long Term Trends DSD

31 Abstracting HW-SW Interfaces After Partitioning and Communication Synthesis SW API-SW HW-SW Interfaces API-HW NoC SW adaptation (HdS) HdS Abstract CPU SS HW services HW adaptation API-SW = SW programming model API-HW = NoC programming model Abstract CPU sub-system HdS = HW dependant SW HW services: local architecture (e.g. bus) SW adaptation : implement programming model on CPU subsystem HW adaptation: adapt CPU subsystem to NoC DSD

32 SoC Design Space Application Programming model Concurrency Decomposition Mapping Communication Synchronisation Interconnect NoC Programming Model HW Adaptation for application specific communication Computation sub-system Programming model CPU sub-system for application specific computation SW Adaptation T 1 T 6 T 3 T 5 T 2 T 4 API API HdS HdS CPU 1 CPU 1 sub system sub system CPU 2 sub system HW IF HW IF Com. Network HW IF HW Sub-systems DSD

33 More IMPLICIT Parallel Programming Model at different abstraction levels concurrency decomposition Interconnection mappingcommunication synchronization Interface Explicit concurrency, decomposition, mapping; Implicit communication, synchronization, Interconnection and Interface SDL, compositional C++ Explicit concurrency, decomposition, mapping, communication, synchronization; Implicit Interconnection and Interface MPI, TLM Message, thread package, concurrent C More Explicit Explicit concurrency, decomposition, mapping, communication, synchronization, Interconnection; Implicit Interface TLM Transaction All explicit ISA SW + RTL HW DSD

34 Conclusion ASIC is dead, long live SoC Design. SoC is not Software Hardware dependant Software vs. Embedded SW Application specific HW-SW interfaces Application specific SoC vs. Generic platform Composition of heterogeneous programming models vs. SW programming model Perspectives: Abstract HW-SW Interfaces, TLM for SW (2005) Abstract interconnect (2010) Abstract synchronization (2015) Abstract communication (2020) DSD

35 Thank You DSD

36 HW-SW Codesign Models Roadmap To Abstract HW SW Typical languages or models Key Technologies Year of marketing Gate delay All explicit RTL Logic optimization 1995 Interfaces ISA Embedded local Systems HW-SW interfaces TLM wrappers architecture design & optimization Interconnect Synchronization Communication Mapping Research MPI Focus Concurrent OO (Conc-small talk) SDL BSP, Log P Network-on-Chip -Network interface -Configuration System synchronization, asynchronous design Communication computation Partitioning, communication synthesis Task allocation, scheduling automation >> Decomposition ParLog Automatic partitioning >> Concurrency B, Algebric notation Execution model generation >> DSD

37 System Integration Issues Strategy: All applications to be SW running on generic platforms Computation power SW design methods Economics: Best margin and volume in market window ASIC/SoC to wait for powerful CPU. Cannot wait to be fully SW. Technology : Mixed HW-SW solutions System Architecture: still an Art Application and real-time SW: Manage Complexity HW-SW Interfaces: High Performances Standard cores: Shorten design time. DSD

38 Key Results Early and multi-level simulation allows for: Architecture exploration Debug cost reduction Debug software before hardware is ready Mitigate hardware prototyping step Automatic generation of HW and SW adaptation layers: a drastic improvement of design productivity. DSD

39 Multi-level Simulation Speed-up and Accuracy SW simulation at programming model level Application SW Abstract SW Interface Model RTL (or TLM) Speed-up ~500 (>>) Accuracy 75% (<<) HW Native SW simulation with abstract CPU sub-system model (HAL) Application SW OS HAL Model HW RTL ~100 85% HW/SW co-simulation with ISS ISS 1 100% HW RTL DSD

40 Early Simulation to Reduce HW/SW Interface Debug Cycle Validate HdS at several levels of abstraction: Applied to 83 % case study = = 17 % % HdS bugs 0 % 13 % 40 % 30% % Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW Ti T1 App. SW API Parallel Prog. Model API API PPM API PPM API PPM API PPM µ-kernel Hardware Abstraction Layer CPU Core CPU interface Network adapt. MPICH MPI SC Simulation Model µ-kernel + HAL + CPU µ-kernel Simulation Model (HAL + CPU) Instruction Set Simulator (ISS) µ-kernel HAL Simulation Model CPU ISS µ-kernel HAL On HW prototype DSD

41 SoC Design Issues Generic SoC platform vs. Application specific MPSoC HdS vs. Application specific HW-SW interfaces SW programming model vs. a composition of heterogeneous programming models Application specific HW-SW interfaces Computation specific CPU sub-system Interconnect SW adaptation: HdS HW adaptation Early validation to reduce design and debug cost. DSD

42 Outline 1. From ASIC to SoC 2. Embedded Software vs. Hardware dependent Software 3. Long Term Trends 4. Finding the Successful Strategy 5. Key Technologies DSD

43 SoC Design Strategic Issues (Handel Jones) IC VENDORS THAT ARE STRONG IN DESIGN ARE GENERALLY THE MOST PROFITABLE AND ARE IN SUPERIOR MARKET POSITION. DESIGN STRENGTHS INCLUDE COMBINATION OF DESIGN TOOLS USED, TRAINING OF ENGINEERES, IP PORTFOLIO, AND LINKING WITH PROCESS PARAMETERS. DATA SHOWS STRONG CORRELATION BETWEEN DESIGN STRENGTHS AND PROFITS. IMPACT OF DESIGN STRENGTH MAY LAST MANY YEARS, 5-7 YEARS FOR MARKET POSITIONNING. DESIGN PROBLEMS ARE BECOMING MORE SEVERE AS FEATURE DIMENSIONS DECREASE. DSD

44 SoC Initiatives in the World Taiwan: SoC strategy, build on top of semiconductor and PC industries. 4 year program to leverage education & SME Bring software into ASIC teams. Korea: strategic plan to be #1 in SoC in 2012 China: plan to train 50,000 SoC designers Hong Kong: huge SoC design centers (1 Bn $ building) USA, Canada, Japan: started few years ago DSD

45 Mastering SoC Design Pluridisciplinary Dissemination/training program Leverage existing designers Leverage existing professors New engineers generation New design methods and tools From ISA to Platform_API Abstraction of inter-domain interfaces Learn how to live with imperfections Common University/Industry Research schemes Long-term research programs Realignment process and reducing fragmentation DSD

46 The Virtual Component Model for MPSoC Basic model: a set of hierarchically interconnected virtual modules and an execution environment Virtual Module: Content: Tasks/Instances + communication channels) Abstract interface: set of virtual ports Virtual SW component Processor Internal/external ports Structure and services HW Virtual component IP Internal port (comp. prog. model) Abs. level TLM Protocol rd/wr SW task 1 SW task 2 HW block 1 HW block 2 Execution environment (e.g. AMBA bus) External port (NoC prog. Model) RT level Colif: An XML object-oriented database for virtual architectures Components programming models NoC programming models MPSoC programming model is the composition of NoC and components programming models. AMBA DSD

47 MPSoC Design Issues Generic MPSoC platform vs. Application specific MPSoC HdS vs. Application specific HW-SW interfaces SW programming model vs. a composition of heterogeneous programming models Application specific HW-SW interfaces Computation specific CPU sub-system Interconnect SW adaptation: HdS HW adaptation Early validation to reduce design and debug cost. DSD

48 Paradigm Shift Application changes, designers hard to scale Computation models, CPUs, network and massive memory on chip Smart devices, Analog/RF and MEMS on chip Technology advances, methods and tools don t scale Nano technologies, Need to rethink backend Multi-physics issues Design methods, need to rethink front-end Platformization of competitive applications Low cost high performance new smart SoC design Detecting breakthroughs, corporate R&D are no more adapted Pluridisciplinarity requires research in too many directions. No more affordable for single player, even INTEL. Application + Architecture + SoC design: enables fast and low cost design to help keeping focus and boosting competitiveness. DSD

49 Programming Model for DivX (DMA) HW component Virtual IP(I/O) HW component Virtual IP(DMA) SW component SW component (P1) SW component (P2) SW component (P3) (P4) HW block 1 HW block 2 HW block 1 HW block 2 Stand by SW encoder task 1 p1 p2 p3 SW SW task task 1 2 SW SW task task 1 2 SW task 2 RT-level channels SystemC transaction level channels Shared-memory Programming Model Shared memory: DMA control: p1.switch_banks() p2.waitevent() p3.sendevent() memory_bank_struct *memory_io; // initialize encoder library initialize(5, true, 0, 900); // loop forever while(1) { // waits for data p1.waitevent(); // gets the data address memory_io = (memory_bank_struct*) p2.switch_banks(); // signals computation starting p3.sendevent(); // calls encoding function divx_compress(&(memory_io->ins), &memory_io->outs, 1); // signals computation ended p3.sendevent(); wait(); } DSD

HW-SW Interfaces Abstraction and Design for Multi-Processor SoC

HW-SW Interfaces Abstraction and Desin for Multi-Processor SoC MPSoC 04 Dr. Ahmed Amine JERRAYA TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble Cedex France Tel: +33 476 57 47 59 Fax: +33 476 47