Course Project Part 1

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Miranda Oliver
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1 1 4 to 1 MUX with 8 bit Inputs A Complete Circuit 1 B 8 bit Enabler 3 C 8 bit MUX Merger 5 2 8 bit Adder

1 1 1 4 to 1 MUX with 8 bit Inputs A Complete Circuit 1 B 8 bit Enabler 3 C 8 bit MUX Merger bit Adder A Complete Circuit 7 B Full Adder 9 Course Project Part 1 Table of Contents 1A 4 to 1 MUX with 8 bit Inputs

2 2 The 4 to 1 MUX uses two selector bits to determine which 8 bit value is passed through. In order to implement this design, two sub designs were created. The first is an 8 bit Enabler, and the second is, for lack of a better name, the 8 bit MUX Merger. The function of both of these will be explained later. Essentially, though, the decoder works with four enablers to determine which values are allowed through. Since the decoder will have only a single output with 1, and the rest 0, only one of the enablers allows the original value of the bus through, while the rest output 0. All four busses then enter the MUX Merger and are consolidated to a single bus that outputs one of the original values. Instead of testing every 8 bit value combination across 4 busses, I have done the following to show the effectiveness of the MUX. First, I set each 8 bit bus to values that are not equal to each other; then I use all four selector combinations in order to show which bus s value is allowed through the MUX. Simplified Output Table S1 S0 Output Point on Waveform 0 0 I0 Beginning 0 1 I I I SOURCES: Logic and Computer Design Fundamentals Class Notes

3 1B 8 bit Enabler 3

4 4 The 8 bit Enabler takes an 8 bit input and a 1 bit enable. Using 8 logical AND gates, the enabler outputs the original 8 bit number only if the 1 bit enable is true. In the original design, four of these enablers are used with a decoder. One of the four busses would be the input on this circuit, as well as one of the outputs from the decoder. Since only one output works at a time from the decoder, only one of the four 8 bit busses would pass through. The value of the 8 bit input makes no difference on how the circuit functions, so I ve decided to use only four test cases, which are as follows: Simplified Output Table Input Enable Output Point on Waveform Beginning SOURCES: Logic and Computer Design Fundamentals Class Notes

5 8 bit MUX Merger 5

6 6 I had trouble naming this one. It doesn t actually function as an 8 bit logical OR. Its purpose is to take all four 8 bit busses and compare all of their equivalent bits with OR gates; however, only one of the inputs will have a value that isn t 0. Therefore, the real purpose of this sub design is to take all four busses, determine which one has a value, and pass it as a single bus. Once again, the value of the input busses makes no difference on the outcome. The value of whichever bus that has one is the only value that will pass through. I0 I1 I2 I3 Output Point on Waveform Beginning SOURCES: Logic and Computer Design Fundamentals

7 2A 8 bit Adder 7

8 8 The 8 bit adder takes two 8 bit values and outputs the sum of those values. This circuit also takes a carry in, which adds 1 to the value. If the sum exceeds the maximum the 8 bit value can output (255), it also outputs a single bit signifying this and the sum starts from zero again. Therefore, would output 0 and a C_Out bit (signifying 256). Specifically, this is a ripple carry adder. An alternative solution would be a carry look ahead adder. The ripple carry design is slower, but much simpler, whereas the carry look ahead is faster, but more complicated. In this case, I chose to use a simpler design. Once again, instead of doing all possible test cases, I decided to give the few interesting ones that showcase the circuit working as intended. A_In B_In C_In Y_Out C_Out Point on Waveform Beginning ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~395 SOURCES: Logic and Computer Design Fundamentals

9 2B Full Adder 9

10 10 The full adder accepts 3 bits as input and outputs two. The inputs A_In and B_In represent two bits of equal significance. The last input, C_In, represents a carry from a sum of lower significance. The output S_Out represents the sum of the bits, and C_Out is used as a carry to another adder of higher significance. 8 of these are used to make an 8 bit Ripple Carry Adder. The logic is simple, just refer to the truth table. A_In B_In C_In S_Out C_Out Point on Waveform Beginning SOURCES: Logic and Computer Design Fundamentals

EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS

EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,