COMPSCI 210 S Computer Systems 1. 6 Sequential Logic Circuit

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1 COMPSCI 2 S2 27 Computer Systems 6 Sequential Logic Circuit

2 Overview Basic sequential logic circuit Latches Registers Memory Finite state machine 2

3 Building Functions from Logic Gates Combinational logic circuit Output depends only on the current inputs Stateless Sequential logic circuit Output depends on the sequence of inputs (past and present) Stores information (state) from past inputs We'll first look at some useful combinational circuits, then show how to use sequential circuits to store information 3

4 Building Functions from Logic Gates Combinational logic circuit Output depends only on the current inputs Stateless Sequential logic circuit Output depends on the sequence of inputs (past and present) Stores information (state) from past inputs 4

5 6. Sequential Logic Circuit Combinational vs. Sequential Combinational Circuit Always gives the same output for a given set of inputs Examples: adder always generates sum and carry, regardless of previous inputs Sequential Circuit Stores information Output depends on stored information (state) plus input A given input might produce different outputs, depending on the stored information Example: ticket counter Advances when you push the button Output depends on previous state Useful for building memory elements and state machines 5

6 6. Sequential Logic Circuit Sequential Logic Sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs Sequential logic has state (memory) while combinational logic does not Sequential logic is used to construct finite state machines A basic building block in all digital circuitry, as well as memory circuits and other devices 6

7 6.2 Latch R-S Latch: Simple Storage Element R is used to reset or clear the element set it to zero S is used to set the element set it to one 7

8 6.2 Latch R-S Latch: Simple Storage Element If both R and S are one, out could be either zero or one. quiescent state -- holds its previous value Note: if a is, b is, and vice versa 8

9 6.2 Latch R-S Latch: Simple Storage Element R-S Latch Summary R = S = hold current value in latch S =, R= set value to R =, S = set value to R = S = both outputs equal one final state determined by electrical properties of gates Don t do it! 9

10 6.2 Latch Gated D-Latch Two inputs: D (data) and WE (write enable) When WE =, latch is set to value of D S = NOT(D), R = D When WE =, latch holds previous value S = R =

11 6.3 Registers and Memory Register A register stores a multi-bit value We use a collection of D-latches, all controlled by a common WE When WE=, n-bit value D is written to register

12 6.3 Registers and Memory Representing Multi-bit Values Number bits from right () to left (n-) Just a convention -- could be left to right, but must be consistent Use brackets to denote range: D[l:r] denotes bit l to bit r, from left to right 5 A = A[4:9] = A[2:] = May also see A<4:9>, especially in hardware block diagrams 2

13 6.3 Registers and Memory Memory Now that we know how to store bits, we can build a memory a logical k m array of stored bits Address Space: number of locations (usually a power of 2) k = 2 n locations Addressability: number of bits per location (e.g., byte-addressable) m bits 3

14 6.3 Registers and Memory 2 2 x 3 Memory address word select word WE input bits write enable 4 address decoder output bits

15 6.3 Registers and Memory Cell Arrays and Coincident Selection Write down the number of cell if the following address is used a.) A[3:] = cell 2 b.) A[3:] = Cell 9 5

16 Break & Exercises One minute break Kahoot! time 6

17 6.3 Registers and Memory Exercise 6. Q. What should be the number of cell if the address is A cell 2 B cell 3 C cell 4 D cell 5 7

18 6.3 Registers and Memory Exercise 6. Q2. What should be the number of cell if the address is A cell 2 B cell 3 C cell 4 D cell 5 8

19 6.3 Registers and Memory More Memory Details This is a not the way actual memory is implemented Fewer transistors, much more dense, relies on electrical properties But the logical structure is very similar Address decoder Word select line Word write enable Two basic kinds of RAM (Random Access Memory) Static RAM (SRAM) Fast, maintains data without power Dynamic RAM (DRAM) Slower but denser, bit storage must be periodically refreshed 9

20 6.3 Registers and Memory Registers and Memory Registers Can be accessed simultaneously Independent data bus The house has its own driveway Memory One address can be accessed at a time Shared data bus The houses with shared driveway 2

21 6.4 State Machine State Machine Another type of sequential circuit Combines combinational logic with storage Remembers state, and changes output (and state) based on inputs and current state State Machine Inputs Combinational Logic Circuit Outputs Storage Elements 2

22 6.4 State Machine Combinational vs. Sequential Two types of combination locks Combinational Success depends only on the values, not the order in which they are set. Sequential Success depends on the sequence of values (e.g, R-3, L-22, R-3). 22

23 6.4 State Machine State The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken Examples: The state of a basketball game can be represented by the scoreboard Number of points, time remaining, possession, etc. The state of a tic-tac-toe game can be represented by the placement of X s and O s on the board 23

24 6.4 State Machine State of Sequential Lock Our lock example has four different states, labelled A-D: A: The lock is not open, and no relevant operations have been performed B: The lock is not open, and the user has completed the R-3 operation C: The lock is not open, and the user has completed R-3, followed by L-22 D: The lock is open 24

25 6.4 State Machine State Diagram Shows states and actions that cause a transition between states 25

26 6.4 State Machine Finite State Machine A description of a system with the following components: A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions An explicit specification of what causes each external output value Often described by a state diagram Inputs may cause state transitions Outputs are associated with each state (or with each transition) 26

27 6.4 State Machine Finite State Machine A description of a system with the following components: A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions An explicit specification of what causes each external output value Often described by a state diagram Inputs may cause state transitions Outputs are associated with each state (or with each transition) 27

28 6.4 State Machine Traffic Sign Example A blinking traffic sign No lights on & 2 on 3, 2, 3, & 4 on, 2, 3, 4, & 5 on (repeat as long as switch is turned on) DANGER MOVE RIGHT 28

29 6.4 State Machine Traffic Sign Example Traffic Sign State Diagram Switch off Switch on State bit S State bit S Outputs 29

30 Summary On completion of this class, you are able to Remember the functions, circuits and truth tables of latches and flip-flops Access the correct memory cell given an memory address Determine the state and outputs based on the state diagram Reading: Chapter 3 of textbook 3

Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Computing Layers

Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Computing Layers Chapter 3 Digital Logic Structures Original slides from Gregory Byrd, North Carolina State University Modified slides by C. Wilcox, S. Rajopadhye Colorado State University Computing Layers Problems Algorithms