Engineering 303 Digital Logic Design Fall 2018

Transcription

1 Engineering 303 Digital Logic Design Fall 2018 LAB 4: Seven Seg, Full Adder, Ripple Adder, Heirarchical Design Build the following designs and verify correct operation. This lab uses hierarchical design. Review Part 2 - Qartus II Tutorial: Hierarchical Diagram Design Simulation from lab 1 before you do section 3 of this lab. Deliverables: 0) Seven Segment Decoder 1) Full Adder 2) 8-bit Ripple Carrry Adder 3) 8-bit Ripple Carrry Adder with Hexadecimal Display Demonstration Requirement: Demonstrate Part 3 RippleAdder with seven segment display on the DE2 board from the last part of this lab. Part 0 A Verilog Binary to Hexadecimal Seven-Segment Decoder This is an important design that you will be using the rest of the semester. Make sure it works!! Using Verilog, design and implement a circuit that will receive a 4-bit value from switches, and output a 7- bit code to drive a seven-segment display. The display will output a hexadecimal value between 0 (decimal 0) and F (decimal 15). Here is the diagram for the 7-segment decoder, and the segment numbers. B 4 Just combo logic in here 7 S SSdecode For example, 0000 (hex 0), should turn on all segments except segment 6. Another example, 0011 (hex 3), should turn on segments 0, 1, 2, 3, and 6. Another example, 1010 (hex A), should turn on all segments except 3. The signals to activate (turn on) individual segments on the DE2 board are "active low". This means that a logic level 0 turns a segment ON. For example if "S0" through "S6" are all logic 0, the display will show an 8. Engineering 303 Lab 4 Folsom Lake College Page 1 of 9

2 Your truth table will look like this, the first row is done for you. It is important that you number the signals left-to-right from "most significant bit" (msb) to "least significant bit" (lsb), as shown here. For example B3 thru BO, left to right. Inputs Outputs Hex B3 B2 B1 B0 S6 S5 S4 S3 S2 S1 S A B C d E F Makes the seven seg display 0 Use Verilog design entry. Method 1 - Write the Boolean equations from the truth table and enter the equations into Quartus using Verilog. Use the project name SevenSeg. Note that it is not necessary to simplify the equations using K-maps. You can essentially just enter the unsimplified minterms. Use the following Verilog template as your guide. Note that for convenience we can declare all 4 bits of B as a group using the syntax [3:0] B. In your equations, reference individual bits using B[0] and so forth. Below is a partial solution. // A 4-Bit Binary to Seven-Segment Decoder module SevenSeg (B, S); input [3:0] B; output [6:0] S; // declare a set of 4 inputs wires // SOP equations from the truth table // First one is done for you, you determine the rest assign S[0] = ~B[3] & ~B[2] & ~B[1] & B[0] ~B[3] & B[2] & ~B[1] & ~B[0] B[3] & ~B[2] & B[1] & B[0] B[3] & B[2] & ~B[1] & B[0]; // etc... all the way to S[6] endmodule Engineering 303 Lab 4 Folsom Lake College Page 2 of 9

3 Another method that we will learn about latter in the class is to use a case statement. Below is another parial solution. The case statement checks the value of B and ouputs the binary value specified in the list. In Verilog case statements must appear inside always statements which we will study latter in the class. Make sure to include the endcase clause before endmodule. Method 2 Use a Case statement to create a Verilog design // A 4-Bit Binary to Seven-Segment Decoder module SevenSeg (B, S); input [3:0] B; output [6:0] S; // declare a set of 4 inputs wires // Binary output from the truth table // First two are done for you, you determine the rest always@(*) case(b) 0: S=7 b100_0000; 1: S=7 b111_1001; //etc.. complete the rest through F F: S=7 000_1110; endcase endmodule Use either method to create a Verilog design for the seven segment decoder. Simulate your design. When simulating, be sure to group your inputs in descending order from "most significant bit" (msb) to "least significant bit" (lsb), as shown. Drag and drop signals to arrange them. You will need to use 16 x 0.1us = 1.6 us end time to test all sixteen of your inputs. Verify that your waveform matches your truth table. In your report, include the Verilog design and simulation waveforms. Engineering 303 Lab 4 Folsom Lake College Page 3 of 9

4 Part 1 A Full Adder Block Diagram Simulation Use a block diagram design to implement the full adder circuit shown below. Use the project name FullAdder. This circuit adds 3 bits to produce a 2-bit binary sum. For example, the last row shows 1+1+1=11, binary 3. Inputs A B Carry In Outputs Carry- Out Sum ENGR303 Simulate your design and verify that the waveform matches the truth table. Include the design and your results in the lab report. Engineering 303 Lab 4 Folsom Lake College Page 4 of 9

5 Part 2 Heirarchical Design Alpha - A Ripple Carry Adder Implement an 8-bit serial adder composed of full-adder modules, from Part 1 of this lab, chained together. This circuit will add 2 numbers A and B, where each number is an 8-bit value between (decimal 0, hex 00) and (decimal 255, hex FF). Below is a simplified degram for a 4-bit version. Implement the 8-bit version, given in the detailed Quartus block diagram at the end of this document. 4-bit Ripple Carry Adder The RippleAdder adder module uses the FullAdder module from Part 1 of this lab. This technique is known as "instantiation". Instantiation is how we implement complex heirachical design. Helpful Hint: Review Part 2-Qartus II Tutorial: Hierarchical Diagram Design Simulation from lab 1 before you continue. Create the symbol files from the FullAdder project you made in the previous part. Then create a new Quartus project for the RippleAdder, named RippleAdder8bit, and reference the Full Adder project in the Project Library. Then you will be able to insert the FullAdder into your RippleCarry adder project file. Another Helpful Hint: Insert an initial single instance of the FullAdder then add the input and outputs and label s0, a0, b0. Select all and copy (CNTL-C) and paste (CNTL-V) and Quartus will auto increment the I/O names to s1, a1, b1. Repeat and place one a top the other until you have a total of eight instances. Now connect cout to cin as shown and complete the cin and cout. When testing the waveform, make sure A and B bits are arranged from msb to lsb (top to bottom). Drag and drop to arrange them. Arrange and group and subgroup the signals as shown. Change the radix from Binary to unsigned decimal to simplify reading. Set a count on the Inputs signal, then expand to show A and B values. Here is a section of the waveform showing = 39. Seems to work, but you should also examine your waveform carefully for several other values. Include the diagram and sample waveform segment in the lab report. ENGR303 Engineering 303 Lab 4 Folsom Lake College Page 5 of 9

6 Part 3 Heirarchical Design - Ripple Carry Adder with Hex Display Hexadecimal display is useful when testing larger designs on the DE2 board. Use a block diagram design to combine the seven segment decoder and the ripple carry adder. The final circuit will display the hexadecimal equivalent of the binary adder output. You will create a new RippleCarry8bitDecode project, and reference the subprojects (and the subsubproject) using the Project Library. Remember to export the symbol files from the subprojects first. The design shown below uses a bus to group wires together. A bus is just a set of wires. Use the Orthogonal Bus Tool to draw buses to connect things. Use the Orthogonal Node Tool to draw single wires to connect to the bus. Single wires are connected to a bus by name matching (see Hint). Be sure to ground the carryin (cin) input using the GND symbol. Helpful Hint: Select the wire to be named then right click and select properties then enter the name (eg A[0]) and then select OK. To name a bus do the same although use a bus naming (eg Sum[7..0]). Name buses and individual wires as shown below so that things are hooked up correctly. For testing on hardware, it is often usefull to run some internal signals out of the design so that we can look at their values on the hardware. These extra output signals are sometimes called hooks. For this design the adder outputs S[7..0] have been run out as hooks. Connect all the module outputs including the S hooks to DE2 pins. Enter, compile, simulate, verify the design given below. Fully document all this in your report. ENGR303 The waveform would look something like shown below. You should check the output of a few sample input sequences on the waveform before you download to DE2 hardware. But, it is actually much easier to test this design on the DE2 device than it is with the waveform. Engineering 303 Lab 4 Folsom Lake College Page 6 of 9

7 ENGR303 You must demo this part so you will need to assign pins and download to DE2 hardware. Page 31 of the DE2 user manual has pin numbers for the seven segment displays. For your convenience, here are the pins for the 0 th and 1 st hex displays: Signal Name HEX0[0] HEX0[1] HEX0[2] HEX0[3] HEX0[4] HEX0[5] HEX0[6] DE2 Pin PIN_AF10 PIN_AB12 PIN_AC12 PIN_AD11 PIN_AE11 PIN_V14 PIN_V13 HEX1[0] HEX1[1] HEX1[2] HEX1[3] HEX1[4] HEX1[5] HEX1[6] PIN_V20 PIN_V21 PIN_W21 PIN_Y22 PIN_AA24 PIN_AA23 PIN_AB24 Engineering 303 Lab 4 Folsom Lake College Page 7 of 9

8 For debugging, it is useful to also hookup the binary Sum output value. Multibit values must be displayed left-to-right, from most-significant-bit (msb) to least-significant-bit (lsb). Use the following pins for the OUTPUT Sum[7..0] LAB 4 SIGNAL DE2 Name DE2 Pin Sum[0] LEDR[0] PIN_AE23 Sum[1] LEDR[1] PIN_AF23 Sum[2] LEDR[2] PIN_AB21 Sum[3] LEDR[3] PIN_AC22 Sum[4] LEDR[4] PIN_AD22 Sum[5] LEDR[5] PIN_AD23 Sum[6] LEDR[6] PIN_AD21 Sum[7] LEDR[7] PIN_AC21 Use the following pins for INPUTS A and B LAB 4 SIGNAL DE2 Name DE2 Pin A[0] SW[0] PIN_N25 A[1] SW[1] PIN_N26 A[2] SW[2] PIN_P25 A[3] SW[3] PIN_AE14 A[4] SW[4] PIN_AF14 A[5] SW[5] PIN_AD13 A[6] SW[6] PIN_AC13 A[7] SW[7] PIN_C13 B[0] SW[8] PIN_B13 B[1] SW[9] PIN_A13 B[2] SW[10] PIN_N1 B[3] SW[11] PIN_P1 B[4] SW[12] PIN_P2 B[5] SW[13] PIN_T7 B[6] SW[14] PIN_U3 B[7] SW[15] PIN_U4 Demonstrate your RippleAdder with seven segment display to the instructor. Engineering 303 Lab 4 Folsom Lake College Page 8 of 9

9 ENGR303 Ripple Carry 8-Bit Adder Design Engineering 303 Lab 4 Folsom Lake College Page 9 of 9