Computer Systems O rganization Organization Chapter 2 1

Transcription

1 Computer Systems Organization Chapter 2 1

2 computer system has three major components: CPU memories (primary and secondary) I/O (Input / Output) equipment such as printers, scanners, and modems 2

3 Central Processing Unit The organization of a simple computer with one CPU and two I/O devices 3

4 1. CPU Its function is to execute programs stored in the main memory by fetching their instructions, examining them, and then executing them one after another Bus is a collection of parallel wires for transmitting address, data and control signal, external to CPU or internal to CPU. CPU parts Control unit : Fetching instructions from the main memory and determine their type. ALU unit : perform operations such as additions and Boolean AND needed to carry out the instructions. SmallS high-speedh memory: Store temporary results and certain control information, made up of a number of registers (Program Counter :PC) (Instruction Register :IR). (Accumulator :AC) Several buses 4

5 CPU Organization The data path of a typical Von Neumann machine. 5

6 Instruction Execution Steps 1. Fetch next instruction from memory into instr. register. 2. Change program counter to point to next instruction. 3. Determine type of instruction just fetched. 4. If instructions uses word in memory, determine where, fetch word, if needed, into CPU register. 5. Execute the instruction. 6. Go to step 1 to begin executing the following instruction. Fetch-Decode-Execute 6

7 Interpreter (1)... An interpreter t for a simple computer (written in Java). 7

8 Interpreter (2) An interpreter t for a simple computer (written in Java). 8

9 RISC versus CISC What is RISC? a) RISC: or Reduced Instruction Set Computer. is a type of microprocessor architecture t thatt utilizes a small, highly-optimizedhl i set of instructions, ti rather than a more specialized set of instructions often found in other types of architectures. History The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors: one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called PIPELINING pipelining: a technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory a) Apple and SUN b) Alpha, Am29k, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture (including PowerPC), SuperH, and SPARC. 9

10 What is CISC? a) CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy p made sense, and was commonly implemented in such large computers as the PDP-11 and the DECsystem 10 and 20 machines. b) Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy. c) But recent changes in software and hardware technology have forced a reexamination of CISC and many modern CISC processors are hybrids, implementing many RISC principles. d) CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this. The major difference is that RISC chips use simpler instructions sets to achieve higher clock frequencies and process more instructions per clock cycle than CISC processors. Typically CISC chips have a large amount of different and complex instructions 10

11 Design Principles for Modern Computers 1. All instructions directly executed by hardware (High speed) 2. Maximize rate at which instructions are issued(mips,millions of instruction per second 3. Instructions should be easy to decode 4. Only loads, stores should reference memory 5. Provide plenty of registers (32) 11

12 Parallelism How to make the chips run faster Increase clock speed Parallelism : doing two or more things at once Instruction-level Parallelism(multiple instructions) Processor-level Parallelism(multiple CPU) 12

13 Instruction-Level Parallelism Pipelining a) A five-stage pipeline b) The state of each stage as a function of time. Nine clock cycles are illustrated 13

14 Superscalar Architectures (1) Dual pipeline CPU Dual five-stage pipelines with a common instruction fetch unit. Need too much hardware 14

15 Superscalar Architectures (2) A superscalar processor with five functional units. Reduce the hardware, have one pipeline with multiple functional units 15

16 Processor-Level Parallelism (1) multiple CPU An array of identical processor of the ILLIAC IV type. Single control unit per quadrant Referred to SIMD (Single instruction-stream multiple data ) 16

17 Processor-Level Parallelism (2) multiprocessors a) A single-bus multiprocessor (contention). b) A multicomputer with local memories(local memory for program code and data not shared, reducing bus traffic, digitized photograph). 17

18 2. Primary Memory Memory Addresses (1) Three ways of organizing g a 96-bit memory. Each memory consists of cells (location), each cell has address N cells, have address 0 to n-1, if a cell consists of k bits,hold any one of 2 to K different bit combinations. If the address has m bits, the max. # of cells is 2 to m, fig a needs 4 bits, b&c 3 bits. 18 Standard 8 bit cell, called byte, Bytes are grouped in words

19 Primary Memory Memory Addresses (2) N b f bit ll f hi t i ll Number of bits per cell for some historically interesting commercial computers 19

20 Byte Ordering (1) (a) Big endian memory (b) Little endian memory Bytes in a word can be numbered from L-to-R (SPARC) or R-to-L (Intel) The numbering begins at the big called Big endian. 20

21 Byte Ordering (2) (a) A personal record for a big endian machine. (b) The same record for a little endian machine. (c) The result of transferring from big endian to little endian. Name is OK, age is not, solution (d) The result of byte-swapping (c). 21

22 Error-detecting & Error Correcting Codes Errors due to voltage spikes on the power lines. Some memories use error-detecting and error-correcting. Extra bits added to the word. Memory word (m), redundant bits (r), n-bit codeword= m + r. Two codeword , How many bits differ, XOR and count the # of 1 bits = 3. Hamming distance : the # of bit positions in which h two codewords differ, and , Ham. =3 because it takes 3 single-bit errors to convert one into the other. Error-detecting and error-correcting depends on HD To detect (d) single bit-errors errors, we need a distance HD=d+1 code, To correct (d) single bit-errors, we need a distance HD=2d+1 code 22

23 Error Correcting Codes Example for error-detecting, single parity bit ( parity bit is chosen so that the # of 1 bits in the codeword is even or odd, such a code has a distance 2, since any single-bit error produces a codeword with the wrong parity. i.e it takes two single-bit errors to go from a valid codeword to another valid codeword. Used to detect single errors. Another example: consider a code with only four valid codeword , , , , this code has a distance 5, 5=2d+1, d=2, so this code can correct double errors, if a codeword arrives, the receiver knows the original is

24 Error Correcting Codes (1) Number of check bits for a code that can correct a single error m+r+1<2 to r, m is data, r is the check bits. 24

25 Error Correcting Codes (2) for 4-bits word (a) Encoding of 1100 (b) Even parity added, codeword 4 data bits and 3 parity (c) Error in AC, bit 0 goes to 1 25

26 Cache Memory The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located. 26

27 Cache Memory CPUs have always been faster than memory. In practice, this means that after the CPU has issued the memory read request it must wait for memory. The problem is not technology but economics. So we can have a small amount of fast, expensive memory or a large amount of slow cheap memory. What we would like, of course, is a large amount of fast cheap memory, Caching is the answer (French: cacher to hide) Programs do not reference memory at random (well, yours might). If memory location A is referenced, the odds are that a memory location close to A will be referenced soon. This is called the Principle of Locality of Reference Caching works by using a two level memory, a small fast one and a large slow one. When a word is initially referenced it is brought into the fast (cache) memory. Whenever it is referenced from then on it is fetched from the cache. If a word is referenced (read or write) k times in a short period then the computer needs 1 reference to slow memory and k-1 to fast memory, large k better performance 27

28 Cache Memory Performance Let c be the cache access time, m be the main memory access time and h be the hit ratio, in other words the fraction of all memory references which can be satisfied from the cache. h = (k-1)/k, The mean access time, then, is (mat = c + (1-h)m) As h tends to 1 all references can be satisfied from the cache, and mat approaches c. As h tends to 0 all references require access to main memory, and mat approaches c+m; c being the time to check the cache and m being the time required after an unsuccessful cache search. On some systems the cache search and main memory access can be started in parallel, but this requires extra hardware in order to abort the memory request if the required word is found in the cache. Main memory and cache are divided into fixed-size blocks, in cache blocks referred to cache lines, Size of the cache line, 16-KB = 1024 lines of 16 bytes 28

29 Memory Packaging and Types A single inline memory module (SIMM) holding 256 MB. Two of the chips control the SIMM. Or DIMM(Dual inline memory module ) has a row in each side 29

30 3. Secondary Memory Memory Hierarchies Afi five-level l memory hierarchy. h CPU registers.. 30

31 Magnetic Disks (1) A portion of a disk track. Two sectors are illustrated. Each sector has 512 data bytes, preamble to allow the head to be synchronized before reading and writing, ECC error correcting code 31

32 Magnetic Disks (2) A disk with four platters. The set of tracks at a given radial position is called a Cylinder, most disks rotate t

33 Magnetic Disks (3) Adi disk with ithfive zones. Each zone has many tracks.

34 IDE DISKS IDE :integrated drive electronics EIDE : extended d IDE EIDE drives and controller, controller has two channels, primary and secodary, allow 4 drives per controller ATA : advanced technology attachment, serial ATA transfer 150MB/sec

35 SCSI Disks Some of the possible SCSI (small computer system

36 RAID (1) Redundant Array of Inexpensive Disks RAID levels 0 through 2. Backup and parity disks are shown shaded.

37 RAID (1) Redundant Array of Inexpensive Disks RAID levels l 3 through h 5.

38 CD-ROMs (1), Optical disks Recording structure t of a Compact Disk or CD-ROM.

39 CD-ROMs (2) Logical data layout on a CD-ROM.

40 CD-Recordables Cross section of a CD-R disk and laser (not to scale). A CD-ROM has a similar structure, except without the dye layer and with a pitted aluminum layer instead of

41 DVD A double-sided, dual layer DVD (digital versatile disk). Smaller pits (.4 microns, red laser, double-sided 17 GB ) Successor to DVD is Blue-Ray, uses blue laser, shorter wavelength, double-sided 50 GB, data rate is 4.5 MB/s

42 Input/Output Buses (1) Physical structure t of a personal computer.

43 Input/Output Buses (2) Logical structure of a simple personal computer. PCI bus Each I/O device consists of two parts: one containing most of the electronics, called the controller, and one containing the I/O device itself, such as a disk drive

44 A controller that reads or writes data to or from memory without CPU intervention is said to be performing Direct Memory Access, better known by its acronym DMA When the transfer is completed, the controller normally causes an interrupt, forcing the CPU to suspend running its current program and start running a special procedure, called an interrupt handler BUSES, we have an old PC bus, called the ISA (Industry Standard Architecture) bus. EISA (Extended ISA) bus, The most popular of these now is the PCI (Peripheral Component Interconnect) What happens if the CPU and an I/O controller want to use the bus at the same time? The answer is that a chip called a bus arbiter decides who goes next. In general, I/O devices are given preference over the CPU the PCI bus has a bridge to the ISA bus AGP ( Accelerated Graphics port) bus. Allow more bandwidth from CPU AGP ( Accelerated Graphics port) bus. Allow more bandwidth from CPU to the video RAM

45 Input/Output Buses (3) A typical modern PC with a PCI bus and an ISA bus.

46 When a positive voltage is applied to the grid, the electrons are accelerated, causing the beam to hit the screen and make it glow briefly. When a negative voltage is used, the electrons are repelled, so they do not pass through the grid and the screen does not glow Terminals Computer terminals consist of two parts: a keyboard and a monitor when a key is depressed, an interrupt is generated and the keyboard interrupt handler (a piece of software that is part of the operating system) is started. The interrupt handler reads a hardware register inside the keyboard controller to get the number of the key (1 through 102) that was just depressed. When a key is released, a second interrupt is caused CRT (Cathode Ray Tube), monitor, (Color monitors have three electron guns, one each for red, green and blue.) To produce a pattern of dots on the screen, a grid is present inside the CRT.

47 CRT Monitors (a) Cross section of a CRT (b) CRT scanning pattern

48 LCD (Liquid Crystal Display) Liquid crystals are viscous organic molecules that flow like a liquid but also have spatial structure, like a crystal. the optical properties of the crystal depend on the direction and polarization of the incoming light. An LCD display screen consists of two parallel glass plates between which is a sealed volume containing a liquid crystal. Many kinds of LCD displays are in use, TN (Twisted Nematic) display, twisted crystal structure of the LCD molecules guides the light as it passes and rotates its polarization, making it come out horizontally. Thus in the absence of an electric field, the LCD screen is uniformly bright. By applying a voltage to selected parts of the plate, the twisted structure can be destroyed, blocking the light in those parts. Two schemes are commonly used for applying the voltage. In a (low-cost) passive matrix display, both electrodes contain parallel wires. active matrix display. It is considerably more expensive but it gives a better image so it is winning ground. Instead of just having two sets of perpendicular wires, it has a tiny switching element at each pixel position on one of the electrodes

49 Flat Panel Displays (a) The construction of an LCD screen. (b) The grooves on the rear and front plates are perpendicular to one another.

50 Mice Optical mouse: it has LED (Light Emitting Diode) and a photodetector on the bottom. The optical mouse is used on top of a special plastic pad containing a rectangular grid of closely spaced lines. As the mouse moves over the grid, the photodetector senses line crossings by seeing the changes in the amount of light being reflected back from the LED. Electronics inside the mouse count the number of grid lines crossed in each direction.

51 Telecommunications A pure sine wave transmits no information at all. varying the amplitude, frequency, or phase, a sequence of 1s and 0s can be transmitted, This process is called modulation. Amplitude p modulation two different voltage levels are used, for 0 and 1, respectively. frequency modulation,the voltage level is constant but the carrier frequency is different for 1 and 0. frequency shift keying. phase modulation,the amplitude and frequency do not change, but the phase of the carrier is reversed 180 degrees when the data switch from 0 to 1 or 1 to 0 The number of time intervals (i.e., the number of potential signal changes per second) is baud rate (symbols per second ). With 2 or more bits per interval, the bit rate will exceed the baud rate. Many people confuse these two terms. The device that accepts characters from a computer in the form of two-level signals, one bit at a time, and transmits the bits in groups of one or two, in amplitude-, frequency-, or phase-modulated form, is the modem. To mark the start and end of each character, an 8-bit character is normally sent preceded by a start bit and followed by a stop bit, making 10 bits in all.

52 Telecommunications a) Transmission of the binary number over a telephone line bit by bit. (a) Two-level signal. (b) Amplitude modulation. (c) Frequency modulation. b) (d) Phase modulation.

53 DSL(Digital Subscriber Lines (1)) Operation of ADSL. Asymmetric DSL, like having 250 modems 1.1 MHz divided into 256 channel, Hz each Ch 0 used for POTS( plain old telephone service) Ch 1-5 not used

54 Digital Subscriber Lines (2) A typical ADSL equipment configuration.

55 Internet over Cable (1) Frequency allocation in a typical cable TV system used for Internet access

56 Internet over Cable (2) Typical details of the upstream and downstream channels in North America. QAM-64 (Quadrature Amplitude Modulation) allows 6 bits/hz but only works at high frequencies. QPSK (Quadrature Phase Shift Keying) works at low frequencies but allows only 2 bits/hz.

57 Digital Cameras Adi digital it camera.

58 ASCII Character Codes (1) (American Standard Code for Information Interchange) The ASCII Character set: characters 0 31.

59 ASCII Character Codes (2) The ASCII Character set: characters Each ASCII character has 7 bits, allowing for 128 characters in all

60 UNICODE ASCII is fine for English but less fine for other languages. The first attempt at extending ASCII was IS 646, which added another 128 characters to ASCII, making it an 8-bit code called Latin-1. The next attempt was IS 8859, which introduced the concept of a code page, a set of 256 characters for a particular language or group of languages. UNICODE, Standard (IS 10646). The basic idea behind UNICODE is to assign every character and symbol a unique, permanent 16-bit value, called a code point. 16-bit symbols, UNICODE has 65,536 code points. Since the world s languages collectively use about 200,000 symbols