SDR SDRAM Controller Example

Transcription

1 SDR SDRAM Controller Example User Guide 10/2012 Capital Microelectronics, Inc. China

2 Contents Contents Introduction System Level Structure Interface at HyperTerminal Setting of HyperTerminal Usage of interface... 7 Revision History

3 1 Introduction This document describes an example that uses SDRAM IP, following is the detail of the example: Function - PC connects with 8051 through UART. User can send command to 8051 through the interface on PC; send testing start-address & end-address to FPGA User logic, so as to test writing and reading of SDRAM from start-address to end-address; - User logic write and read the memory cells of SDRAM and compare the read data with the previous write data and send the testing result back to The SDRAM IP is configured as below to meet the SDRAM-Chip: - data_width = 16; - row_addr_width = 12; - col_addr_width = 9; - bank_addr_width = 2. SDR SDRAM and User Logic all work at 133MHz 8051 core works at 95MHz UART works at baud rate Device: CME-M5, CME-M7, CME-HR3 3

4 2 System Level Structure Following is general structure of the example: PC UART 8051 CLK CKE CSn RASn User Logic SDR SDRAM Controller IP CASn WEn A SDR SDRAM Chip Clk_in PLL BA DQM DQ CME-M5(FPGA) Figure 2-1 System level structure of the example This case consists of 3 parts: PC, FPGA and SDRAM-Chip. PC Part connects with 8051 through UART, which is introduced at section 3. FPGA is the main controller, which contains 2 hard IPs(8051 and PLL), 1 soft IP(SDRAM-Controller-IP), and some user logic. The PLL has a 20MHz clock input, and generates a 95MHz clock to 8051, a 133MHz clock to FPGA user logic and SDRAM chip receives the command from PC and sends start address and end address to FPGA when FPGA is not busy. Then sends out test results to PC through UART serial port. FPGA user logic sends write/read command to SDRAM-Chip through SDRAM-Controller-IP. There is a FSM in user logic. After POR, FSM stays in IDLE state. When detects the start sample (start/end) address signal, FSM leaves IDLE state and active the busy output. After get the start address and end address from 8051, the FSM sends write request, start address and data to SDRAM-Controller-IP. The write request keeps active until write finish. Then the FSM sends read request and start address to SDRAM-Controller-IP and reads back all data. During the reading from SDRAM, user logic compares the read data with the previous written data. After read finish, FPGA sends the check result to 8051 and the FSM returns to IDLE state and de-actives the busy output. 4

5 Interface between 8051 and User logic: p3[6] --- busy, p3[7] --- error_occur, p3[4] --- load, p3[3:2] --- start sample address when being 2 b10, p2[7:0],p1[7:0],p0[7:0] bit address(start address or end address) 5

6 3 Interface at HyperTerminal Following shows the setting of HyperTerminal and usage of the interface. 3.1 Setting of HyperTerminal Steps of building a new connection of HyperTerminal with corresponding setting is shown as figures below: Figure 3-1 Build a new connection of HyperTerminal Figure 3-2 Select a port of UART (here COM1) 6

7 Figure 3-3 Configure baud-rate(19200) and bit-stream-control 3.2 Usage of interface After download or power-on, the HyperTerminal interface will display the information like Figure 3-4. Figure 3-4 HyperTerminal after download/power-on First, you can type help for the usage, this command will show the other two commands usage and format, as you see at figure 3-5; 7

8 Second, command mem <start_addr> <end_addr>, this command will test SDRAM from start address <start_addr> to end address <end_addr>, after FPGA gets the two addresses, user logic in FOGA will first write data to all the SDRAM memory cells between the two addresses, then read data back, and return a check result to 8051 and 8051 will send success or fail to the interface. Here <start_addr> or <end_addr> should be hexadecimal format starting with 0x, and with 6 hexadecimal characters after 0x. Third, command auto, it will test the default memory cells(from 0x to 0x7fffff) of sdram, this command is the same with mem 0x x7fffff. Figure 3-5 Commands with usage of the interface 8

9 Revision History Revision Date Comments Initial release 9