UART Design Example. User Guide. 04/2014 Capital Microelectronics, Inc. China

Transcription

1 UART Design Example User Guide 04/2014 Capital Microelectronics, Inc. China

2 Contents Contents Introduction System level structure EMIF interface application Single channel application Multiple channel application Design example function introduction AHB interface application Example Result EMIF interface example result AHB interface example result Pin and Design Source description Pin descriptions Pin assignments Design source Revision History

3 1 Introduction This document describes three examples that uses UART IP, two are of EMIF interface used on M5 device and one is of AHB interface used on M7A device. The two examples with EMIF interface are for single channel application and four channels application. In both applications, the function and basic configuration is the same. Function EMIF interface PC connects with 8051 through UART communicate with PC through UART IP can send data and receive data through UART IP in scan mode or interrupt mode AHB interface PC connects with ARM through UART. ARM communicate with PC through UART IP. ARM can send data and receive data through UART IP in scan mode or interrupt mode The UART IP is configured as below: EMIF interface BASE_ADDR = 23 h04_0000; Baud rate: Working mode: Mode 1 (asynchronous transmitter/receiver with 8 data bits and SRELH, SRELL baud rate generator is used) 8-bit width is selected In single channel application, the UART IP can work with fifo or with no fifo. But in multiple channels application it is recommended to configure the IP with fifo because without fifo data loss may occur when multiple channels receive data simultaneously. External interrupt 0 is used as UART s interrupt in single channel application. In multiple channels application, owing to existence of fifo in transmit/receive data path, there is no need for the IP to work in interrupt mode. As a result, interrupt resources are saved. AHB interface BASE_ADDR = 32 ha000_0000; Baud rate: Working mode: Mode 1 (asynchronous transmitter/receiver with 8 data bits and SRELH, SRELL baud rate generator is used) 8-bit width is selected In the application, the UART IP can work with fifo or with no fifo. External interrupt FP0 is used as UART s interrupt. 3

4 The examples works at FPGA Array logic:100mhz ARM Core:200MHz 8051 Core:100MHz Device: EMIF interface CME_M5 AHB interface CME_M7 4

5 2 System level structure 2.1 EMIF interface application Single channel application Following is general structure of the example design: 8051 EMIF tx 100M UART IP PC clk 20M PLL 100M rx CME_M5 Figure 2-1 System level structure of the single channel example PC Part connects with 8051 through UART. The PLL has a 20MHz clock input, and generates a 100MHz clock to 8051 and FPGA UART IP controls UART IP through EMIF interface can write and read UART IP s internal registers through EMIF operation. The differences between 8051 internal UART IP and the external UART IP are that: access internal UART IP through SFR (Special function register) bus. But 8051 access external UART IP through xdata operation (EMIF interface). Since the memory address need to access is more than 128K (0x20000), all xdata operation need to be implemented through data bank operation. 2. Interrupt handle is different has specific interrupt request input from internal UART IP. But for external UART IP, the interrupt request needs to be sent to 8051 through external interrupt inputs Multiple channel application Following is general structure of the example design: 5

6 8051 EMIF tx UART1 rx tx clk 20M PLL 100M 100M rx tx rx tx rx UART2 UART3 UART4 tx rx PC CME_M5 Figure 2-2 System level structure of multi-channel example There are 4 UART channels in example design: channel1~4. They are connected one by one. Channel 1 receives data from PC and sends to channel 2; Channel 2 receives data from channel 1 and sends to channel 3; Channel 3 receives data from channel 2 and sends to channel 4; Channel 4 receives data from channel 3 and sends to PC. For each UART, transmit and receive fifo are used to avoid data loss. And because of fifo, scan mode is selected so that interrupt resources can be saved. Note: For efficient control by software, the base address of the 4 UART IP should be set in order. In this example, base address for UART 1 is 0x40000, base address for UART 2 is 0x40020, base address for UART 3 is 0x40040, base address for UART 4 is 0x Design example function introduction This is the common part for single application and multi-channel application In the main function, there are transmit/receive test with 4 different configuration. The whole code contains five parts. (1) Serial port configuration (2) Transmit/receive test in scan mode, with no fifo Note: define FIFO_EN = 0 in system_top.v undefine FIFO_EN in UARTMan.h undefine BATCHRDEN in UARTMan.h (3) Transmit/receive test in interrupt mode, with no fifo Note: define FIFO_EN = 0 in system_top.v undefine FIFO_EN in UARTMan.h undefine BATCHRDEN in UARTMan.h 6

7 (4) Transmit/receive test in interrupt mode, with fifo Note: define FIFO_EN = 1 in system_top.v define FIFO_EN in UARTMan.h undefine BATCHRDEN in UARTMan.h(general data read mode) define BATCHRDEN in UARTMan.h(batch data read mode) (5) Transmit/receive test in scan mode, with fifo Note: define FIFO_EN = 1 in system_top.v define FIFO_EN in UARTMan.h undefine BATCHRDEN in UARTMan.h Among (2), (3), (4) and (5), when one of the four parts of code is executed, the other three should be converted to comment text. The following diagram shows the design example function. Open UART (set work mode, baud rate) UART send test (send A0~AF) Receive data From PC? N Y UART send data received Figure 2-3 Example design function As is shown in the diagram, in this example, 1 First to open the UART, 8051 configures UART IP internal registers through EMIF interface to set UART working mode and baud rate, here mode 1 and baud rate are used. 2 UART sends out 1 group of 0xA0~0xAF data to PC in scan mode. UART IP waits for PC send out data. After get 1 byte of data, UART will send out this byte to PC to confirm whether received data are correct. 7

8 2.2 AHB interface application Following is general structure of the example design: ARM AHB tx 200M UART IP PC clk 20M PLL 100M rx CME_M7 Figure 2-4 System level structure of AHB interface example This case consists of 3 parts as shown in above figure: PLL, SOC(ARM) and UART IP 1. PLL(generated by Wizard): a) In the example on M7, this part has an input of 20MHz and provides the clock 200MHz and 100MHz,the former is used by ARM and the latter is used in FPGA logic. The block can be configured as the figure 2-5 below in the Primace software by Wizard tool. In the example on M7,on the page2, PLL location is set ''2''. Figure 2-5 PLL block configuration of example on M7 8

9 2. SOC(ARM)(generated by Wizard): a) This part is an ARM M3 processor core in the example on M7, which contains two AHB bus,ahb0 and AHB1. In the example, FPGA logic connects with the AHB0 slave interface. b) It is configured as the figure 2-6(a), 2-6(b), 2-6(c). Figure 2-6(a) select peripherals Figure 2-6(b) set clock 9

10 Figure 2-6(c) set hex file c) The c code in the firmware file "main.c" is used to achieve the function of accessing the UART IP on FPGA. The function flow as figure 2-7. In the main function, the configuration as below (1) Serial port configuration set work mode 1 and baud rate (2) Transmit/receive test in interrupt mode, with fifo Note: define FIFO_EN = 1 in system_top.v(fpga logic) define FIFO_EN in UARTMan.h define BATCHRDEN in UARTMan.h(batch data read mode) (3) Set internal register value Note: define OVERTIMETH 0x00104b00 in UARTMan.h define RCVFIFOTH 0x4 in UARTMan.h 10

11 ARM function GPIO init FPGA logic Generate reset signal to FP logic and config internal register FP logic get reset signal and generate the interrupt signal Open UART (set work mode,band rate) UART send test (send A0 ~ AF) Receive data from PC? N Y UART send data received Figure 2-7 firmware flow of example on M7 3. UART IP(generated by Wizard) a) This block is generated by Primace Wizard, which is of batch read function with interrupt and with fifo. b) It can be configured as figure 2-8 below. Figure 2-8 UART IP configuration 11

12 3 Example Result 3.1 EMIF interface example result Figure 3-1 UART transmission test results Figure 3-2 UART reception test results 12

13 3.2 AHB interface example result Figure 3-3 example on M7 test results Because the RCVFIFOTH value is 0x4 in UARTMan.h, the so the result is as Figure 3-3, if the data number is less than 4 or not the integral number of 4, the data will be received till the time is up to OVERTIMETH value defined in UARTMan.h. 13

14 4 Pin and Design Source description User Guide of UART design example 4.1 Pin descriptions Table 4-1 The uart example of emif interface on M5 top module pin description Name Direction Width Description clk_i Input 1 Clock input (20MHz) rs232_rx0 Input 1 Reveive data input rs232_tx0 output 1 Transmit data output Table 4-2 The uart example of ahb interface on M7 top module pin description Name Direction Width Description clk_i Input 1 Clock input (20MHz) rs232_rx0 Input 1 Reveive data input rs232_tx0 output 1 Transmit data output rst_uart_flag output 1 Indicate uart reset signal led output 2 Indicate interrupt signal 4.2 Pin assignments The following figure 4-1 shows the detail pin assignments in IO Editor of Primace 14

15 Figure 4-1 IO pin assignment on M7 Figure 4-2 IO pin assignment on M5 4.3 Design source The UART example RTL source files are shown in table 4-3 and table 4-4. Table 4-3 The UART example s source files description on M7 File src\ \uart_v3.v \system_top.v \mysystem.v Description Directory for project source coded UART IP module, generated through IP wizard UART IP test top module, user can change this RTL according real application requirement Hard ARM IP core, generated through IP wizard 15

16 \MyPll.v Hard PLL IP core, generated through IP wizard \firmware \UARTMan.h \UART.c \main.c Directory for ARM firmware Header file for external UART IP, including function declaration, basic setting Source code for external UART IP, including basic UART setting, UART transmission and reception function Main code for UART test, including GPIO initiate, sending and receiving test in both scan and interrupt working mode Table 4-4 The UART example s source files description on M5 File src\ \serial_core.v \emif_uart_fifo_ctl.v \emif_uart_top.v \uart_fifo.v \syn_fifo.v \emb_uart_m5.v \system_top.v \mysystem.v \MyPll.v Description Directory for project source coded UART core control module, encrypted UART/FIFO control model with EMIF interface, encrypted Top module of the UART IP with EMIF interface, encrypted Top module of FIFO, encrypted Control module of EMB5K, encrypted EMB5K related code of M5 device UART IP test top module, user can change this RTL according real application requirement Hard 8051 IP core, generated through IP wizard Hard PLL IP core, generated through IP wizard \firmware \UARTMan.h \UARTMan.c \main.c Directory for 8051 firmware Header file for external UART IP, including function declaration, basic setting Source code for external UART IP, including basic UART setting, UART transmission and reception function Main code for UART test, including sending and receiving test in both scan and interrupt working mode 16

17 Revision History Revision Date Comments Initial release Upgrade for 5,6,7,8-bit width & fifo support Batch data read and reception overtime control support Add AHB interface 17