High Performance Multiprocessor System

Transcription

1 High Performance Multiprocessor System Requirements : - Large Number of Processors ( 4) - Large WriteBack Caches for Each Processor. Less Bus Traffic => Higher Performance - Large Shared Main Memories (128MB - 1GB) MIPS ARCHITECTURE MEETS THESE REQUIREMENTS RESULT : RISC PROCESSOR IN MOST MP SYSTEMS SHIPPED TODAY - Ardent, ermi, RC, SGI are announced - Several designs yet to announce 8/14/91 multiprocessing - 1

2 MIPS MULTIPROCESSOR SUPPORT -ARCHITECTURAL SUPPORT - PHYSICAL - ARCHITECTURAL PARTITIONING WELL SUITED OR MP - ON-CHIP CONTROL AND MMU - O-CHIP SEAMLESS P - TOTAL 128 K BYTE PER PROCESSOR -R3000HARDWARE SUPPORT OR COHERENCE Snooper watches Bus transactions If Address matches with any cache entry: MP_STALL STALLS THE PROCESSOR MP _INVALIDATE SIGNAL CAUSES CPU TO WRITE THE LOCATION AS INVALID. 8/14/91 multiprocessing - 2

3 LOW COST DESIGN - DUPLICATE TAG RAMS OR SNOOPING - WRITE THROUGH S - SNOOPER COMPARES WRITE ADDRESSES IN DUPLICATE TAG - I MATCHES, MP_STALL ASSERTED - ENTRY INVALIDATED OR THAT ENTRY 8/14/91 multiprocessing - 3

4 MP DESIGN - 1 READ R3000 BUER BUS I- WRITE BUER D- B U E B U E R R D- READ BUER R3000 WRITE BUER I- 2ND D-TAG 2ND D-TAG SNOOPER MP BUS SNOOPER 8/14/91 multiprocessing - 4

5 SNOOPER LOGIC DATA ADDRESS MP BUS SECONDARY OE* INDEX LATCH 1 LATCH 2 TAG DATA TAG COMPARATOR COMPARATOR MP INVALIDATE MPSTALL 8/14/91 multiprocessing - 5

6 HIGH PERORMANCE MP DESIGN - TWO LEVELS O - WRITE THROUGH PRIMARY - WRITE BACK SECONDARY - EXTERNAL WRITE BACK LOGIC AND SNOOP CONTROL 8/14/91 multiprocessing - 6

7 MP DESIGN - 2 READ R3000 BUER BUS I- WRITE BUER D- B U E B U E R R D- READ BUER R3000 WRITE BUER I- SECONDARY & CONTROL SECONDARY & CONTROL SNOOPER SNOOPER MP BUS 8/14/91 multiprocessing - 7

8 WRITE BACK LOGIC EACH BLOCK IN SECONDARY IN ONE O 4 STATES : WRITE HIT : I STATE == DIRTY, THEN WRITE TO INVALID : NO DATA I STATE == RESERVED VALID : CLEAN, POTENTIALLY SHARED THEN 1. WRITE TO RESERVED : WRITTEN JUST ONCE, WRITTEN THROUGH'D 2. CHANGE STATE TO DIRTY TO MAIN MEMORY AND ONLY COPY IN ANY I STATE == VALID THEN 1. WRITE THROUGH TO MAIN MEMORY DIRTY : WRITTEN MORE THAN ONCE AND 2. CHANGE STATE TO RESERVED ONLY COPY IN ANY SNOOP CONTROLLERS OR OTHER S: READ MISS : I THE ENTRY MATCHES, INVALIDATE THE I SNOOP CONTROLLERS IND THE BLOCK IN ANOTHER THEN I STATE == DIRTY THEN 1. SUPPLY THE DATA 2. WRITE TO MEMORY 3. CHANGE STATE TO VALID I STATE == RESERVED THEN 1. SUPPLY THE DATA 2. CHANGE STATE TO VALID I STATE == VALID THEN SUPPLY THE DATA ELSE READ ROM MEMORY WRITE MISS : I SNOOP CONTROLLER INDS A COPY IN ANOTHER THEN I STATE == DIRTY THEN 1. SUPPLY THE DATA TO THE 2. INVALIDATATES ITS COPY 3. ATER LOADING THE BLOCK, CHANGE STATE TO DIRTY ELSE LOAD THE BLOCK ROM MEMORY AND CHANGE STATE TO DIRTY SNOOP CONTROLLERS OR OTHER S, I IND THE COPY, INVALIDATES THE BLOCK 8/14/91 multiprocessing - 8

9 MP DESIGN - 2 SECOND LEVEL DESIGN 1. ASSUME IRST LEVEL IS WRITE THRU AND SECOND LEVEL IS WRITE BACK 2. BOTH IRST AND SECOND LEVEL S ARE PHYSICALLY ADDRESSED (NO REVERSE TRANSLATION NEEDED) 3. MAIN MEMORY READS AND WRITES ALWAYS GO THROUGH THE SEC- OND LEVEL (NOT THE WRITE BUERS) 4. IRST AND SECOND LEVEL S MAINTAIN COHERENCY. IRST LEVEL IS A SUBSET O THE SECOND LEVEL 5. PROCESSOR GETS DATA ROM THE ASTER IRST LEVEL I IT HITS 8/14/91 multiprocessing - 9

10 MP DESIGN - 2 COHERENCY PROTOCOL THE ILLINOIS SCHEME IS USED - WRITE INVALIDATE IRST LEVEL HAS 2 STATES VALID, INVALID SECOND LEVEL HAS 4 STATES INVALID PRIVATE CLEAN (UNMODIIED, ONLY COPY) SHARED CLEAN (UNMODIIED, POSSIBLY OTHER COPIES) DIRTY ( MODIIED, ONLY COPY, WRITE BACK TO MAIN MEM- ORY) 8/14/91 multiprocessing - 10

11 ILLINOIS SCHEME STATE DIAGRAM READ MISS PRIVATE (ROM MEMORY) INVALID CLEAN BUS WRITE MISS BUS WRITE MISS WRITE HIT BUS READ MISS READ MISS (ROM ) WRITE HIT DIRTY BUS READ MISS WRITE MISS PROCESSOR-BASED TRANSITION BUS-INDUCED TRANSITION SHARED CLEAN BUS READ MISS 8/14/91 multiprocessing - 11

12 ESTIMATED PARTS LIST READ BUER : CT374A WRITE BUER : MIPS R3020 OR CT521 IO'S ROM IDT PRIMARY I & D : 64K X 1 SECONDARY D : 8K X 8 WRITE BACK LOGIC : APPROX 10 PALS SNOOPER LOGIC : 1 BUER 1 COMPARATOR 2 PALS APPROXIMATE BOARD SPACE : 100 Square inches per processor module 8/14/91 multiprocessing - 12

13 Multiprocessor System Shipping Today Dual Processor Board 2 Modules IC's, 15" x 15" Module Module CPU PU 64KB I-Cache 64KB D-Cache (16K x 4's) Rd/Wr Buffers CPU PU 64KB I-Cache 64KB D-Cache (16K x 4's) Rd/Wr Buffers 64KB Secondary Cache (8K x 8's, to be 32K x 8's) Snoopy Logic Write Back Logic 64KB Secondary Cache (8K x 8's, to be 32K x 8's) Snoopy Logic Write Back Logic Common Bus Interface Logic 8/14/91 multiprocessing - 13

14 MIPS MULTIPROCESSOR SUMMARY MINIMUM LOGIC NEEDED TO PROVIDE SUPPORT WITHOUT PENALIZ- ING UNIPROCESSORS. EXISTENCE PROO: MP SYSTEMS SHIPPING TODAY BY MULTIPLE VEN- DORS. ARCHITECTURAL AND HARDWARE SUPPORT: - PHYSICAL, USEUL PARTITIONING, LARGE S PLUS... - TWO SIGNALS ALLOW THE CPU TO CONTROL THE AT HIGH CLOCK RATES & ALSO INVALIDATE WHEN SNOOPING DETECTS A HIT. LEXIBLE MP SYSTEM CONIGURATIONS: - SUPPORTS MINIMUM SYSTEM WITH DUPLICATE TAGS AND LARGE SYSTEMS WITH SECONDARY S. 8/14/91 multiprocessing - 14