PIC18F6XK22/PIC18F8XK22

Transcription

1 PIC18F6X22/PIC18F8X22 to PIC18F6XK22/PIC18F8XK22 Migration Guide INTRODUCTION The PIC18F87K22 family is an extension of Microchip s PIC18F8722 family. This family combines the traditional advantages of all PIC18 microcontrollers namely, high computational performance and a rich feature set with an extremely competitive price point. These features make the PIC18F87K22 family a logical choice for many high-performance applications where the price is a primary consideration. Differentiating features of the newer device include: Extended operating voltage range XLP technology A Charge Time Measurement Unit (CTMU) A Real-Time Clock Calendar (RTCC) A configurable 12-bit Analog-to-Digital (A/D) Converter An increased number of Capture/Compare/PWM modules (CCPs) An increased number of timers, some with gated timer feature This document highlights the similarities and differences between the PIC18F8722 and PIC18F87K22 families. It also covers the general principles for migrating PIC18F8722 family applications to the PIC18F87K22 family. This document is structured like a data sheet, as shown at right, with each section focusing on a peripheral or major feature. Each section contains the following information, as applicable: A table comparison of PIC18F8722 and PIC18F87K22 family peripheral features A table comparing bit names for each function A list of new PIC18F87K22 family features A list of unsupported PIC18F8722 family features A summary of migration considerations Users are encouraged to review the PIC18F87K22 Family Data Sheet (DS39960) for information on the new modules and how they may be used in applications that are candidates for migration (See References). CONTENTS Device Overview... 2 Power-Managed Modes/ Oscillator Configurations... 5 Resets... 7 Flash Program Memory/Data EEPROM Memory x8 Hardware Multiplier... 8 Interrupts... 8 I/O Ports... 9 Timers Capture/Compare/PWM (CCP) Enhanced Capture/Compare/PWM (ECCP) Master Synchronous Serial PORT (MSSP) I2C 14 Master Synchronous Serial PORT (MSSP) SPI Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Bit Analog-to-Digital Converter (A/D) Analog Comparator Module Comparator Voltage Reference Module High/Low-Voltage Detect (HLVD) VREG Package Information Summary References Document Revision History Microchip Technology Inc. DS01431A-page 1

2 DEVICE OVERVIEW The PIC18F87K22 is a new family with low-power features and XLP technology. This family of devices is available in 64-pin and 80-pin packages and are largely pin compatible with the PIC18F8722 family for easy migration. Some additional features and improvements on existing features are available for the PIC18F87K22 family. Table 1 compares feature differences between the 64-pin devices of the PIC18F6X22 and PIC18F6XK22 families. Table 2 compares 80-pin devices of the PIC18F8X22 and PIC18F8XK22 families. TABLE 1: COMPARISON BETWEEN PIC18F6X22 AND PIC18F6XK22 64-PIN DEVICES Feature Description PIC18F6X22 PIC18F6XK22 Maximum Operating Frequency 40 MHz 64 MHz Operating Range 2.0V to 5.5V 1.8V to 5.5V XLP No Maximum Program Memory 64 Kbytes/32,768 Instructions (PIC18F6622) 64 Kbytes/32,768 Instructions (PIC18F66K22) 128 Kbytes/65,536 Instructions (PIC18F6722) 128 Kbytes/65,536 Instructions (PIC18F67K22) Maximum Data Memory 3,936 bytes 3,936 bytes Data EEPROM Memory 1,024 bytes 1,024 bytes Interrupt Sources I/O Ports Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Internal Weak Pull-up PORTB PORTB, PORTD, PORTE Selectable EC and HS Oscillator Power No EC with three power selections for 3 frequency ranges HS with two power selections for 2 frequency ranges Selectable SOSC Oscillator Power No High-Power/Digital/Low-Power Oscillator Option for SOSC T1CKI and T1OSCI Pins T1CKI and T1OSCI are implemented on two separate pins T1CKI and T1OSCI are multiplexed on the same pin INTOSC Up to 8 MHz Up to 16 MHz REFO No RTCC No Timers/Gated Timers 5/0 11/4 ECCP/CCP 3/2 3/7 EUSART/MSSP 2/2 2/2 Internal Regulator No Low-Power BOR No Peripheral Module Disable (PMD) No A/D Converter Non-Differential, 10-bit with 12 I/P Channels Differential, 12-bit with 16 I/P Channels CTMU No On-Chip Temperature Sensor No Analog Comparators Two Three Ultra Low-Power Wake-up (ULPWU) No WDT Prescaler Options DS01431A-page 2 Preliminary 2012 Microchip Technology Inc.

3 TABLE 2: COMPARISON BETWEEN PIC18F8X22 AND PIC18F8XK22 80-PIN DEVICES Feature Description PIC18F8X22 PIC18F8XK22 Maximum Operating Frequency 40 MHz 64 MHz Operating Range 2.0V to 5.5V 1.8V to 5.5V XLP No Maximum Program Memory 64 Kbytes (PIC18F8622) 64 Kbytes (PIC18F86K22) 128 Kbytes (PIC18F8722) 128 Kbytes (PIC18F87K22) Program Memory 32,768 Instructions (PIC18F8622) 32,768 Instructions (PIC18F86K22) 65,536 Instructions (PIC18F8722) 65,536 Instructions (PIC18F87K22) Maximum Data Memory 3,936 bytes 3,936 bytes Data EEPROM Memory 1,024 bytes 1,024 bytes Interrupt Sources I/O Ports Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Internal Weak Pull-up PORTB PORTB, PORTD, PORTE, PORTJ Selectable EC and HS Oscillator power No EC with three power selections for 3 frequency ranges HS with two power selections for 2 frequency ranges Selectable SOSC Oscillator Power No High-Power/Digital/Low-Power Oscillator Option for SOSC T1CKI and T1OSCI Pins T1CKI and T1OSCI are implemented on two separate pins T1CKI and T1OSCI are multiplexed on the same pin INTOSC Up to 8 MHz Up to 16 MHz REFO No RTCC No Timers/Gated Timers 5/0 11/4 ECCP/CCP 3/2 3/7 EUSART/MSSP 2/2 2/2 Peripheral Module Disable (PMD) No A/D Converter Non-Differential, 10-bit with 16 I/P Channels Differential, 12-bit with 24 I/P Channels CTMU No On-Chip Temperature Sensor No Internal Regulator No Low-Power BOR No Comparators Two Three Ultra Low-Power Wake-up (ULPWU) No WDT Prescaler Options New PIC18F87K22 Family In addition to the rich feature set of the PIC18F8722 family, the following new features are available to improve flexibility and reduce the CPU overhead: Oscillator Options There are new oscillator options that allow three different power levels for External Clock modes and two power levels for High-Speed Crystals/Resonator mode, with operating speed up to 64 MHz. Secondary Oscillator The secondary oscillator allows for a High-Power mode, Low-Power mode and a Digital Input mode. Internal Oscillator The internal oscillator block now has three power-managed modes and is capable of up to 16 MHz operation. Configurable Reference Clock Output The device clock with configurable prescaler is available for output to eliminate additional oscillators for other components Microchip Technology Inc. DS01431A-page 3

4 Open-Drain Output The output pins for several peripherals can be configured as open-drain outputs. Internal Pull-up Resistors In addition to internal pull-up in PORTB of the PIC18F8722 family, PORTD and PORTE pins in PIC18F6XK22 devices and PORTD, PORTE and PORTJ pins in PIC18F8XK22 devices have internal weak pull-up resistors that can be enabled. Hardware Real-Time Clock and Calendar (RTCC) The RTCC module is a 100-year clock and calendar with automatic leap year detection. The module is intended for applications where accurate time must be maintained for extended periods with minimum to no intervention from the CPU. The module is optimized for low-power usage in order to provide extended battery life while keeping track of time. Gated Timer Functionality enabling the 16-bit timers to increment based on either of the comparator outputs, when TMR2 matches PR2, or an external pin input. Capture/Compare/PWM Module Five additional CCP modules have been added. A/D Converter The A/D module has been improved with 12 bits of resolution as well as allowing a differential Input mode and up to 16 input channels for the PIC18F6XK22 family and 24 input channels for the PIC18F8XK22 family. Charge Time Measurement Unit (CTMU) The charge time measurement unit interfaced with the A/D module allows implementation of many applications, such as capacitive touch buttons and sliders. Low-Power BOR The Brown-out Reset module has a range of four power-saving options. Watchdog Prescaler Options The Watchdog Timer has five additional prescaler options, allowing periods of up to 4,194s (approximately 70 minutes). Ultra Low-Power Wake-up (ULPWU) A lowpower Sleep mode using a slow falling voltage on an analog pin to trigger a wake-up. On-Chip Regulator Unlike PIC18FXX22 devices, PIC18FXXK22 devices require two supply voltages for operation, up to 5.5V for I/Os and peripherals and up to 3.3V for core and memory. To enable single supply design an on-chip 3.3V regulator is provided which can power the core and memory. Peripheral Module Disable (PMD) The PIC18F87K22 family allows peripheral modules to be selectively disabled, reducing or eliminating their power consumption. Setting the PMD bit, for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. There are four PMD registers in the PIC18F87K22 family, (i.e., PMD0, PMD1, PMD2 and PMD3). These registers have bits associated with each module for disabling or enabling a particular peripheral. PMD is available for CCP, timer, comparator, PSP, CTMU, RTCC, EMB, EUSART, MSSP and A/D modules. Each section contains a subsection with this heading that specifies which of its features are supported by the PIC18F8722 family, but not by the PIC18F87K22 family. While migrating from the PIC18F8722 family to the PIC18F87K22 family, users should consider: The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. When the regulator is enabled, the PIC18F87K22 family requires a low-esr (< 5Ω) capacitor on the VCAP/ VDDCORE pin to stabilize the voltage regulator output. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 µf connected to ground. When the regulator is disabled, the VCAP/VDDCORE pin must be tied to a 0.1 µf capacitor connected to ground. The PGM pin is not available within the PIC18F87K22 family. For more information on low-voltage programming and high-voltage programming, refer to the PIC18F6XKXX/8XKXX Family Flash Microcontroller Programming Specification (DS39947). The VDD Pin No.10 (PIC18F6XK22)/Pin No.12 (PIC18F8XK22) has been replaced with the VDDCORE/VCAP pin, hence care should be taken for the appropriate connection to the VDDCORE/ VCAP pin. PORTF<0> is not available and the corresponding pin has been replaced by ENVREG. The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the setting in PIC18F8XK22 devices of the ECCPMX Configuration bit (CONFIG3H<1>). The PIC18F87K22 family is available in the same package as the PIC18F8722 family, i.e., - 64-pin TQFP and - 80-pin TQFP Due to the additional features within this family, some PIC18F8XK22/PIC18F6XK22 pins may have more functions than compared to PIC18F8X22/PIC18F6X22 pins. DS01431A-page 4 Preliminary 2012 Microchip Technology Inc.

5 POWER-MANAGED MODES/ OSCILLATOR CONFIGURATIONS New oscillator features have been added to the PIC18F87K22 family which increase the system clock frequency and clock options while reducing power consumption. Maximum system clock frequency has increased from 40 MHz for the PIC18F8722 family to 64 MHz for the PIC18F87K22 family. New power modes are introduced in HS and EC Oscillator modes. An Ultra Low-Power Wake-up, an inexpensive feature that provides a low-power technique for periodically waking up the device from Sleep mode, is supported. Table 3 shows the power-managed modes/oscillator configurations comparison between the PIC18F8722 and PIC18F87K22 families. Table 4 shows the power-managed modes/oscillator configurations bit naming conventions and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 3: COMPARISON OF PIC18F6X22/PIC18F8X22 AND PIC18F6XK22/PIC18F8XK22 POWER-MANAGED MODES/OSCILLATOR CONFIGURATIONS Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Maximum Operating Frequency 40 MHz 64 MHz Internal Oscillators 2 (8 MHz and 31 khz) 3 (16 MHz, 512 khz and 31 khz) External Clock Power modes One Three Secondary Oscillator Power modes One Two HS Oscillator Power modes One Two PLL Input Frequency Range 4 MHz to 10 MHz 4 MHz to 16 MHz INTOSC Tuning bits Five Six INTOSC + PLL Frequency Range 16 MHz 32 MHz 16 MHz 32 MHz 64 MHz LP Operating Frequency 5 khz to 200 khz 32 khz EC Operating Frequency 0 to 40 MHz 0 to 64 MHz Default INTOSC Frequency 1 MHz 8 MHz TABLE 4: POWER-MANAGED MODES/OSCILLATOR CONFIGURATIONS BIT NAMING CONVENTION AND FUNCTIONALITY Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 INTOSC Stable Output Status IOFS (OSCCON<2>) HFIOFS (OSCCON<2>) MFIOFS (OSCCON<1>) Secondary Oscillator Status T1RUN (T1CON<6>) SOSCRUN (OSCCON2<6>) Oscillator Start-up Time-out Status bit OSTS (OSCCON<3>) OSTS (OSCCON<3>) INTOSC Frequency Tuning TUN<4:0> (OSCTUNE<4:0>) TUN<5:0> (OSCTUNE<5:0>) Internal Oscillator Frequency Value IRCF<2:0> (OSCCON<6:4>) 000 (31 khz) 001 (125 khz) 010 (250 khz 011 (500 khz) 100 (1 MHz) 101 (2 MHz) 110 (4 MHz) 111 (8 MHz) 000 (31 khz) 001 (250 khz) 010 (500 khz) 011 (1 MHz) 100 (2 MHz) 101 (4 MHz) 110 (8 MHz) 111 (16 MHz) Secondary Oscillator Enable T1OSCEN (T1CON<3>) SOSCEN (T1CON<3>) 2012 Microchip Technology Inc. DS01431A-page 5

6 TABLE 4: External Clock mode (CONFIG1H<3:0>) FOSC = 0101 FOSC = 0101 (16 MHz to 64 MHz) FOSC = 1011 (160 khz to 16 MHz) FOSC = 1101 (DC to 160 khz) External Clock mode with CLKOUT FOSC = 0100 FOSC = 0100 (16 MHz to 64 MHz) FOSC = 1010 (160 khz to 16 MHz) FOSC = 1100 (DC to 160 khz) High-Speed Crystal mode FOSC = 0010 (HS) FOSC = 0110 (HSPLL) FOSC = 0010 (16 MHz to 25 MHz) FOSC = 0011 (4 MHz to 16 MHz) Medium Speed (XT) Crystal mode FOSC = 0001 FOSC = 0001 Low-Power (LP) Crystal mode FOSC = 0000 FOSC = 0000 External RC Oscillator mode FOSC = 11xx FOSC = 0111 External RC Oscillator mode with CLKOUT FOSC = 101x FOSC = 0110 Internal Oscillator mode FOSC = 1000 FOSC = 1000 Internal Oscillator mode with CLKOUT POWER-MANAGED MODES/OSCILLATOR CONFIGURATIONS BIT NAMING CONVENTION AND FUNCTIONALITY (CONTINUED) Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 FOSC = 1001 FOSC = 1001 Internal Oscillator PLL Enable PLLEN (OSCTUNE<6>) PLLEN (OSCTUNE<6>) New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family to optimize the power consumption and increase system clock flexibility: Maximum operation frequency increased from 40 MHz to 64 MHz External clock oscillator has three power modes: - Low-Power mode (FOSC 160 khz) - Medium-Power mode (160 khz FOSC 16 MHz) - High-Power mode (16 MHz FOSC 64 MHz) Internal oscillator has three sources with the following frequency ranges: - Low-Frequency LF-INTOSC (31.25 khz) - Medium-Frequency MF-INTOSC (31.25 khz to 500 khz) - High-Frequency HF-INTOSC (31.25 khz to 16 MHz) Secondary oscillator has three run modes - Low-Power SOSC mode - Digital (SCLKI) mode - High-Power SOSC mode The Ultra Low-Power Wake-up feature provides an inexpensive solution for extended wake-up times using an external capacitor A dedicated PLL enable bit is available for all clock sources capable of 4 MHz operation All PIC18F8722 family oscillator features and powermanaged modes are supported by the PIC18F87K22 family. While migrating from the PIC18F8722 to the PIC18F87K22 family, users should consider: New bit and register locations for primary and secondary oscillator features New low-power modes to reduce power consumption Increased number of INTOSC tuning bits Changes made to supported Crystal mode frequency ranges New default internal oscillator frequency DS01431A-page 6 Preliminary 2012 Microchip Technology Inc.

7 RESETS The PIC18F87K22 family supports Configuration Mismatch (CM) Reset, in addition to all of the PIC18F8722 family Resets. Table 5 shows the Reset comparisons between the PIC18F8722 and PIC18F87K22 families. TABLE 5: Feature Description COMPARISON OF RESETS PIC18F6X22/ PIC18F8X22 PIC18F6XK22/ PIC18F8XK22 Configuration No Mismatch (CM) Reset Power-on Reset (POR) MCLR During Normal Operation MCLR During Power-Managed modes WDT Reset Programmable BOR RESET Instruction Stack Full/ Underflow Reset BOR Trip Voltages (V) Number of BOR Power Levels One Four New PIC18F87K22 Family The Configuration Mismatch (CM) Reset is a new feature of the PIC18F87K22 family that is designed to detect and attempt to recover from random, memory corrupting events. These include Electrostatic Discharge (ESD) events that can cause widespread, single bit changes throughout the device and result in catastrophic failure. In the PIC18F87K22 family, the device Configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>). The state of the bit is set to 0 whenever a CM event occurs. The bit does not change for any other Reset event. The affect of a CM Reset is similar to a MCLR Reset, RESET instruction, WDT time-out or Stack Event Resets. All the above Resets and Power-on Reset cause the Configuration Words shadow registers to be reloaded from the programmed Configuration Word locations. All PIC18F8722 family Reset functions are supported by the PIC18F87K22 family. Though all PIC18F8722 family Reset features are supported by the PIC18F87K22 family, changes made in the BOR Reset trip point should be considered. These values have been modified to support the PIC18F87K22 family s lower voltage operation. Table 6 shows the Reset bit naming conventions and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 6: RESETS BIT NAMING CONVENTION AND FUNCTIONALITY Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Configuration Mismatch (CM) N/A CM (RCON<5>) Reset Detection Flag BOR Trip Point Selection BORV<1:0> (CONFIG2L<4:3>) BORV<1:0> (CONFIG2L<4:3>) BOR Enable BOREN<1:0> (CONFIG2L<2:1>) BOREN<1:0> (CONFIG2L<2:1>) Power-up Timer Enable PWRTEN (CONFIG2L<0>) PWRTEN (CONFIG2L<0>) BOR Software Enable SBOREN (RCON<6>) SBOREN (RCON<6>) Reset STATUS Register RCON RCON Stack Error Reset Enable STVREN (CONFIG4L<0>) STVREN (CONFIG4L<0>) 2012 Microchip Technology Inc. DS01431A-page 7

8 FLASH PROGRAM MEMORY/DATA EEPROM MEMORY The differences between the PIC18F8722 and PIC18F87K22 families are a few interrupt flag bit locations. The sizes of the program memory and data EEPROM are the same in both families. Table 7 shows the Flash Program Memory/Data EEPROM Memory bit naming comparison between the PIC18F8722 and PIC18F87K22 families. TABLE 7: Functionality Data EEDATA/ Flash Write Operation Interrupt Enable EE Interrupt Priority Data EEDATA/ Flash Write Operation Interrupt Flag New PIC18F87K22 Family None. FLASH PROGRAM/DATA EEPROM BIT NAME COMPARISON PIC18F6X22/ PIC18F8X22 EEIE (PIE2<4>) EEIP (IPR2<4>) EEIF (PIR2<4>) The maximum Boot Block size that can be configured in the PIC18F87K22 family is 4 Kbytes while in the PIC18F8722 family is 8 Kbytes. PIC18F6XK22/ PIC18F8XK22 EEIE (PIE6<4>) EEIP (IPR6<4>) EEIF (PIR6<4>) While migrating from the PIC18F8722 to the PIC18F87K22 family, the changed register locations and new positions of the EEIE, EEIP and EEIF bits must be addressed. Since the register locations have changed, this will require a code change for both assembler and compiler development tools. The execution of a write or erase of Flash program memory in the PIC18F87K22 family writes or erases memory blocks of 128 bytes. While in the PIC18F8722 family it writes or erases memory blocks of 64 bytes. The Boot Block size in the PIC18F87K22 family can be configured as 2 or 4 Kbytes. While in the PIC18F8722 family it can be configured as 2, 4 or 8 Kbytes. Therefore, two bits (CONFIG4L<5:4>) are used to select the Boot Block size in the PIC18F8722 family and only one bit (CONFIG4L<4>) in the PIC18F87K22 family. 8X8 HARDWARE MULTIPLIER There are no differences between the PIC18F8722 and the PIC18F87K22 families hardware multiplier. INTERRUPTS The PIC18F87K22 family has increased the number of interrupts for better control of peripherals and external events through the port pins. (See the bold text in Table 8). There are some changes in bit names of interrupt control and status SFRs. This section covers interrupts associated with the core functions. TABLE 8: Feature Description Interrupt Flag Registers Interrupt Enable Registers Interrupt Priority Registers INTERRUPTS COMPARISON PIC18F6X22/ PIC18F8X22 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 New PIC18F87K22 Family Timer gate interrupts, CTMU interrupt, RTCC interrupt, Interrupts due to additional CCP, comparators and timers have been added to the PIC18F87K22 family core interrupt suite. All PIC18F8722 family interrupt features are supported by the PIC18F87K22 family. PIC18F6XK22/ PIC18F8XK22 PIR1, PIR2, PIR3, PIR4, PIR5, PIR6 PIE1, PIE2, PIE3, PIE4, PIE5, PIE6 IPR1, IPR2, IPR3, IPR4, IPR5, IPR6 While migrating from the PIC18F8722 to the PIC18F87K22 family, the user has to consider that a few interrupt control/status bits are moved to different registers. Also, some new bits are added corresponding to the new peripherals. For more information, refer to the respective sections for the peripherals of interest. DS01431A-page 8 Preliminary 2012 Microchip Technology Inc.

9 I/O PORTS The PIC18F87K22 family is nearly pin compatible with the PIC18F8722 family for easy migration. TABLE 9: I/O COMPARISON Number of I/O Table 10 shows the port bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 10: PORT BIT NAMING CONVENTION AND FUNCTIONALITY Table 9 shows the I/O comparison between the PIC18F8722 and PIC18F87K22 families. Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 54 (PIC18F6X22) 70 (PIC18F8X22) 53 (PIC18F6XK22) 69 (PIC18F8XK22) Peripherals with Open-drain Option I 2 C SPI, I 2 C, ECCP, CCP, EUSART, CTMU Ports with Internal Pull-up Option PORTB PORTB, PORTD, PORTE, PORTJ (1) AVDD/AVSS Pins Note 1: Not available on 64-pin devices (PIC18F6XK22). TABLE 10: Feature Description PORT Data PORT Latch Port Direction Pull-up Enables PIC18F6X22/ PIC18F8X22 PORTA<7:0> PORTB<7:0> PORTC<7:0> PORTD<7:0> PORTE<7:0> PORTF<7:0> PORTG<5:0> PORTH<7:0> (1) PORTJ<7:0> (1) LATA<7:0> LATB<7:0> LATC<7:0> LATD<7:0> LATE<7:0> LATF<7:0> LATG<5:0> LATH<7:0> (1) LATJ<7:0> (1) TRISA<7:0> TRISB<7:0> TRISC<7:0> TRISD<7:0> TRISE<7:0> TRISF<7:0> TRISG<4:0> TRISH<7:0> (1) TRISJ<7:0> (1) RBPU (INTCON2<7>) PIC18F6XK22/ PIC18F8XK22 PORTA<7:0> PORTB<7:0> PORTC<7:0> PORTD<7:0> PORTE<7:0> PORTF<7:1> PORTG<5:0> PORTH<7:0> (1) PORTJ<7:0> (1) LATA<7:0> LATB<7:0> LATC<7:0> LATD<7:0> LATE<7:0> LATF<7:1> LATG<4:0> LATH<7:0> (1) LATJ<7:0> (1) TRISA<7:0> TRISB<7:0> TRISC<7:0> TRISD<7:0> TRISE<7:0> TRISF<7:1> TRISG<4:0> TRISH<7:0> (1) TRISJ<7:0> (1) RBPU (INTCON2<7>) RDPU (PADCFG1<7>) REPU (PADCFG1<6>) RJPU (1) (PADCFG1<5>) (1) Feature Description PSP Control Register Note 1: PORT BIT NAMING CONVENTION AND FUNCTIONALITY (CONTINUED) PIC18F6X22/ PIC18F8X22 PSPCON New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: PORTB, PORTD and PORTE have an internal pull-up option. Also, PORTJ has an internal pullup option on all 80-pin devices. The PIC18F8722 family has pull-ups only on PORTB. Open-drain outputs on EUSART, MSSP, CTMU, ECCP and the CCP modules. PORTF<0> is replaced with ENVREG functionality leaving only seven bits (PORTF<7:1>) for PORTF in the PIC18F87K22 family. Hence, care should be taken while using PORTF. PIC18F6XK22/ PIC18F8XK22 PSPCON Unimplemented on 64-pin devices (PIC18F6XK22). RF0 is not available as an I/O pin for the PIC18F87K22 family and has been replaced with ENVREG. The PIC18F87K22 family has more number of pins multiplexed with analog functions due to increase in number of analog input channels. As on POR, these pins are configured as analog inputs. The user should configure it as digital if used as digital pin Microchip Technology Inc. DS01431A-page 9

10 TIMERS The PIC18F87K22 family has six 8-bit timers and five 16-bit timers, while the PIC18F8722 family has only two 8-bit timers and three 16-bit timers. These differences and other features, that facilitate enhanced performance and flexibility, include: Gated Timer mode to support event-triggered counting Comparator, timer and gate pin available as event trigger for Timer1/3/5/7 Multiple clock sources Individual secondary oscillator enable control for Timer1/3/5/7 TABLE 11: TIMER COMPARISON Additional flexibility in timer selection for CCP/ ECCP modules In addition to FOSC/4, the system clock (FOSC) can also be selected as the Timer1 clock source Table 11 shows the timer comparison between the PIC18F8722 and PIC18F87K22 families. Table 12 shows the timer bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Timer Modules Five Eleven 8-Bit Timers Two Six 16-Bit Timers Three Five Associated CCP Modules Two Seven Timer with Gated Option None Timer1/3/5/7 Source of Clock for 16-bit timer Instruction Clock (FOSC/4) External Clock (T1/3CKI or SOSC) Instruction Clock (FOSC/4) External Clock (T1/3CKI or SOSC) System Clock (FOSC) Individual Secondary Oscillator T1OSCEN (T1CON<3>) for Timer1 SOSCEN (TxCON<3>) for Timer1/3/5/7 Enables Secondary Oscillator Clock Status T1RUN (T1CON< 6>) SOSCRUN (OSCCON2<6>). TABLE 12: TIMER BIT NAMING CONVENTION AND FUNCTIONALITY COMPARISON Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Timer1 Clock Source Select TMR1CS (T1CON<1>) TMR1CS<1:0> (T1CON<7:6>) Secondary Oscillator Enable T1OSCEN (T1CON<3>) SOSCEN (T1CON<3>) Secondary Oscillator System Clock Status T1RUN (T1CON<6>) SOSCRUN (OSCCON2<6>) 16-Bit Read/Write Enable RD16 (T1CON<7>) RD16 (T1CON<1>) Timer3 Clock Source Select TMR3CS (T3CON<1>) TMR3CS<1:0> (T3CON<7:6>) Secondary Oscillator Enable N/A SOSCEN (T3CON<3>) 16-Bit Read/Write Enable RD16 (T3CON<7>) RD16 (T3CON<1>) DS01431A-page 10 Preliminary 2012 Microchip Technology Inc.

11 New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: The PIC18F87K22 family has 11 timers overall: five 16-bit timers and six 8-bit timers Four of the 16-bit timers, Timer1/3/5/7 come with the enhanced features for multiple clock sources and a configurable gated timer feature to control counting with event triggers Timer1/3/5/7 can derive its clock from one of the following sources: - System Clock (FOSC): Timer counts four times faster than the instruction cycle supporting highest available precision over a shorter interval of time - Instruction Clock (FOSC/4): Timer counts at the same rate at which the instructions will be executed. This is the legacy feature supported by the PIC18F8722 family - External Clock Source/Secondary Oscillator: Counter from the external signal on the TxCKI pin or timer from the secondary oscillator. Note that the TxCKI and SOSCO pins are two separate pins which enable the use of a secondary oscillator for the RTCC module while TxCKI is being used for the TimerX module Timer1/3/5/7 together can derive its clock from a secondary oscillator with the secondary oscillator Enable bit (SOSCEN). The SOSCEN bit is available individually in the timer configuration registers, TxCON (in the PIC18F8722 family, Timer1 and Timer3 share this bit) Timer1/3/5/7 Gated mode is an event triggered timer enable, in which an external trigger source controls the timer count and sets the interrupt flag. The polarity of the trigger is selectable with the gate signal polarity bit, TxGPOL (TxGCON<6>). The gate triggers are software selectable and can be one of the following: - TIMERx Gate Pin - TMR(x+1) to match PR(x+1) output - Comparator 1 or Comparator 2 Output The following Gated modes are available for Timer1/3/5/7: - Count Enable mode Timer can be configured to count freely or the count can be enabled and disabled using the timer gate circuitry - Toggle mode Measures the full cycle length of the timer gate signal - Single Pulse mode Captures the single pulse gate event - Single Pulse and Toggle Combined mode Measures the cycle times on the timer gate source Gated timer interrupts can be enabled to indicate gated timer count completion The following timing gate sources are available for Timer1/3/5/7 - TIMERx Gate Pin - TMR(x+1) to match PR(x+1) output - Comparator 1 Output - Comparator 2 Output External clock gate input pins are available for Timer1/3/5/7 All PIC18F8722 family timer features are supported by the PIC18F87K22 family. The PIC18F87K22 family allows clock speeds up to 64 MHz, compared to the PIC18F8722 family s top speed of 40 MHz. This means higher clock rates and improved resolution are supported Microchip Technology Inc. DS01431A-page 11

12 CAPTURE/COMPARE/PWM (CCP) The CCP module of the PIC18F8722 and PIC18F87K22 families are very similar. Table 13 shows the major differences between the controllers. TABLE 13: CAPTURE/COMPARE MODE COMPARISONS Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Number of Modules Two Seven Name of the Modules CCP4, CCP5 CCP4-CCP10 Associated I/O Pin (1) RG3, RG4 RG3, RG4, RE2-RE6 Associated Timer Selection bits Timer1, Timer3 Timer1,Timer3,Timer5,Timer7 Timer Size T3CCP<2:1> (T3CON<6,3>) CxTSEL (CCPTMRS<7:0>) Interrupt Flags CCP4IF (PIR3<1>), CCP5IF (PIR3<2>) CCP4IF (PIR4<1>), CCP5IF (PIR4<2>), CCP6IF (PIR4<3>), CCP7IF (PIR4<4>), CCP8IF (PIR4<5>), CCP9IF (PIR4<6>), CCP10IF (PIR4<7>) Note 1: In all 80-pin devices the CCP6, CCP7, CCP8, CCP9, ECCP1/ECCP3 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). These pins are also available on RH7, RH6, RH5 and RH4. TABLE 14: PWM MODE COMPARISONS Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Number of Modules Two Seven Name of the Modules CCP4, CCP5 CCP4-CCP10 Associated I/O Pin (1) RG3, RG4 RG3, RG4, RE2-RE6 Clock Sources Timer2, Timer4 Timer2, Timer4, Timer6, Timer8 Associated Timer Selection bits T3CCP<2:1> (T3CON<6,3>) CxTSEL (CCPTMRS<7:0>) Minimum Duty Cycle 25 ns at 40 MHz (TOSC) 15.6 ns at 64 MHz (TOSC) Minimum Period 100 ns at 40 MHz (TCY) 62.5 ns at 64 MHz (TCY) Note 1: In all 80-pin devices the CCP6, CCP7, CCP8, CCP9, ECCP1/ECCP3 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). These pins are also available on RH7, RH6, RH5 and RH4. New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: Faster clock speed for high-resolution capture, compare and PWM functions More CCP peripherals Four timer resources for the PWM peripheral The PIC18F87K22 family uses the CCPTMRS register s CxTSEL bits to select timers (PIC18F8722 family selects timers using T3CCP bits of T3CON). The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). All PIC18F8722 family CCP features are supported by the PIC18F87K22 family. DS01431A-page 12 Preliminary 2012 Microchip Technology Inc.

13 ENHANCED CAPTURE/COMPARE/ PWM (ECCP) The Enhanced Capture/Compare/PWM module is very similar between the PIC18F8722 and PIC18F87K22 families. Significant differences include the method for timer selection and the addition of Pulse Steering mode. ECCP capture and compare functionality is identical to that of the CCP modules. For more information on these functions, see the CCP section of the PIC18F87K22 Family Data Sheet (DS39960). Table 15 shows the ECCP comparison between the PIC18F8722 and PIC18F87K22 families. TABLE 15: ENHANCED CAPTURE COMPARISON Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Number of Modules Three Three Name of the Modules ECCP1, ECCP2, ECCP3 ECCP1, ECCP2, ECCP3 Associated I/O Pins (1) RC2, RC1/RE7/RB3 (2), RG0 RC2, RC1/RE7/RB3 (2), RG0 Open-Drain Option No Capture/Compare Clock Sources Timer1, Timer3 Timer1, Timer3 PWM Clock Sources Timer2, Timer4 Timer2, Timer4, Timer6, Timer8, Timer10, Timer12 Timer Select Register T3CON CCPTMRS Pulse Steering mode No Minimum Duty Cycle 25 ns at 40 MHz (TOSC) 15.6 ns at 64 MHz (TOSC) Minimum Period 100 ns at 40 MHz (TCY) 62.5 ns at 64 MHz (TCYK) Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller mode or Extended Microcontroller mode. 2: This Pin association is only available on 80-pin devices. New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: Faster clock speed for high-resolution capture, compare and PWM functions Four timer resources for the PWM peripheral Pulse Steering mode The only significant migration consideration is how the PWM timer selection is made. The selection has been moved from the T3CON register to a new register, CCPTMRS, using the CxTSEL bits. All other ECCP functionality is the same when migrating from the PIC18F8722 to the PIC18F87K22 family. All PIC18F8722 family ECCP features are supported by the PIC18F87K22 family Microchip Technology Inc. DS01431A-page 13

14 MASTER SYNCHRONOUS SERIAL PORT (MSSP) I 2 C The PIC18F87K22 family supports the address masking feature in I 2 C slave operation. This feature allows the I 2 C slave to respond to a range of addresses by masking the corresponding bits of the incoming address. Table 16 shows the I 2 C comparison between the PIC18F8722 and PIC18F87K22 families. TABLE 16: I 2 C COMPARISONS Feature Description 7-Bit Address Masking mode 5-Bit Address Masking mode New PIC18F87K22 Family ADDRESS MASKING PIC18F6X22/ PIC18F8X22 No No PIC18F6XK22/ PIC18F8XK22 The PIC8F87K22 family is capable of using two different address masking modes in I 2 C slave operation: 5-Bit Address Masking and 7-Bit Address Masking. The masking mode is selected at device configuration using the MSSPMSK Configuration bit (CONFIG3H<3>). The default device configuration is 7-Bit Address Masking mode. Masking an address bit causes the bit to become a don t care. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I 2 C slave behaves the same way, whether address masking is used or not. However, when address masking is used, the I 2 C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking the SSPxBUF. Both masking modes, in turn, support address masking of 7-bit and 10-bit addresses. The combination of masking modes and addresses provides different ranges of acknowledgeable addresses for each combination. While both masking modes function in roughly the same manner, the way they use address masks are different. All PIC18F8722 family I 2 C features are supported by the PIC8F87K22 family. None. DS01431A-page 14 Preliminary 2012 Microchip Technology Inc.

15 MASTER SYNCHRONOUS SERIAL PORT (MSSP) SPI Table 17 shows the SPI comparison between the PIC18F8722 and PIC18F87K22 families. Both the PIC18F8722 and PIC18F87K22 families have two MSSP (SPI) modules. Both families support all SPI modes of operation and are similar in performance. TABLE 17: SPI COMPARISON Feature Description PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 SPI Modules Two Two Maximum Clock Speed (1) 10 MHz (40 MHz/4) 16 MHz (64 MHz/4) Open-Drain Peripheral Outputs No (SCKx and SDOx can be configured as open-drain outputs) Note 1: The 16 MHz SPI frequency may be reduced to meet data setup and hold times. New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: Increased MIPS operation enabling higher data transmission rates, up to 16 MHz Additional FOSC/8 option for SPI Master mode Open-drain ability on outputs (SCK and SDO) enabling to be interfaced with different voltage levels, using pull-up To enable the open-drain outputs capability, the SSPxOD bits in ODCON1 register must be set There have been some minor changes in the control and STATUS registers and bits names, so care must be taken while accessing them. In the PIC18F87K22 family the SS1 pin is multiplexed with AN5. By default this pin is an analog pin, so the user should configure it as a digital pin to be used as SS1 pin. To configure this as a digital pin, bit ANCON0<5> should be cleared. All PIC18F8722 family MSSP/SPI features are supported by the PIC18F87K22 family Microchip Technology Inc. DS01431A-page 15

16 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) Both the PIC18F8722 and PIC18F87K22 families have two EUSART modules. The PIC18F87K22 family also has additional control features for supporting a wider variety of data formats. Table 18 shows the EUSART comparison between the PIC18F8722 and PIC18F87K22 families. Table 19 shows the EUSART bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 18: Feature Description EUSART COMPARISONS PIC18F6x22/ PIC18F8x22 PIC18F6xK2/ PIC18F8xK22 EUSART Modules Two Two Open-Drain Option No LIN/J2602 Bus Support Wake-up on Reception Auto-Baud 12-Bit Break Character Synchronous mode Data/Receive Polarity Select No TABLE 19: EUSART BIT NAMING CONVENTION AND FUNCTIONALITY Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Transmit Status/Control TXSTAx TXSTAx Receive Status/Control RCSTAx RCSTAx EUSART1 Baud Rate Generator Register High Byte SPBRGH1 SPBRGH1 EUSART1 Baud Rate Generator Register Low Byte SPBRG1 SPBRG1 EUSART2 Baud Rate Generator Register High Byte SPBRGH2 SPBRGH2 EUSART2 Baud Rate Generator Register Low Byte SPBRG2 SPBRG2 Baud Rate Control Registers BAUDCONx BAUDCONx Auto-Baud Detect Enable ABDEN (BAUDCONx<0>) ABDEN (BAUDCONx<0>) Wake-up Enable WUE (BAUDCONx<1>) WUE (BAUDCONx<1>) 16-Bit Baud Rate Register Enable BRGH (BAUDCONx<3>) BRGH (BAUDCONx<3>) Synchronous Clock Polarity Select SCKP (BAUDCONx<4>) TXCKP (BAUDCONx<4>) Data/Receive Polarity Select N/A RXDTP (BAUDCONx<5>) Receive Operation Idle Status RCIDL (BAUDCONx<6>) RCIDL (BAUDCONx<6>) Auto-Baud Acquisition Rollover Status ABDOVF (BAUDCONx<7>) ABDOVF (BAUDCONx<7>) New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: The data polarity can be selected. The RXDTP bit (BAUDCONx<5>) decides the polarity of the RX pin and the TXCKP bit (BAUDCON<4>) decides the polarity of the TX pin. With higher baud rates due to FOSC speed up to 64 MHz, all of the PIC18F8722 family baud rates are supported by the PIC18F87K22 family. This is similar to the PIC18F8722 family which provides configurations to reduce the baud rate error percentage. The Synchronous Clock Polarity Select bit, TXCKP (BAUDCONx<4>), is also applicable in Asynchronous mode as a transmit polarity select bit and hence should be considered when operating in Asynchronous mode. All of the PIC18F8722 family EUSART features are supported by the PIC18F87K22 family. DS01431A-page 16 Preliminary 2012 Microchip Technology Inc.

17 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) The PIC18F8722 family has a 10-bit A/D converter, while the PIC18F87K22 family has a 12-bit A/D converter with a sign bit. The converter in the PIC18F87K22 family is a differential A/D converter (with two inputs), while the PIC18F8722 family has a single input. The PIC18F87K22 family s differential A/D converter can be configured as a single input A/D converter by connecting the negative input internally to AVSS. Table 20 shows the A/D convertor comparison between the PIC18F8722 and PIC18F87K22 families. Table 21 shows the A/D convertor bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 20: Feature Description A/D Resolution Number of Analog Channels Modes of Operation A/D Trigger Sources Operation During Sleep A/D CONVERTER COMPARISONS PIC18F6X22/ PIC18F8X22 10-bit 12 (PIC18F6X22) 16 (PIC18F8X22) Single Input One (ECCP2 Trigger) PIC18F6XK22/ PIC18F8XK22 12-bit plus one sign bit 16 (PIC18F6XK22) 24 (PIC18F8XK22) Differential Four (RTCC, Timer1, CTMU, ECCP2) New PIC18F87K22 Family The following new features are available within the PIC18F87K22 family: A differential A/D converter capable of measuring the differential voltage between two channels Increased resolution that enables more accurate digital values of corresponding analog signals and a sign bit that indicates A/D results polarity VDDCORE and band gap voltages that can be measured by selecting the appropriate channel Channel connections that are internal to the source, so no external connections are required and five Channel Select bits, CHS<4:0>, for accessing more channels Increased A/D trigger sources, so the module can be triggered from four different sources: ECCP2, RTCC, Timer1 and CTMU (PIC18F8722 family has only one trigger source i.e., ECCP2) Two internal A/D VREF+ sources (2.048V, typical and 4.096V, typical) that can be used as VREF+, in addition to the external VREF and AVDD The ability to reduce power consumption by shutting off the module through the disable bit, ADCMD (PMD0<0>) The module is enabled by default on POR. All PIC18F8722 family A/D converter features are supported by the PIC18F87K22 family. The PIC18F8722 family has an analog channel AN5 multiplexed to the RF0 pin where as, the PIC18F87K22 family has AN5 multiplexed to the RF7 pin. All remaining analog channels and external VREF signals have been multiplexed with the same ports pins. The PIC18F8722 family selects the port configuration through the PCFG<3:0> bits (ADCON1<3:0>). The PIC18F87K22 family does this through the individual port pins corresponding ANSEL bits of the ANCON0, ANCON1 and ANCON2 registers. The PIC18F87K22 family has changed the bit names and functionality of the ADCON1 register, so care must be taken in configuring this register. TABLE 21: Channel Select A/D CONVERTER BIT NAMING CONVENTION AND FUNCTIONALITY Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Port Configuration Bits A/D Reference Voltage Configuration Bits Trigger Selection Bits CHS<3:0> (ADCON0<5:2>) PCFG<3:0> (ADCON1<3:0>) VCFG<1:0> (ADCON1<5:4>) CCP2M<3:0> (CCP2CON<3:0>) CHS<4:0> (ADCON0<6:2>) CHSN<2:0> (ADCON1<2:0>) ANSEL<7:0> (ANCON0<7:0>, ANSEL<15:8> (ANCON1<15:8>), ANSEL<23:16> (ANCON2<23:16>) VCFG<1:0> (ADCON1<5:4>) VNCFG (ADCON1<3>) TRIGSEL<1:0> (ADCON1<7:6>) A/D Result Registers ADRESH, ADRESL ADRESH, ADRESL 2012 Microchip Technology Inc. DS01431A-page 17

18 ANALOG COMPARATOR MODULE The analog comparator module contains three comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation are also available. Benefits of the PIC18F87K22 family comparator module: Each comparator has a dedicated Configuration bit CON(CMxCON<7>) to enable or disable the module Each comparator has its own Comparator Output Enable bit, COE (CMxCON<6>), that makes the output available on the CxOUT pin Interrupt polarity can be selected for individual comparators and configured for low-to-high or high-to-low transitions, or any change of the comparator output Table 22 shows the comparator comparison between the PIC18F8722 and PIC18F87K22 families. TABLE 22: Feature Description Number of Comparators Internal Band Gap Reference Option Selectable Interrupt Edge Individual Comparator Interrupts COMPARATOR COMPARISONS PIC18F6X22/ PIC18F8X22 Two No No No PIC18F6XK22/ PIC18F8XK22 Three Table 23 shows the comparator bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 23: COMPARATOR BIT NAMING CONVENTION AND FUNCTIONALITY Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Comparator Output Status bits CxOUT (CMCON<7:6>) CMPxOUT (CMSTAT<7:5>) Comparator Output Polarity CxINV (CMCON<5:4>) CPOL (CMxCON<5>) Comparator I/O Operating modes CIS (CMCON<3>) CM<2:0> (CMCON<2:0>) CREF(CMxCON<2>) CCH<1:0> (CMxCON<1:0>) New PIC18F87K22 Family Comparator The PIC18F87K22 family has the following new features for improving flexibility and reducing CPU overhead: Separate CMCON registers for each comparator, providing flexibility to individually configure each comparator Individual interrupts for each comparator The ability to configure individual comparator interrupts for any of the following occurrences using the EVPOL<1:0> bits: - Low-to-high transition of the comparator output - High-to-low transition of the comparator output - Any change of the comparator output Fixed internal reference voltage VBG, (1.024V nominal) on the inverting terminal, if desired All PIC18F8722 family comparator features are supported by the PIC18F87K22 family. All PIC18F8722 family comparator functions can be supported with the PIC18F87K22 family. However, migration requires a source code rewrite, due to changes in the control registers, CMxCON and CMSTAT. DS01431A-page 18 Preliminary 2012 Microchip Technology Inc.

19 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference module is a resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. The comparator voltage reference module is controlled through the CVRCON register. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- inputs, that are multiplexed with RA3 and RA2. The voltage source is selected by the CVRSS bit of the CVRCON register. Table 24 shows the CVREF comparisons between the PIC18F8722 and PIC18F87K22 families. TABLE 24: Feature Description CVREF COMPARISONS PIC18F6X22/ PIC18F8X22 PIC18F6XK22/ PIC18F8XK22 Number of Taps Number of Output Voltage Levels Range Selection No Table 25 shows the CVREF bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 25: CVREF BIT NAMING CONVENTION AND FUNCTIONALITY Functionality PIC18F6X22/PIC18F8X22 PIC18F6XK22/PIC18F8XK22 Reference Enable CVREN (CVRCON<7>) CVREN (CVRCON<7>) Output Enable CVROE (CVRCON<6>) CVROE (CVRCON<6>) Range Selection CVRR (CVRCON<5>) N/A Source Selection CVRSS (CVRCON<4>) CVRSS (CVRCON<5>) Value Selection CVR<3:0> (CVRCON<3:0>) CVR<4:0> (CVRCON<4:0>) The Comparator Range Selection option is not available within the PIC18F87K22 family. All remaining PIC18F8722 family comparator voltage reference features are supported by the PIC18F87K22 family. New PIC18F87K22 Family The PIC18F87K22 family has a single voltage range with improved resolution, and 32 output voltage levels as compared to 16 output voltage levels of the PIC18F8722 family. For more information on the available voltages, range and functionality, refer to the PIC18F87K22 Family Data Sheet (DS39960). The following changes to the CVREF module need to be considered when migrating from the PIC18F8722 to PIC18F87K22 families: There is no Comparator VREF Range Selection bit (CVRR) in the PIC18F87K22 family. This means the device will have a single, expanded range For the PIC18F87K22 family, the CVREF voltage resolution is based on 32 levels, unlike the PIC18F8722 family s 16 levels 2012 Microchip Technology Inc. DS01431A-page 19

20 HIGH/LOW-VOLTAGE DETECT (HLVD) Both PIC18F87K22 and PIC18F8722 families have one HLVD module. Table 26 shows the HLVD comparison of the PIC18F8722 and PIC18F87K22 families. TABLE 26: Feature Description HLVD COMPARISONS PIC18F6X22/ PIC18F8X22 PIC18F6XK22/ PIC18F8XK22 HLVD Modules One One Programmable Level and Direction 16 Configurable Voltage Direction External Reference Band Gap Reference Stable Status Table 27 shows the HLVD bit naming convention and functionality of the PIC18F8722 and PIC18F87K22 families. TABLE 27: Functionality Internal Reference Voltage Stable Flag Band Gap Reference Voltages Stable Status Flag (This flag does not assure HLVD module readiness) HLVD BIT NAMING CONVENTION AND FUNCTIONALITY PIC18F6X22/ PIC18F8X22 IRVST (HLVDCON <5>) N/A PIC18F6XK22/ PIC18F8XK22 IRVST (HLVDCON <5>) BGVST (HLVDCON<6>) No other migration considerations are needed. VREG The PIC18F87K22 family operates on two voltage domains, core operates at max 3.3V and I/Os and peripherals at max 5.5V. To enable single-supply voltage application design, an on-chip 3.3V voltage regulator is provided. With the internal regulator, an external LDO is not required to provide the separate core supply. It also permits the device to run at a higher VDD. It requires a 10 µf, low Equivalent Series Resistance (ESR) capacitor, like ceramic or tantalum, on the VCAP pin. A second regulator is available to reduce power consumption in Sleep modes. This option permits the main LDO to be disabled and uses a low-power regulator to maintain data memory and port logic levels in these modes. New PIC18F87K22 family The core operates nominally at 3.3V and the on-chip voltage regulator provides this voltage. There are no VREG features within the PIC18F8722 family that are not supported by the PIC18F87K22 family. Pin No.10 in PIC18F6X22 and Pin No. 12 in PIC18F8X22 are VDD pin, while they are VDDCORE/ VCAP pin in PIC18F6XK22 and PIC18F8XK22. Therefore, a low-esr capacitor (10 µf) should be connected to this pin, removing the VDD supply connection. New PIC18F87K22 Family The PIC18F87K22 family has the Band Gap Reference Voltages Stable Status Flag bit associated with the HLVDCON register BGVST(HLVDCON<6>). This Status bit is not defined in the HLVDCON register of the PIC18F8722 family. All PIC18F8722 family LVD features are supported by the PIC18F87K22 family. DS01431A-page 20 Preliminary 2012 Microchip Technology Inc.