Reset and clock control (RCC)

Transcription

1 Reset and clock control (RCC)

2 RESET Sources 86 System RESET Resets all registers except some RCC registers, PWR registers and Backup domain Sources Low level on the NRST pin (External Reset) WWDG event IWDG event Firewall event A software reset (through NVIC) Low-power mode security reset Option byte loader reset Brown-out Reset Reset flag source can be found in RCC_CSR register

3 RESET Sources 87 Power RESET Sources Brown-out reset BOR => reset all registers except those in Backup domain Exit from STANDBY => all registers in V CORE domain are reset Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby/Shutdown modes control) are not impacted. Exit from SHUTDOWN generates a BOR Reset. Backup domain RESET Resets in the Backup domain: RTC registers + Backup Registers + RCC BDCR register Sources BDRST bit in RCC BDCR register VDD or VBAT power on, if both supplies have previously been powered off Peripherals individual reset in RCC_AHBxRSTR/APBxRSTRy

4 Reset block diagram 88 Reset pull-up deactivated when internal reset V DD /V DDA R PU External RESET NRST Filter SYSTEM RESET WWDG RESET PULSE GENERATOR (min 20µs) IWDG RESET Firewall RESET Option byte loading RESET Software RESET BOR RESET Low power management RESET

5 Clocks: MSI (Multi-Speed Internal) 89 MSI = clock at startup from Reset, Standby or Shutdown modes. Programmable frequency : 12 ranges selected with MSIRANGE in RCC_CR: 100 khz, 200 khz, 400 khz, 800 khz, 1 MHz, 2 MHz, 4 MHz (reset value), 8 MHz, 16 MHz, 24 MHz, 32 MHz, 48 MHz. After Reset and Shutdown, MSI frequency is 4 MHz, selected by MSISRANGE in RCC_CSR register After Standby: Frequency selected from 1, 2, 4 or 8 MHz with MSISRANGE in RCC_CSR register. MSIRGSEL must be set in RCC_CR to switch to the frequency selected by MSIRANGE

6 Clocks: MSI (Multi-Speed Internal) 90 Can be selected as clock at wakeup from Stop 1 or 2 modes / CSS backup clock Normal mode and PLL-mode (=auto-calibration with LSE) PLL-mode : allows USB FS device functionality (0.25% accuracy) Factory and user trimmed

7 Clocks: HSI(High-Speed Internal) 91 HSI 16MHz, factory and user trimmed Can be selected as clock at wakeup from Stop 1 or 2 modes / CSS backup clock Can be automatically woken up when exiting Stop modes (HSIASFS set in RCC_CR) Clock requested by I2C and U(S)ART/LPUART peripherals to support wakeup from Stop 1 or 2 modes

8 Accuracy (max) Consumption (typ) Startup time (typ) HSI vs. MSI (design spec) Normal mode MSI Over temperature: ±6% Over voltage: From 100 to 800 khz : ±1% From 1 to 8 MHz : ±2% From 16 to 48 MHz : ±4% 100 khz : 0.5 µa 800 khz : 2µA 1 MHz : 5µA 8 MHz : 20 µa 16 MHz : 60 µa 48 MHz : 160 µa 100 khz : 10 µs 48 MHz : 2.5 µs PLL-mode Better than 0.25% 1.25 ms for 5% of final freq. HSI TBD 130 µa 0.9 µs 92

9 Clocks: HSE(High-Speed External) 93 HSE 4-48MHz External source (Bypass mode) up to 40 MHz External Crystal/Ceramic resonator (4-48MHz) Clock Security System (CSS) Automatic detection of HSE failure with NMI generation Break input to TIM1/TIM8/TIM15/TIM16/TIM17 Backup clock can be HSI or MSI depending on STOPWUCK in RCC_CFGR MSI by default

10 Clocks: PLL 94 3 PLLs Each with 3 independent outputs PLLs input frequency must be between 4 and 16 MHz PLL input can be MSI/HSI or HSE 5,6,7,8 f(vco clock) = (f(pll clock input)/pllm) PLLN f(pll_p) = f(vco clock) / PLLP f(pll_q) = f(vco clock) / PLLQ f(pll_r) = f(vco clock) / PLLR PLLM from 1 to 8 PLLN from 8 to 86 PLLP = 7 or 17 PLLQ = 2, 4, 6, 8 PLLR = 2, 4, 6, 8 PLLP from 02/07/ to 31 in derivatives

11 System clock 95 Selected between HSI/HSE/MSI/PLL Maximum frequency 80 MHz APB1 and APB2 up to 80 MHz Clock source max frequency depending on voltage scaling: Voltage range MSI HSI HSE PLL Range 1 Range 2 48 MHz range 24 MHz range 16 MHz 48 MHz 80 MHz VCO max = 344 MHz 16 MHz 26 MHz 26 MHz VCO max = 128 MHz 95

12 Clocks: LSE (Low-Speed External) 96 LSE: programmable amplifier driving capability (4 modes) Mode Crystal (max) Consumption (typ) Ultra low power 50kOhm/6pF 200 na Medium low driving 80kOhm/6pF 260 na Medium high driving 50kOhm/12.5pF 410 na High driving 80kOhm/12.5pF 540 na Available in all low-power modes + VBAT

13 Clocks: LSI (Low-Speed Internal) 97 LSI 32kHz Parameters STM32L15x STM32L4x Accuracy over parts KHz ~8% Accuracy over temperature -10% / +4% 2% (0..85 C) ( C) Consumption (typ) 400nA 110nA Available in all low-power modes except Shutdown and VBAT

14 Clocks 98 Clock security system on LSE Available in all modes except Shutdown and VBAT. Still working under reset. Clock-out capability : MCO selected between : LSI LSE SYSCLK LSCO selected between : LSI LSE Available in all modes except VBAT HSI HSE PLLCLK MSI

15 Peripheral clocks Enable registers: RCC_AHBxENR, RCC_APBxENRy: Peripheral clock disable by default (except Flash) After enable bit is set: 2 clock cycles delay before clock to be active Clocks Registers read and write access not supported when clock is disable. Caution: SRAM1 and SRAM2 do not have enable bit 99 Peripheral clocks Enable registers in Sleep and Stop modes: RCC_AHBxSMENR, RCC_APBxSMENRy: If the corresponding peripheral xxen bit is set: xxsmen controls if the peripheral clocks are enable in Sleep, LPSleep, Stop 1/2 modes. No effect if xxen is cleared Control both bus and kernel clock Control both in Sleep and Stop modes (for peripheral with independent clock active in Stop) Caution: SRAM1 and SRAM2 clock is enable by default in Sleep/LPSleep