System Simulator for x86

Transcription

1 MARSS Micro Architecture & System Simulator for x86 CAPS SUNY Binghamton Presenter Avadh Patel

2 Present State of Academic Simulators Majority of Academic Simulators: Are for non x86 platforms Do not support Full System Simulate single core CPUs Current state of x86 Simulators: Very few open source, cycle accurate, full system simulator Some arebased on PTLsim (which was developed by Matt Yourst of CAPS group) Most target single core designs QUF 11 DATE 2011 MARSSx86 ( 2

3 Future Computing Systems Server/Desktop Space: Integrated Systems Many modules in one chip IO bound software applications Hardware Software co design Mobile Space: SoC will integrate more modules Operating System will become more complex Researchers will require more powerful tools for innovative i designs QUF 11 DATE 2011 MARSSx86 ( 3

4 Simulator for Future Enabling research of future micro processors and SoCs Hardware software co design Heterogeneous Architecture Real IO activities Allow existing models to integrate with ease MUST run unmodified binaries 4

5 PTLsim Cycle accurate x86 simulator with: Detailed out of order pipeline pp Simple Cache/Memory simulation Uses Xen to support full system simulation Limitations: Setup required custom kernel with Xen support Difficult to tap into IO activities No support to use external modules/libraries 5

6 QEMU Port of Choice Fully user space level full system emulation PTLsim X was suffering because of Xen setup Runs unmodified binaries an OS Tons of emulated devices 6

7 QEMU Port of Choice Support for Checkpoints/Snapshots Simulators are very slow Not feasible to boot an OS for each benchmark run Leverage QCOW2 format s support to create snapshots at user specified addresses in benchmarks 7

8 QEMU Port of Choice 100% open source Many simulators based on closed source platform Like GEMS, FeS2 which are based on Simics Ati Active community with great support 8

9 MARSSx86 An Overview Simulat ted Software Stack User Space Applications Shared Libraries Services Operating System CPU Model Emulation Simulation Mem mory Manage ement DRAM IO Mem Disk Marss Framework IO Devices User Interface 9

10 MARSSx86 Simulator Model Fron nt End Dis spatch CPU Core Out Of Order Order Issue Re Order Buffer Function Unit Clusters Register File Various Modules in CPU Core that simulates detailed pipeline logic Private Caches Shared Caches Cache/Memory Coherent Caches Interconnect t DRAM Controller Cache/Memory Modules Provide highly configurable Memory Hierarchy designs 10

11 MARSSx86 Execution Control Flow CPU Context is shared between Emulated and Simulated models 11

12 MARSSx86 Key Features True Full System Not only Kernel space simulation but also real time IO simulation Supports running unmodified OSes Simulate real multi threaded workloads Real Time IO simulation i allows quick ikmodeling dli of new IO devices and their simulation 12

13 MARSSx86 Key Features Hardware Software Co Design Simulates full stack of software Communicate between software and Simulated Hardware No special requirement to build software for MARSS Co Simulation Emulation and Simulation Model in one framework Seamless switch hbetween two models dl Fast Fwd to interesting regions of benchmarks 13

14 Co Design & Co Simulation Softwa are Stack User Space Applications/Benchmarks Shared Libraries Services Operating System MMIO Simulated Hardware CPU Model Emulator Simulator DRAM IO Devices Disk, USB,PCI etc. Shared Device Models between CPU Models C0 C1 C2 C3 MLC MLC MLC MLC QUF 11 DATE 2011 Interconnect Shared Cache / DRAM MARSSx86 ( 14

15 MARSSx86 Key Features Heterogeneous Core Modeling Performance models for Aggressive out of order design with RISC substrate In order cores like Atom Multi Threaded core design for both out of order and in order models Simulate mix n match match of different types of core models 15

16 Heterogeneous Core Modeling Highly configurable Cores and Memory Models Oo Oo Oo Oo MT MT MT MT MT MT Oo Oo PC PC PC PC PC PC PC PC PC Interconnect Shared Cache / DRAM Interconnect Shared Cache / DRAM Interconnect Shared Cache / DRAM Multicore Configuration MT Configuration MT Multicore Configuration Oo InC Oo InC PC PC Interconnect Shared Cache / DRAM Hybrid Core Configuration 1 MT InC MT InC PC PC Interconnect Shared Cache / DRAM Hybrid Core Configuration 2 Oo : Out Of Order Core MT : Mutli Threaded core InC : In Order core PC : Private Cache 16

17 More Features Easily integrate external modules DRAMSim2 SystemC Phase Change RAM (PCRAM) New statistics framework enables separate collection of statistics from different regions Collects separate statistics for Kernel and User space Separate statistics collection of user specific ROI QUF 11 DATE 2011 MARSSx86 ( 17

18 Simulator Performance One of the most important requirement Marss runs cycle accurate simulation in range of 400 to 200 KIPS Fast simulation i allows users to test wide ranges of benchmark behavior in one simulation run 18

19 Simulator Performance 800 SPECInt2006 Benchmarks running with Test input (Full Application run) Instructions co ommits per secon nd in Thousands sjeng omnetpp mcf xalanc gcc astar gobmk libquantum hmm perl bzip Average Native System Configuration: Quad Core Intel Xeon 2.67GHz (Nehalem) with 8GB RAM Error bars show Maximum and Minimum Speed in KIPS QUF 11 DATE 2011 MARSSx86 ( 19

20 A Case Study Benchmark Regions 1,4 1,2 1 0,8 0,6 04 0,4 0,2 0 astar 0,10 0,80 1,50 2,20 2,90 3,60 4,30 5,00 5,70 6,40 7,10 7,80 8,50 9,20 9,90 10,60 11,30 12,00 12,70 13,40 14,10 14,81 15,51 16,21 16,91 17,61 18,31 19,01 19,71 20,41 21,11 21,81 22,51 23,21 23,91 24,61 25,31 IPC per 100 Million Cycles Cycles in billions 2 1,5 1 0,5 0 Bzip2 IPC per 100 Million Cycles Cycles in billions 20

21 Future Work ARM Port? Don t have enough expertise May be in next 6 12 months More Cache Coherence C h Models More CPU Models 21

22 Q & A Grab a copy to hack from: Open Source under GPL v2 License Send your comments/questions to apatel@cs.binghamton.edu 22

23 Backup 23

24 Technical Details Functional Model : QEMU JIT code generator for emulation More than 100 IO device models Supports multiple ISA 24

25 Technical ldtil Details Performance Model Based on PTLsim (older x86 simulator from CAPS Group) Components used from PTLsim: Decoder, Core components of Out Of Order Datapath, SuperSTL and Logic libraries lb Fast models for coherent cache, memory system Several added optimizations for performance, correctness and flexibility 25

26 Technical Details Benchmark Regions 1,6 1,4 12 1,2 1 0,8 0,6 0,4 0,2 mcf IPC per 100 Million Cycles 0 0, 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12,,10,50,90,30,70,10,50,90,30,70,10,50,90,30,70,10,50,90,30,70,10,50,91,31,71,11,51,91,31,71,11,51 Cycles in billions 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 gcc IPC per 10 Million Cycles 0 10,01 120,36 230,77 341,21 451,62 561,85 672,15 782,41 892, , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,37 QUF 11 DATE 2011 MARSSx86 ( Cycles in Millions 26

27 Simulator Performance IPC 1,8 1,6 1,4 1, ,8 0,6 0,4 0,2 0 SPECInt2006 Benchmarks running with Test input (Full Application run) Marss Nehalem sjeng omnetpp mcf xalanc gcc astar gobmk quantum hmm perl bzip Average Default OoO Core Model is configured with Nehalem Parameters Not exact modeling QUF 11 DATE 2011 MARSSx86 ( 27

28 Sim mulated So oftware Stack User Space Applications Shared Libraries Services Operating System Model CPU Emulation Simulation Me emory Man nageme nt DRAM IO Mem Disk IO Devices User Interface ABC Framework 28

29 Oo Oo Oo Oo Oo Oo Oo Oo PC PC PC PC Interconnect Shared Cache / DRAM PC PC PC PC Interconnect Shared Cache / DRAM C0 C1 C2 C3 MLC MLC MLC MLC Interconnect Shared Cache & DRAM 29

30 Sw Softwa are Stack User Space Applications/Benchmarks Shared Libraries Services Operating System MMIO Hw CPU Model Emulated Simulated DRAM IO Devices Disk, USB,PCI etc. 30

31 Key Features True Full System Co Design & Co Simulation Heterogeneous Models Simulator Performance 31

32 Modules in the Framework CPUs Emulation CPU Simulation Memory Management Unit IO Emulation & BIOS Support Guest Disk Image Management User Interface JIT Soft MMU Exceptions Interrupts t Out Of Order Pipeline In Order Pipeline Multicore Heterogeneous Coherent Caches On Chip Interconnect Guest to Host mapping DRAM DMA IO Memory Page fault Handling VGA NIC USB etc. IO APIC Local APIC Raw Copy on write (QCOW) Snapshots (Checkpoints) Monitor Full Graphic support VNC Serial lport 32

33 True Full System Simulation Not only Kernel space simulation but also real time IO simulation Supports running unmodified OSes Simulate real multi threaded li d workloads Real Time IO simulation allows quick modeling of new IO devices and their simulation 33

34 Key Features True Full System Co Design & Co Simulation Heterogeneous Models Simulator Performance 34

35 Key Features True Full System Co Design & Co Simulation Heterogeneous Models Simulator Performance 35

36 Key Features True Full System Co Design & Co Simulation Heterogeneous Models Simulator Performance 36