The DragonBeam Framework: Hardware-Protected Security Modules for In-Place Intrusion Detection

Transcription

1 : Hardware-Protected Security Modules for In-Place Intrusion Detection Man-Ki Yoon, Mihai Christodorescu, Lui Sha, Sibin Mohan University of Illinois at Urbana-Champaign Qualcomm Research Silicon Valley June 6, 2016

2 Security Monitoring In-place Monitoring n n n OS External Monitoring n n n OS

3 Security Monitoring In-place Monitoring n n n OS External Monitoring n n n OS Unsafety of the monitor

4 Security Monitoring In-place Monitoring n n n OS External Monitoring n n n OS Semantic gap Unsafety of the monitor

5 DragonBeam Framework n n n OS Command/Response Secure Layer Untrusted Layer

6 DragonBeam Framework Monitored Core Secure Core n n n Secure Memory OS Command/Response Untrusted Layer Secure Layer

7 DragonBeam Framework Monitored Core Secure Core n n n Secure Memory OS Command/Response Untrusted Layer Secure Layer Secure Kernel Module - Performs security monitoring operations - Expands the observability - Protected by Secure Core

8 DragonBeam Framework Monitored Core Secure Core n n n Secure Memory OS Command/Response Untrusted Layer Secure Layer Secure Kernel Module Manager - Commands to perform security operations - Analyzes monitored information - Guarantees the integrity and the liveness of

9 DragonBeam Framework Monitored Core Secure Core n n n Secure Memory OS Command/Response Untrusted Layer Secure Layer Secure Memory - Secure communication channel between and - Only accessible by or Secure Core - Also hosts code/data

10 Example Use Case Time Secure Data Memory

11 Example Use Case Sends Command Time check_syscall_table() { send_cmd(cmd_syscall_table); settimer(timeout); } Secure Data Memory

12 Example Use Case Sends Command Time 1 check_syscall_table() { send_cmd(cmd_syscall_table); settimer(timeout); } Secure Data Memory

13 Example Use Case Sends Command Time skm_isr() { save sp; move sp to secure stack; switch (*CMD) { case CMD_SYSCALL_TABLE: send_syscall_table(); break; } restore sp; } 2 1 check_syscall_table() { send_cmd(cmd_syscall_table); settimer(timeout); } Secure Data Memory

14 Example Use Case Sends Command Collects Information Time skm_isr() { save sp; move sp to secure stack; switch (*CMD) { case CMD_SYSCALL_TABLE: send_syscall_table(); break; } restore sp; 3 } 2 1 check_syscall_table() { send_cmd(cmd_syscall_table); settimer(timeout); } send_syscall_table() { get cur_syscall_table; for each entry i write cur_syscall_table[i]; response_ready(); } Secure Data Memory

15 Example Use Case Sends Command Collects Information Time skm_isr() { save sp; move sp to secure stack; switch (*CMD) { case CMD_SYSCALL_TABLE: send_syscall_table(); break; } restore sp; 3 } 2 1 check_syscall_table() { send_cmd(cmd_syscall_table); settimer(timeout); } send_syscall_table() { get cur_syscall_table; for each entry i write cur_syscall_table[i]; response_ready(); } 4 Secure Data Memory

16 Example Use Case Sends Command Analyzes Data Collects Information Time skm_isr() { save sp; move sp to secure stack; switch (*CMD) { case CMD_SYSCALL_TABLE: send_syscall_table(); break; } restore sp; 3 } send_syscall_table() { get cur_syscall_table; for each entry i write cur_syscall_table[i]; response_ready(); } 2 4 Secure Data Memory 5 1 check_syscall_table() { send_cmd(cmd_syscall_table); settimer(timeout); } recv_syscall_table() { cleartimer(timeout); retrieve current syscall table; for each entry i if (cur.table[i]!=org.table[i]) Raise alert! }

17 Challenges Monitored Core Secure Core n n n Secure Memory OS Command/Response identification Secure memory access control integrity and liveness guarantee

18 Registration Requested by, verified by Calculates a hash of s code Directly from physical frames Base address Page Size.text Size Loading Registration request Page table Information Page Table Hierarchy Virtual Address Space Physical Address Space

19 Registration Requested by, verified by Calculates a hash of s code Directly from physical frames Base address Page Size.text Size Loading Registration request Page table Information Find phys. frames of.text Page Table Hierarchy Virtual Address Space.text Physical Frames Physical Address Space

20 Registration Requested by, verified by Calculates a hash of s code Directly from physical frames Base address Page Size.text Size Loading Registration request Page table Information Find phys. frames of.text Page Table Hierarchy Virtual Address Space Calculate the hash of.text Match Not.text Physical Frames Begin operations Halt and alarm Physical Address Space

21 Secure Memory Access Control Who initiated memory transaction? Use the current program counter and page mapping information Registered.text info Secure Memory RAM Array Monitored Core Program Counter Page Table Base Address Within.text? Same with the registered one? Registered Page Table info Malicious Module

22 Secure Memory Access Control What if attacker modifies s page mapping? Physical Address Space Page Table Hierarchy Base Virtual Address Space.text Physical Frames Size

23 Secure Memory Access Control What if attacker modifies s page mapping? Physical Address Space Page Table Hierarchy Base Virtual Address Space.text Physical Frames Size Page Table Hierarchy Altered Malicious Module s Physical Frames

24 Secure Memory Access Control What if attacker modifies s page mapping? Solution: Regularly translate virt-to-phys address and verifies.text hash Physical Address Space Page Table Hierarchy Base Virtual Address Space.text Physical Frames Size Page Table Hierarchy Altered Malicious Module s Physical Frames

25 Heartbeat and Hashing Heartbeat Checks if is alive Only can respond Timeout Requests for HB Receives HB Sends HB Time

26 Heartbeat and Hashing Heartbeat Checks if is alive Only can respond Timeout Requests for HB Receives HB Sends HB Time.text hashing Checks if s code and page mapping have not been altered

27 Random Check Intervals To prevent TOCTTOU (Time Of Check To Time Of Use) attacks Attacker cannot guess the pattern of checks OP HB OP HB HS HB HS OP HB OP HS OP HB HB OP Time OP Operation (Send/Response/Analysis) HB Heartbeat (Request/Send/Receive) HS Hashing.text

28 Implementation Leon3 Core 1 (Monitored Core) Pipeline AHBRAM Secure Memory Secure Data/Stack Leon3 Core 2 (Secure Core) Pipeline Leon3 processor on Xilinx ZC702 FPGA SPARC V8, soft-core 83.3 MHz 256 MB MMU Access Control Controller Base Size Unused MMU AMBA AHB BUS AHB2AXI Bridge AHB2APB Bridge IRQ Linux Main Memory Multiprocessor Interrupt Controller IRQ

29 Implementation Leon3 Core 1 (Monitored Core) Pipeline Leon3 on-chip SRAM (128KB) AHBRAM Secure Memory Secure Data/Stack Leon3 Core 2 (Secure Core) Pipeline Leon3 processor on Xilinx ZC702 FPGA SPARC V8, soft-core 83.3 MHz 256 MB MMU Access Control Controller Base Size Unused MMU AMBA AHB BUS AHB2AXI Bridge AHB2APB Bridge IRQ Linux Main Memory Multiprocessor Interrupt Controller IRQ

30 Implementation Leon3 Core 1 (Monitored Core) Pipeline and for Secure Memory access control AHBRAM Secure Memory Secure Data/Stack Leon3 Core 2 (Secure Core) Pipeline Leon3 processor on Xilinx ZC702 FPGA SPARC V8, soft-core 83.3 MHz 256 MB MMU Access Control Controller Base Size Unused MMU AMBA AHB BUS AHB2AXI Bridge AHB2APB Bridge IRQ Linux Main Memory Multiprocessor Interrupt Controller IRQ

31 Implementation Leon3 Core 1 (Monitored Core) Pipeline AHBRAM Secure Memory Secure Data/Stack Leon3 Core 2 (Secure Core) Pipeline Leon3 processor on Xilinx ZC702 FPGA SPARC V8, soft-core 83.3 MHz 256 MB MMU Access Control Controller Base Size Unused MMU AMBA AHB BUS AHB2AXI Bridge AHB2APB Bridge IRQ Linux Main Memory Multiprocessor Interrupt Controller IRQ Unmodified Linux 3.8

32 Evaluation Use Cases 1) System call table integrity check 2) Hidden module detection

33 Evaluation Use Cases 1) System call table integrity check 2) Hidden module detection Main Memory Kernel Module List Module 1 Kernel Module Region (12MB) Module 2 Module 4

34 Evaluation Use Cases 1) System call table integrity check 2) Hidden module detection Main Memory Kernel Module List Module 1 Kernel Module Region (12MB) No matching module Module 2 Module 4 Module 3 (Hidden)

35 Evaluation Use Cases 1) System call table integrity check 2) Hidden module detection Sends Command Receives Result Traverses module list Finds orphan pages Time Main Memory Kernel Module List Module 1 Kernel Module Region (12MB) No matching module Module 2 Module 4 Module 3 (Hidden)

36 Evaluation Performance Overhead Average ratio of execution time to the case of No SPEC Benchmarks on the monitored core Heartbeat (100 ms).text hashing (100 ms) System call table check (100 ms) Hidden module detection (100 ms) bzip2 hmmer libquantum mcf sjeng Benchmark

37 Evaluation Performance Overhead Average ratio of execution time to the case of No SPEC Benchmarks on the monitored core In- Procedure Heartbeat (100 ms).text hashing (100 ms) System call table check (100 ms) Hidden module detection (100 ms) bzip2 hmmer libquantum mcf sjeng Benchmark

38 Evaluation Performance Overhead Average ratio of execution time to the case of No SPEC Benchmarks on the monitored core Memory traffic interference Heartbeat (100 ms).text hashing (100 ms) System call table check (100 ms) Hidden module detection (100 ms) bzip2 hmmer libquantum mcf sjeng Benchmark

39 Evaluation Performance Overhead Average ratio of execution time to the case of No SPEC Benchmarks on the monitored core Random order Random interval: [0,1,,199,200] ms Back-to-back with prob. of 5% Heartbeat (100 ms).text hashing (100 ms) System call table check (100 ms) Hidden module detection (100 ms) Random (random interval) bzip2 hmmer libquantum mcf sjeng Benchmark

40 Evaluation Hardware Cost Modified Leon3 Core 1 (Monitored Core) AHBRAM Leon3 Core 2 (Secure Core) Pipeline Secure Memory Secure Data/Stack Pipeline MMU Access Control Controller Base Size Unused MMU AMBA AHB BUS AHB2AXI Bridge AHB2APB Bridge IRQ Linux Main Memory Multiprocessor Interrupt Controller IRQ

41 Evaluation Hardware Cost Modified Leon3 Core 1 (Monitored Core) AHBRAM Leon3 Core 2 (Secure Core) Pipeline Secure Memory Secure Data/Stack Pipeline MMU Access Control Controller Base Size Unused MMU AMBA AHB BUS Resource Original W/ DragonBeam AHB2AXI Bridge AHB2APB Bridge Registers % Look-up Tables Multiprocessor Main % Interrupt Linux Memory Controller IRQ IRQ

42 Extension to Multiple Monitored Cores Extended to quad-core Works only for SMP Single Leon3 Core 1 (Monitored Core 1) Pipeline Secure Memory Secure Data/Stack Leon3 Core 4 (Secure Core) Pipeline MMU Access Control Controller Base Size Unused MMU Pipeline MMU Pipeline MMU Leon3 Core 2 (Monitored Core 2) Leon3 Core 3 (Monitored Core 3)

43 Extension to Multiple Monitored Cores Extended to quad-core Works only for SMP Single Monitored Cores 1 N-1 1 N-1 Mux Mux Extension for N-1 monitored cores Leon3 Core 1 (Monitored Core 1) Pipeline MMU Registered Base >= 0/1 Pipeline Secure Memory Secure Data/Stack < MMU 0/1 Transaction Master ID Leon3 Core 2 (Monitored Core 2) Access Control Controller Registered Base + Size Base Size Pipeline = Unused 0/1 Registered Leon3 Core 4 (Secure Core) MMU 0/1 Leon3 Core 3 (Monitored Core 3) Bus Interface Pipeline = MMU Transaction Master ID ID(Secure Core)

44 Extension to Multiple Monitored Cores Extended to quad-core Works only for SMP Single Leon3 Core 1 (Monitored Core 1) Pipeline Secure Memory Secure Data/Stack Leon3 Core 4 (Secure Core) Pipeline MMU Controller Base Access Size Control Resource Original W/ DragonBeam Unused MMU Dual Core Quad Core Registers % Look-up Tables % Pipeline MMU Pipeline Registers % Look-up Tables % MMU Leon3 Core 2 (Monitored Core 2) Leon3 Core 3 (Monitored Core 3)

45 Conclusion DragonBeam Framework HW/SW framework for trusted security monitoring Bootstrap trust into SW layer from trusted HW Multicore-based Expanded observability due to in-place monitoring Secure Kernel Module Allows for customized security modules to system developers Monitored Core Secure Core Applicati Applicati on n on Secure Memory OS Command/Response

46 Thank you