ProtoFlex Tutorial: Full-System MP Simulations Using FPGAs
|
|
|
- Loraine Lester
- 5 years ago
- Views:
Transcription
1 rotoflex Tutorial: Full-System M Simulations Using FGAs Eric S. Chung, Michael apamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai ROTOFLEX Computer Architecture Lab at Our work in this area has been supported in part by NSF, IBM, Intel, Sun, and Xilinx.
2 Overview art I: Basic rotoflex Concepts FGA Virtualization techniques BlueSARC FGA-accelerated simulator art II: Hands-on Technology review Access CMU s remote FGA infrastructure Compile and run code within an FGA-accelerated simulation of 16-CU UltraSARC III server Run real-time CM cache simulations 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 2
3 art I: Basic Concepts 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 3
4 Full-system Functional Simulators Convenient exploration of real (or future) HW Can boot OS, run commercial apps But too slow for large-scale (>100-way) M studies Existing functional simulators single-threaded High instrumentation overhead 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 4
5 FGA-based simulation Advantages Fast and flexible Low HW instrumentation performance overhead 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 5
6 FGA-based simulation Caveat: simulation w/ FGAs more complex than SW Large-M configurations (>100) expensive to scale Full-system support need device models + full ISA 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 6
7 Reducing Complexity 1 Hybrid Full-System Simulation 2 Multiprocessor Host Interleaving CU Memory Common-case behaviors Devices Uncommon behaviors 4-way Memory 4-way 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 7
8 Outline Hybrid Full-System Simulation Multiprocessor Host Interleaving BlueSARC Implementation Conclusion 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 8
9 Hybrid Full-System Simulation FGA host transplant 3 I/O instr CD FIBRE TERM C Host Simulator 1 Memory SCSI 2 GFX NIC CI 3 ways to map target components FGA-only Simulation-only Transplantable CUs can fallback to SW by transplanting between hosts Only common-case instructions/behaviors implemented in FGA Complex, rare behaviors relegated to software Transplants reduce full-system complexity 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 9
10 Multiprocessor Host Interleaving Advantages: # processors to model in functional simulator # soft cores implemented in FGA Trade away FGA throughput for smaller implementation 1-to-1 mapping between target and host CUs Decouple logical simulated size from FGA host size 1-to-1 Host processor in FGA can be made very simple 4-to-1 host interleaving 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 10
11 FGA Host rocessor Architecturally executes multiple contexts Existing multithreaded micro-architectures are good candidates Our design: Instruction-Interleaved ipeline Switch in new processor context on each cycle Simple, efficient design w/ no stalling or forwarding Long-latency tolerance (e.g., cache miss, transplants) Coherence is free between contexts mapped to same pipeline 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 11
12 Outline Hybrid Full-System Simulation Host M Interleaving BlueSARC Implementation Conclusion 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 12
13 BlueSARC Simulator Functionally models 16-CU UltraSARC III Server HW components are hosted on BEE2 FGA platform Berkeley Emulation Engine 2 5 Virtex-II ro 70s (~66 KLUTs) 2 embedded owercs per FGA Only use 2 out of 5 FGAs (pipeline + DDR controllers) Virtutech Simics used as full-system I/O simulator 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 13
14 BlueSARC Simulator Virtex II ro 70 Core 2 Duo 16-way ipeline rocessor Bus owerc (Hard core) Simulated I/O Devices (using full-system simulator) Interface to 2nd FGA (memory) owerc simulates unimplemented SARC instructions (~10-50 µsec) Ethernet Simics simulates devices, memorymapped I/O and DMA (~ µsec) 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 14
15 Hybrid host partitioning choices BlueSARC owerc405 Simics on C Integer ALU Register Windows Traps/Interrupts I-/D-MMU Memory + Atomics 36% special SARC insns Multimedia Floating oint Rare TLB operations 64% special SARC insns CI bus IS2200 Fibre Channel I21152 CI bridge IRQ bus Text Console SBBC CI device Serengeti I/O ROM Cheerio-hme NIC SCSI bus Implementation = 60% of basic ISA, 36% of special SARC insns, 0% devices 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 15
16 BlueSARC host microarchitecture 1 2, 3 4, ,10,11 12,13 14 Context Selector C, state x16 I-TLB 128-entry (2-way) x16 64KB I-cache RegFile Decode ALU 1 ALU 2 D-TLB 512-entry (2-way) x16 64KB D-cache Writeback Unit Transplant Unit I-TLB 16-entry (directmapped) x16 D-TLB 16-entry (fullyassoc) x16 Trap Unit Assist Unit owerc405 (transplant service processor) 64-bit ISA, SW-visible MMU, complex memory Multi-context state high # of pipeline stages Normal pipeline stage Transplant support unit 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 16
17 BlueSARC Simulator (continued) rocessing Nodes L1 caches Clock frequency Main memory Resources (Xilinx V270) Instrumentation Statistics Software bit UltraSARC III contexts 14-stage instruction-interleaved pipeline Split I/D, 64KB, 64B, direct-mapped, writeback Non-blocking loads/stores 16-entry MSHR, 4-entry store buffer 90MHz on Xilinx V270 4GB total 33.5 KLUTs (50%), 222 BRAMs (67%) w/o stats+debug 43.2 KLUTs (65%), 238 BRAMs (72%) All internal state fully traceable Attachable to FGA-based CM cache simulator 25K lines Bluespec HDL, 511 rules, 89 module types Runs unmodified Solaris + closed-source binaries 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 17
18 MIS erformance BlueSARC (90mhz) Simics-fast (2.0GHz C2Duo) Simics-trace 1.18 oracle bzip2 crafty gcc gzip parser vortex average 39x speedup on average over Simics-trace 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 18
19 One more thing Our latest application w/ BlueSARC: Trace CM L1 Caches InstructionCaches L2 Cache 8 ways Memory References Data Caches Statistics Cache Contents Statistics 16 64KB 2-way split I&D L1 caches 8-way seudo-lru Statistics 4MB 8-way L2 cache 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 19
20 Demo application BlueSARC Demo on BEE2 On-Line Transaction rocessing benchmark (TC-C) in Oracle Runs in Solaris 8 (unmodified binary) FGA + Memory directly loaded from Simics checkpoint 4 DDR2 Controllers + 4 GB memory Virtex-II ro 70 (owerc & BlueSARC) BEE2 latform Ethernet (to Simics on C) RS232 (Debugging) 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 20 20
21 Summary Two techniques for reducing complexity Hybrid full-system simulation M host interleaving Future work Timing extensions Larger-scale implementation (hundreds of CUs) Run-time instrumentation tools 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 21
22 art II: Hands-on Tutorial 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 22
23 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 23
24 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 24
25 Setup rocedures Divide up into FOUR groups Each group needs 1 laptop with: Remote Desktop Connection for Windows X Instructions: user/login: ramp/ramp 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 25
26 Live CM Cache Statistics Statistics updated in real-time on webpage: Click on tabs to watch statistics for any of the four BEE2 boards as they run simulations 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 26
27 Thanks! Any questions? Acknowledgements We would like to thank our colleagues in the RAM and TRUSS projects. 2-Mar-2008 RAM 2008 Tutorial / Eric S. Chung and Michael apamichael 27
ProtoFlex: FPGA Accelerated Full System MP Simulation
ProtoFlex: FPGA Accelerated Full System MP Simulation Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai Computer Architecture Lab at Our work in this area has been supported in part
FPGA-Accelerated Instrumentation
ROTOFLEX: FGA-Accelerated Instrumentation Michael K. apamichael, Eric S. Chung, James C. Hoe, Babak Falsafi, Ken Mai papamix@cs.cmu.edu, {echung, jhoe, babak, kenmai}@ece.cmu.edu ROTOFLEX Computer Architecture
ProtoFlex: FPGA-Accelerated Hybrid Simulator
ProtoFlex: FPGA-Accelerated Hybrid Simulator Eric S. Chung, Eriko Nurvitadhi James C. Hoe, Babak Falsafi, Ken Mai Computer Architecture Lab at Multiprocessor Simulation Simulating one processor in software
A Key Theme of CIS 371: Parallelism. CIS 371 Computer Organization and Design. Readings. This Unit: (In-Order) Superscalar Pipelines
A Key Theme of CIS 371: arallelism CIS 371 Computer Organization and Design Unit 10: Superscalar ipelines reviously: pipeline-level parallelism Work on execute of one instruction in parallel with decode
Full-System Timing-First Simulation
Full-System Timing-First Simulation Carl J. Mauer Mark D. Hill and David A. Wood Computer Sciences Department University of Wisconsin Madison The Problem Design of future computer systems uses simulation
Unit 8: Superscalar Pipelines
A Key Theme: arallelism reviously: pipeline-level parallelism Work on execute of one instruction in parallel with decode of next CIS 501: Computer Architecture Unit 8: Superscalar ipelines Slides'developed'by'Milo'Mar0n'&'Amir'Roth'at'the'University'of'ennsylvania'
Decoupling Dynamic Information Flow Tracking with a Dedicated Coprocessor
Decoupling Dynamic Information Flow Tracking with a Dedicated Coprocessor Hari Kannan, Michael Dalton, Christos Kozyrakis Computer Systems Laboratory Stanford University Motivation Dynamic analysis help
CPS104 Computer Organization and Programming Lecture 20: Superscalar processors, Multiprocessors. Robert Wagner
CS104 Computer Organization and rogramming Lecture 20: Superscalar processors, Multiprocessors Robert Wagner Faster and faster rocessors So much to do, so little time... How can we make computers that
RAMP-White / FAST-MP
RAMP-White / FAST-MP Hari Angepat and Derek Chiou Electrical and Computer Engineering University of Texas at Austin Supported in part by DOE, NSF, SRC,Bluespec, Intel, Xilinx, IBM, and Freescale RAMP-White
An FPGA Host-Multithreaded Functional Model for SPARC v8
An FPGA Host-Multithreaded Functional Model for SPARC v8 Zhangxi Tan xtan@cs.berkeley.edu Krste Asanovic krste@cs.berkeley.edu David Patterson pattersn@cs.berkeley.edu 1. Introduction The RAMP project
Department of Computer Science, Institute for System Architecture, Operating Systems Group. Real-Time Systems '08 / '09. Hardware.
Department of Computer Science, Institute for System Architecture, Operating Systems Group Real-Time Systems '08 / '09 Hardware Marcus Völp Outlook Hardware is Source of Unpredictability Caches Pipeline
Impact of Cache Coherence Protocols on the Processing of Network Traffic
Impact of Cache Coherence Protocols on the Processing of Network Traffic Amit Kumar and Ram Huggahalli Communication Technology Lab Corporate Technology Group Intel Corporation 12/3/2007 Outline Background
ATLAS: A Chip-Multiprocessor. with Transactional Memory Support
ATLAS: A Chip-Multiprocessor with Transactional Memory Support Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, and Kunle Olukotun Transactional Coherence and Consistency
Shengyue Wang, Xiaoru Dai, Kiran S. Yellajyosula, Antonia Zhai, Pen-Chung Yew Department of Computer Science & Engineering University of Minnesota
Loop Selection for Thread-Level Speculation, Xiaoru Dai, Kiran S. Yellajyosula, Antonia Zhai, Pen-Chung Yew Department of Computer Science & Engineering University of Minnesota Chip Multiprocessors (CMPs)
4. Shared Memory Parallel Architectures
Master rogram (Laurea Magistrale) in Computer cience and Networking High erformance Computing ystems and Enabling latforms Marco Vanneschi 4. hared Memory arallel Architectures 4.4. Multicore Architectures
Computer and Information Sciences College / Computer Science Department CS 207 D. Computer Architecture. Lecture 9: Multiprocessors
Computer and Information Sciences College / Computer Science Department CS 207 D Computer Architecture Lecture 9: Multiprocessors Challenges of Parallel Processing First challenge is % of program inherently
Microarchitecture Overview. Performance
Microarchitecture Overview Prof. Scott Rixner Duncan Hall 3028 rixner@rice.edu January 15, 2007 Performance 4 Make operations faster Process improvements Circuit improvements Use more transistors to make
SGI Challenge Overview
CS/ECE 757: Advanced Computer Architecture II (Parallel Computer Architecture) Symmetric Multiprocessors Part 2 (Case Studies) Copyright 2001 Mark D. Hill University of Wisconsin-Madison Slides are derived
CS 152 Computer Architecture and Engineering. Lecture 7 - Memory Hierarchy-II
CS 152 Computer Architecture and Engineering Lecture 7 - Memory Hierarchy-II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste
TraceBack: First Fault Diagnosis by Reconstruction of Distributed Control Flow
TraceBack: First Fault Diagnosis by Reconstruction of Distributed Control Flow Andrew Ayers Chris Metcalf Junghwan Rhee Richard Schooler VERITAS Emmett Witchel Microsoft Anant Agarwal UT Austin MIT Software
Why Use Simulation? Simics & dark2 Assignment 1. What is a Simulator? Full-System Simulation
Simics & dark2 Assignment 1 Håkan Zeffer Uppsala University, Sweden zeffer@it.uu.se Why Use Simulation? Understanding real systems More inspectable Less dangerous Fault injection Debugging Prototype HW
Microarchitecture Overview. Performance
Microarchitecture Overview Prof. Scott Rixner Duncan Hall 3028 rixner@rice.edu January 18, 2005 Performance 4 Make operations faster Process improvements Circuit improvements Use more transistors to make
The Nios II Family of Configurable Soft-core Processors
The Nios II Family of Configurable Soft-core Processors James Ball August 16, 2005 2005 Altera Corporation Agenda Nios II Introduction Configuring your CPU FPGA vs. ASIC CPU Design Instruction Set Architecture
An NVMe-based Offload Engine for Storage Acceleration Sean Gibb, Eideticom Stephen Bates, Raithlin
An NVMe-based Offload Engine for Storage Acceleration Sean Gibb, Eideticom Stephen Bates, Raithlin 1 Overview Acceleration for Storage NVMe for Acceleration How are we using (abusing ;-)) NVMe to support
BERKELEY PAR LAB. RAMP Gold Wrap. Krste Asanovic. RAMP Wrap Stanford, CA August 25, 2010
RAMP Gold Wrap Krste Asanovic RAMP Wrap Stanford, CA August 25, 2010 RAMP Gold Team Graduate Students Zhangxi Tan Andrew Waterman Rimas Avizienis Yunsup Lee Henry Cook Sarah Bird Faculty Krste Asanovic
System Simulator for x86
MARSS Micro Architecture & System Simulator for x86 CAPS Group @ SUNY Binghamton Presenter Avadh Patel http://marss86.org Present State of Academic Simulators Majority of Academic Simulators: Are for non
Chip-Multithreading Systems Need A New Operating Systems Scheduler
Chip-Multithreading Systems Need A New Operating Systems Scheduler Alexandra Fedorova Christopher Small Daniel Nussbaum Margo Seltzer Harvard University, Sun Microsystems Sun Microsystems Sun Microsystems
José F. Martínez 1, Jose Renau 2 Michael C. Huang 3, Milos Prvulovic 2, and Josep Torrellas 2
CHERRY: CHECKPOINTED EARLY RESOURCE RECYCLING José F. Martínez 1, Jose Renau 2 Michael C. Huang 3, Milos Prvulovic 2, and Josep Torrellas 2 1 2 3 MOTIVATION Problem: Limited processor resources Goal: More
Three basic multiprocessing issues
Three basic multiprocessing issues 1. artitioning. The sequential program must be partitioned into subprogram units or tasks. This is done either by the programmer or by the compiler. 2. Scheduling. Associated
RiceNIC. Prototyping Network Interfaces. Jeffrey Shafer Scott Rixner
RiceNIC Prototyping Network Interfaces Jeffrey Shafer Scott Rixner RiceNIC Overview Gigabit Ethernet Network Interface Card RiceNIC - Prototyping Network Interfaces 2 RiceNIC Overview Reconfigurable and
Leveraging OpenSPARC. ESA Round Table 2006 on Next Generation Microprocessors for Space Applications EDD
Leveraging OpenSPARC ESA Round Table 2006 on Next Generation Microprocessors for Space Applications G.Furano, L.Messina TEC- OpenSPARC T1 The T1 is a new-from-the-ground-up SPARC microprocessor implementation
Multithreading: Exploiting Thread-Level Parallelism within a Processor
Multithreading: Exploiting Thread-Level Parallelism within a Processor Instruction-Level Parallelism (ILP): What we ve seen so far Wrap-up on multiple issue machines Beyond ILP Multithreading Advanced
Performance study example ( 5.3) Performance study example
erformance study example ( 5.3) Coherence misses: - True sharing misses - Write to a shared block - ead an invalid block - False sharing misses - ead an unmodified word in an invalidated block CI for commercial
Lecture 11: SMT and Caching Basics. Today: SMT, cache access basics (Sections 3.5, 5.1)
Lecture 11: SMT and Caching Basics Today: SMT, cache access basics (Sections 3.5, 5.1) 1 Thread-Level Parallelism Motivation: a single thread leaves a processor under-utilized for most of the time by doubling
Itanium 2 Processor Microarchitecture Overview
Itanium 2 Processor Microarchitecture Overview Don Soltis, Mark Gibson Cameron McNairy, August 2002 Block Diagram F 16KB L1 I-cache Instr 2 Instr 1 Instr 0 M/A M/A M/A M/A I/A Template I/A B B 2 FMACs
Chapter 5. Introduction ARM Cortex series
Chapter 5 Introduction ARM Cortex series 5.1 ARM Cortex series variants 5.2 ARM Cortex A series 5.3 ARM Cortex R series 5.4 ARM Cortex M series 5.5 Comparison of Cortex M series with 8/16 bit MCUs 51 5.1
Building and Using the ATLAS Transactional Memory System
Building and Using the ATLAS Transactional Memory System Njuguna Njoroge, Sewook Wee, Jared Casper, Justin Burdick, Yuriy Teslyar, Christos Kozyrakis, Kunle Olukotun Computer Systems Laboratory Stanford
FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations
FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for oc Modeling in Full-System Simulations Michael K. Papamichael, James C. Hoe, Onur Mutlu papamix@cs.cmu.edu, jhoe@ece.cmu.edu, onur@cmu.edu
CSE Memory Hierarchy Design Ch. 5 (Hennessy and Patterson)
CSE 4201 Memory Hierarchy Design Ch. 5 (Hennessy and Patterson) Memory Hierarchy We need huge amount of cheap and fast memory Memory is either fast or cheap; never both. Do as politicians do: fake it Give
The Sun Fireplane Interconnect in the Mid- Range Sun Fire Servers
TAK IT TO TH NTH Alan Charlesworth icrosystems The Fireplane Interconnect in the id- Range Fire Servers Vertical & Horizontal Scaling any CUs in one box Cache-coherent shared memory (S) Usually proprietary
Computer Systems Architecture I. CSE 560M Lecture 19 Prof. Patrick Crowley
Computer Systems Architecture I CSE 560M Lecture 19 Prof. Patrick Crowley Plan for Today Announcement No lecture next Wednesday (Thanksgiving holiday) Take Home Final Exam Available Dec 7 Due via email
Software-Controlled Multithreading Using Informing Memory Operations
Software-Controlled Multithreading Using Informing Memory Operations Todd C. Mowry Computer Science Department University Sherwyn R. Ramkissoon Department of Electrical & Computer Engineering University
Lecture 14: Multithreading
CS 152 Computer Architecture and Engineering Lecture 14: Multithreading John Wawrzynek Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~johnw
Yet Another Implementation of CoRAM Memory
Dec 7, 2013 CARL2013@Davis, CA Py Yet Another Implementation of Memory Architecture for Modern FPGA-based Computing Shinya Takamaeda-Yamazaki, Kenji Kise, James C. Hoe * Tokyo Institute of Technology JSPS
History. PowerPC based micro-architectures. PowerPC ISA. Introduction
PowerPC based micro-architectures Godfrey van der Linden Presentation for COMP9244 Software view of Processor Architectures 2006-05-25 History 1985 IBM started on AMERICA 1986 Development of RS/6000 1990
ECE332, Week 2, Lecture 3. September 5, 2007
ECE332, Week 2, Lecture 3 September 5, 2007 1 Topics Introduction to embedded system Design metrics Definitions of general-purpose, single-purpose, and application-specific processors Introduction to Nios
ECE332, Week 2, Lecture 3
ECE332, Week 2, Lecture 3 September 5, 2007 1 Topics Introduction to embedded system Design metrics Definitions of general-purpose, single-purpose, and application-specific processors Introduction to Nios
Hardware Design. MicroBlaze 7.1. This material exempt per Department of Commerce license exception TSU Xilinx, Inc. All Rights Reserved
Hardware Design MicroBlaze 7.1 This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: List the MicroBlaze 7.1 Features List
TDT Coarse-Grained Multithreading. Review on ILP. Multi-threaded execution. Contents. Fine-Grained Multithreading
Review on ILP TDT 4260 Chap 5 TLP & Hierarchy What is ILP? Let the compiler find the ILP Advantages? Disadvantages? Let the HW find the ILP Advantages? Disadvantages? Contents Multi-threading Chap 3.5
Learning Curve for Parallel Applications. 500 Fastest Computers
Learning Curve for arallel Applications ABER molecular dynamics simulation program Starting point was vector code for Cray-1 145 FLO on Cray90, 406 for final version on 128-processor aragon, 891 on 128-processor
Architectural Support for Operating Systems
Architectural Support for Operating Systems Today Computer system overview Next time OS components & structure Computer architecture and OS OS is intimately tied to the hardware it runs on The OS design
Chapter Seven Morgan Kaufmann Publishers
Chapter Seven Memories: Review SRAM: value is stored on a pair of inverting gates very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: value is stored as a charge on capacitor (must be
Fast access ===> use map to find object. HW == SW ===> map is in HW or SW or combo. Extend range ===> longer, hierarchical names
Fast access ===> use map to find object HW == SW ===> map is in HW or SW or combo Extend range ===> longer, hierarchical names How is map embodied: --- L1? --- Memory? The Environment ---- Long Latency
Fast access ===> use map to find object. HW == SW ===> map is in HW or SW or combo. Extend range ===> longer, hierarchical names
Fast access ===> use map to find object HW == SW ===> map is in HW or SW or combo Extend range ===> longer, hierarchical names How is map embodied: --- L1? --- Memory? The Environment ---- Long Latency
GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator Framework. Jan Gray CARRV2017: 2017/10/14
GRVI halanx Update: A Massively arallel RISC-V FGA Accelerator Framework Jan Gray jan@fpga.org http://fpga.org CARRV2017: 2017/10/14 FGA Datacenter Accelerators Are Almost Mainstream Catapult v2. Intel
NOW Handout Page 1. Recap: Gigaplane Bus Timing. Scalability
Recap: Gigaplane Bus Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Address Rd A Rd B Scalability State Arbitration 1 4,5 2 Share ~Own 6 Own 7 A D A D A D A D A D A D A D A D CS 258, Spring 99 David E. Culler
CMSC 411 Computer Systems Architecture Lecture 13 Instruction Level Parallelism 6 (Limits to ILP & Threading)
CMSC 411 Computer Systems Architecture Lecture 13 Instruction Level Parallelism 6 (Limits to ILP & Threading) Limits to ILP Conflicting studies of amount of ILP Benchmarks» vectorized Fortran FP vs. integer
CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP
CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer
General Purpose Signal Processors
General Purpose Signal Processors First announced in 1978 (AMD) for peripheral computation such as in printers, matured in early 80 s (TMS320 series). General purpose vs. dedicated architectures: Pros:
ZSIM: FAST AND ACCURATE MICROARCHITECTURAL SIMULATION OF THOUSAND-CORE SYSTEMS
ZSIM: FAST AND ACCURATE MICROARCHITECTURAL SIMULATION OF THOUSAND-CORE SYSTEMS DANIEL SANCHEZ MIT CHRISTOS KOZYRAKIS STANFORD ISCA-40 JUNE 27, 2013 Introduction 2 Current detailed simulators are slow (~200
Hardware and Software solutions for scaling highly threaded processors. Denis Sheahan Distinguished Engineer Sun Microsystems Inc.
Hardware and Software solutions for scaling highly threaded processors Denis Sheahan Distinguished Engineer Sun Microsystems Inc. Agenda Chip Multi-threaded concepts Lessons learned from 6 years of CMT
ZSIM: FAST AND ACCURATE MICROARCHITECTURAL SIMULATION OF THOUSAND-CORE SYSTEMS
ZSIM: FAST AND ACCURATE MICROARCHITECTURAL SIMULATION OF THOUSAND-CORE SYSTEMS DANIEL SANCHEZ MIT CHRISTOS KOZYRAKIS STANFORD ISCA-40 JUNE 27, 2013 Introduction 2 Current detailed simulators are slow (~200
Computer Science 146. Computer Architecture
Computer Science 46 Computer Architecture Spring 24 Harvard University Instructor: Prof dbrooks@eecsharvardedu Lecture 22: More I/O Computer Science 46 Lecture Outline HW5 and Project Questions? Storage
Lecture 12. Motivation. Designing for Low Power: Approaches. Architectures for Low Power: Transmeta s Crusoe Processor
Lecture 12 Architectures for Low Power: Transmeta s Crusoe Processor Motivation Exponential performance increase at a low cost However, for some application areas low power consumption is more important
CS/ECE 757: Advanced Computer Architecture II (Parallel Computer Architecture) Introduction (Chapter 1)
CS/ECE 757: Advanced Computer Architecture II (arallel Computer Architecture) Introduction (Chapter 1) Copyright 2001 Mark D. Hill University of Wisconsin-Madison Slides are derived from work by Sarita
Outline EEL 5764 Graduate Computer Architecture. Chapter 3 Limits to ILP and Simultaneous Multithreading. Overcoming Limits - What do we need??
Outline EEL 7 Graduate Computer Architecture Chapter 3 Limits to ILP and Simultaneous Multithreading! Limits to ILP! Thread Level Parallelism! Multithreading! Simultaneous Multithreading Ann Gordon-Ross
CS 152 Computer Architecture and Engineering. Lecture 18: Multithreading
CS 152 Computer Architecture and Engineering Lecture 18: Multithreading Krste Asanovic Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~krste
High performance computing. Memory
High performance computing Memory Performance of the computations For many programs, performance of the calculations can be considered as the retrievability from memory and processing by processor In fact
Arquitecturas y Modelos de. Multicore
Arquitecturas y Modelos de rogramacion para Multicore 17 Septiembre 2008 Castellón Eduard Ayguadé Alex Ramírez Opening statements * Some visionaries already predicted multicores 30 years ago And they have
ECE 468 Computer Architecture and Organization Lecture 1
ECE 468 Computer Architecture and Organization Lecture 1 September 7, 1999 ece 468 Intro.1 What is "Computer Architecture" Co-ordination of levels of abstraction Application Compiler Instr. Set Proc. Operating
Exploration of Cache Coherent CPU- FPGA Heterogeneous System
Exploration of Cache Coherent CPU- FPGA Heterogeneous System Wei Zhang Department of Electronic and Computer Engineering Hong Kong University of Science and Technology 1 Outline ointroduction to FPGA-based
Exploring different level of parallelism Instruction-level parallelism (ILP): how many of the operations/instructions in a computer program can be performed simultaneously 1. e = a + b 2. f = c + d 3.
Performance of Multithreaded Chip Multiprocessors and Implications for Operating System Design
Performance of Multithreaded Chip Multiprocessors and Implications for Operating System Design Based on papers by: A.Fedorova, M.Seltzer, C.Small, and D.Nussbaum Pisa November 6, 2006 Multithreaded Chip
CS4230 Parallel Programming. Lecture 3: Introduction to Parallel Architectures 8/28/12. Homework 1: Parallel Programming Basics
CS4230 Parallel Programming Lecture 3: Introduction to Parallel Architectures Mary Hall August 28, 2012 Homework 1: Parallel Programming Basics Due before class, Thursday, August 30 Turn in electronically
Grassroots ASPLOS. can we still rethink the hardware/software interface in processors? Raphael kena Poss University of Amsterdam, the Netherlands
Grassroots ASPLOS can we still rethink the hardware/software interface in processors? Raphael kena Poss University of Amsterdam, the Netherlands ASPLOS-17 Doctoral Workshop London, March 4th, 2012 1 Current
PARALLEL COMPUTER ARCHITECTURES
8 ARALLEL COMUTER ARCHITECTURES 1 CU Shared memory (a) (b) Figure 8-1. (a) A multiprocessor with 16 CUs sharing a common memory. (b) An image partitioned into 16 sections, each being analyzed by a different
EECS 470. Lecture 18. Simultaneous Multithreading. Fall 2018 Jon Beaumont
Lecture 18 Simultaneous Multithreading Fall 2018 Jon Beaumont http://www.eecs.umich.edu/courses/eecs470 Slides developed in part by Profs. Falsafi, Hill, Hoe, Lipasti, Martin, Roth, Shen, Smith, Sohi,
Lecture 7: Introduction to Co-synthesis Algorithms
Design & Co-design of Embedded Systems Lecture 7: Introduction to Co-synthesis Algorithms Sharif University of Technology Computer Engineering Dept. Winter-Spring 2008 Mehdi Modarressi Topics for today
Chapter Seven. Memories: Review. Exploiting Memory Hierarchy CACHE MEMORY AND VIRTUAL MEMORY
Chapter Seven CACHE MEMORY AND VIRTUAL MEMORY 1 Memories: Review SRAM: value is stored on a pair of inverting gates very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: value is stored
Martin Kruliš, v
Martin Kruliš 1 Optimizations in General Code And Compilation Memory Considerations Parallelism Profiling And Optimization Examples 2 Premature optimization is the root of all evil. -- D. Knuth Our goal
EFFECTS OF MICROWAVES Robust Computer Architectures
COMUTER EFFECTS OF MICROWAVES Robust Computer Architectures rof. Electrical & Computer Engineering, College ark UNIVERSITY OF MARYLAND COMUTER System Modeling HDL Model of Chip SIMULATOR Results of hysical
Advanced Memory Organizations
CSE 3421: Introduction to Computer Architecture Advanced Memory Organizations Study: 5.1, 5.2, 5.3, 5.4 (only parts) Gojko Babić 03-29-2018 1 Growth in Performance of DRAM & CPU Huge mismatch between CPU
QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs
QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs Intel: Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Gottschlich
Adapted from David Patterson s slides on graduate computer architecture
Mei Yang Adapted from David Patterson s slides on graduate computer architecture Introduction Ten Advanced Optimizations of Cache Performance Memory Technology and Optimizations Virtual Memory and Virtual
Processors, Performance, and Profiling
Processors, Performance, and Profiling Architecture 101: 5-Stage Pipeline Fetch Decode Execute Memory Write-Back Registers PC FP ALU Memory Architecture 101 1. Fetch instruction from memory. 2. Decode
SimXMD Co-Debugging Software and Hardware in FPGA Embedded Systems
University of Toronto FPGA Seminar SimXMD Co-Debugging Software and Hardware in FPGA Embedded Systems Ruediger Willenberg and Paul Chow High-Performance Reconfigurable Computing Group University of Toronto
SimXMD: Simulation-based HW/SW Co-Debugging for FPGA Embedded Systems
FPGAworld 2014 SimXMD: Simulation-based HW/SW Co-Debugging for FPGA Embedded Systems Ruediger Willenberg and Paul Chow High-Performance Reconfigurable Computing Group University of Toronto September 9,
Simultaneous Multithreading on Pentium 4
Hyper-Threading: Simultaneous Multithreading on Pentium 4 Presented by: Thomas Repantis trep@cs.ucr.edu CS203B-Advanced Computer Architecture, Spring 2004 p.1/32 Overview Multiple threads executing on
Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches
Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches Nikos Hardavellas Michael Ferdman, Babak Falsafi, Anastasia Ailamaki Carnegie Mellon and EPFL Data Placement in Distributed
Maximizing Server Efficiency from μarch to ML accelerators. Michael Ferdman
Maximizing Server Efficiency from μarch to ML accelerators Michael Ferdman Maximizing Server Efficiency from μarch to ML accelerators Michael Ferdman Maximizing Server Efficiency with ML accelerators Michael
Introduction to gem5. Nizamudheen Ahmed Texas Instruments
Introduction to gem5 Nizamudheen Ahmed Texas Instruments 1 Introduction A full-system computer architecture simulator Open source tool focused on architectural modeling BSD license Encompasses system-level
Performance. CS 3410 Computer System Organization & Programming. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]
![Performance. CS 3410 Computer System Organization & Programming. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]](/thumbs/93/113797768.jpg "Performance. CS 3410 Computer System Organization & Programming. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]")
Performance CS 3410 Computer System Organization & Programming [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Performance Complex question How fast is the processor? How fast your application runs?
1. Microprocessor Architectures. 1.1 Intel 1.2 Motorola
1. Microprocessor Architectures 1.1 Intel 1.2 Motorola 1.1 Intel The Early Intel Microprocessors The first microprocessor to appear in the market was the Intel 4004, a 4-bit data bus device. This device
Reference. T1 Architecture. T1 ( Niagara ) Case Study of a Multi-core, Multithreaded
Reference Case Study of a Multi-core, Multithreaded Processor The Sun T ( Niagara ) Computer Architecture, A Quantitative Approach, Fourth Edition, by John Hennessy and David Patterson, chapter. :/C:8
Course web site: teaching/courses/car. Piazza discussion forum:
Announcements Course web site: http://www.inf.ed.ac.uk/ teaching/courses/car Lecture slides Tutorial problems Courseworks Piazza discussion forum: http://piazza.com/ed.ac.uk/spring2018/car Tutorials start
Exploitation of instruction level parallelism
Exploitation of instruction level parallelism Computer Architecture J. Daniel García Sánchez (coordinator) David Expósito Singh Francisco Javier García Blas ARCOS Group Computer Science and Engineering
CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP
CISC 662 Graduate Computer Architecture Lecture 13 - Limits of ILP Michela Taufer http://www.cis.udel.edu/~taufer/teaching/cis662f07 Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer
CPU Architecture Overview. Varun Sampath CIS 565 Spring 2012
CPU Architecture Overview Varun Sampath CIS 565 Spring 2012 Objectives Performance tricks of a modern CPU Pipelining Branch Prediction Superscalar Out-of-Order (OoO) Execution Memory Hierarchy Vector Operations
What are Clusters? Why Clusters? - a Short History
What are Clusters? Our definition : A parallel machine built of commodity components and running commodity software Cluster consists of nodes with one or more processors (CPUs), memory that is shared by
Introduction to Microprocessor
Introduction to Microprocessor Slide 1 Microprocessor A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device That reads binary instructions from a storage device