H8S and H8/300H Monitor

Transcription

1 H8S and H8/300H Monitor TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICD In-Circuit Debugger... Processor Architecture Manuals... H8S... H8S and H8/300H Monitor... 1 Brief Overview of Documents for New Users... 4 Warning... 5 Quick Start of the ESI ROM-Monitor... 6 Quick Start of the Serial ROM-Monitor... 8 Troubleshooting FAQ FAQ for Monitor 10 FAQ for Monitor H8 10 Basics Monitor Features 11 Hardware Breakpoints 11 Monitor Files 12 Address Layout 13 Vector Table 14 Interrupt Control Mode of H8S 14 Configuration 15 Specific SYStem Commands SYStem.CPU CPU type 16 SYStem.CpuAccess Run-time memory access (intrusive) 16 SYStem.MemAccess Real-time memory access (non-intrusive) 17 SYStem.Mode Establish the communication with the CPU 17 SYStem.Option Advanced Advanced 18 SYStem.Option BrkVector Breakpoint trap 18 SYStem.Option IMASKASM Disable interrupts while single stepping 18 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 19 General Settings and Restrictions H8S and H8/300H Monitor 1

2 General Restrictions 20 Memory Classes Support Available Tools 22 Compilers 23 Compilers H8_300H 23 Compilers H8S 23 Target Operating Systems 24 3rd Party Tool Integrations 24 Products Product Information 25 Order Information 25 H8S and H8/300H Monitor 2

3 H8S and H8/300H Monitor Version 06-Nov-2017 P:0123BC \\IARH83H\iarh83h\sieve+66 X!... MIX AI E::w.d.l addr/line code label mnemonic comment { 696 primz = i + i + 3; P:0123BC 0FE5 mov.l er6,er5 P:0123BE 0AD6 add.l er5,er6 P:0123C0 0B86 adds.l #2,er6 P:0123C2 0B06 adds.l #1,er6 697 k = i + primz; P:0123C P:0123C8 0AE5 add.l er6,er5 P:0123CA 01006FF60004 mov.l er6,@(4,sp) ; er6,@(pri E::w.v.f /l /c E::w.v.w { flags = (1, 1, 1, 1, 1, 1, 1, 1, 1, 1 sieve(); ast = (word = 0x0, count = 12346, lef -000 sieve() i = 0 primz = 1 k = anzahl = 0 H8S and H8/300H Monitor 3

4 Brief Overview of Documents for New Users Architecture-independent information: Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows. General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands. Architecture-specific information: Processor Architecture Manuals : These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows: - Choose Help menu > Processor Architecture Manual. RTOS Debuggers (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware debugging. H8S and H8/300H Monitor 4

5 Warning NOTE: Do not connect or remove probe from target while target power is ON. Power up: Switch on emulator first, then target Power down: Switch off target first, then emulator H8S and H8/300H Monitor 5

6 Quick Start of the ESI ROM-Monitor Starting up the ROM Monitor is done as follows: 1. Select the device B: for the ROM Monitor. b: 2. Power the system down (optional). sys.d This instruction is necessary when the system is restarted. When the system is active while you try to reinitialize it, you get an error message. 3. Map the EPROM simulator. The mapping of the EPROM simulator is described in the Emulator Reference Manual. map.rom 0x0--0x1ffff Load the application program. d.load.ubrof appl.dbg The format of the Data.LOAD command depends on the file format generated by the compiler. The corresponding options for all available compilers are listed in the compiler list. A detailed description of the Data.LOAD command is given in the Emulator Reference Manual. 4. Load the monitor program. Usually the monitor program runs from address 200 in the Eprom Simulator RAM. d.load.s1 romh8a.s1 /ny Set other vector locations as required. The NMI and one of the four software traps must point into the monitor. 5. Set the CPU type in the monitor configuration table (0x330). d.s 0x330 0x2 6. Set the CPU derivative in the system window. sys.cpu H8S2655 H8S and H8/300H Monitor 6

7 7. Set the address mode of the CPU. sys.o advanced on 8. Set the TRAP vector for the software breakpoints. sys.o brkvector 0x0 9. Set the polarity of the Reset and NMI signal according to your target. x.respol - x.nmipol - x.nmibreak on 10. Start the ROM Monitor. If the RESET output of the ESI is not connected you must perform a reset manually. sys.up A typical start sequence is shown below: The EPROM (8-bit) is in the addressrange 0x0--0x1ffff b: sys.d winclear map.res map.rom 0x0--0x1ffff d.load.ubrof appl.dbg d.load.s1 romh8a.s1 /ny d.s 0x330 0x2 sys.cpu H8S2655 sys.o advanced on sys.o bv 0x0 x.respol - x.nmipol - x.nmibreak on sys.up r.s pc start ; select the Debugger device ; switch the system down ; clear all windows ; map the EPROM simulator ; load the application ; overload this with the monitor ; set cpu code in monitor configuration ; set cpu derivative ; set address mode of the cpu ; set number of trap for software breaks ; adapt the polarity of RES and NMI ; enables the connection of the NMI signal ; power the system up ; set program counter The start up can be automated by using the programming language PRACTICE. H8S and H8/300H Monitor 7

8 Quick Start of the Serial ROM-Monitor Starting up the ROM Monitor is done as follows: 1. Prepare the monitor-software. 2. Select the device B: for the ROM Monitor. b: 3. Power the system down before pressing the reset button. sys.d This instruction is necessary when the system is restarted. When the system is active while you try to reinitialize it, you get an error message. 4. Set the CPU derivative in the system window. sys.cpu H8S Set the address mode of the CPU. sys.o advanced on 6. Set the TRAP vector for the software breakpoints. sys.o bv 0 7. Define the communication parameters. sys.port COM1 baud= Press the reset button on the target to initialize the monitor. 9. Activate the monitor. sys.up H8S and H8/300H Monitor 8

9 10. Load the application program. d.load.ubrof appl.dbg The format of the Data.LOAD command depends on the file format generated by the compiler. The corresponding options for all available compilers are listed in the compiler list. A detailed description of the Data.LOAD command is given in the Emulator Reference Manual. A typical start sequence is shown below: b: sys.d winclear sys.cpu H8S2655 sys.o advanced on sys.o bv 0x0 sys.port COM1 baud=57600 sys.up d.load.ubrof appl.dbg r.s pc start ; select the Debugger device ; switch the system down ; clear all windows ; set cpu derivative ; set address mode of the cpu ; set number of trap for software breaks ; define communication parameters ; power the system up ; load the application ; set program counter The start up can be automated by using the programming language PRACTICE. H8S and H8/300H Monitor 9

10 Troubleshooting No information available: FAQ FAQ for Monitor EPROM Simulator Error on Data Modification Ref: 0056 Step or Breakpoint Fails Ref: 0061 Stepping Fails when Executing MOV SP,xxx Ref: 0062 Why crashes ROM monitor after modification of EPROM? Check that there is enough space left on the stack. See also "Restrictions for Stack Requirements". Why does single step or breakpoint not work? Check that there is enough space left on the stack before and after the execution of the instruction. See "Restrictions for Stack Requirements". Make sure that the single step and INT3 vector (1 + 3) are valid and point to the correct monitor entry. Why does stepping fail, when executing a MOV SP,xxx instruction? Check that there is enough space left on the stack before and after the execution of the instruction. See "Restrictions for Stack Requirements". Check that the value for the CP is within limits for the CPU and that the register space ist not beeing overwritten by the stack. See "Restrictions for Stack Requirements". FAQ for Monitor H8 No information available H8S and H8/300H Monitor 10

11 Basics Monitor Features The monitor requires no stack during startup and memory operations. A valid stack is only required for single step and go commands (stack pointer must be set by the user). This allows to use the monitor even when the stack is not valid. External RAM memory is not required during startup and for memory operations. This allows to use the monitor also on not fully functional hardware. The NMI pin of the EPROM Simulator can be used to manually stop the target program. The serial version uses the receive interrupt of the SCI to stop the emulation. Hardware Breakpoints Address Breaks (Processor-Type 5) The Address-Break-Controller of the CPU is used to provide a Read-Breakpoint which reacts on program fetch cycles. It generates an address break interrupt which is not maskable. In the serial version, it is helpful to use the Address-Break-Controller as one program breakpoint in ROM and Flash areas. It doesn t work as a break before make breakpoint (see hardware manual chapter Address Breaks ), but it is the only way to stop the cpu on a specified point. For doing this, the read-only area must be mapped as BOnchip. Then a program breakpoint is automatically converted to a Read-Breakpoint. For example: map.bonchip 0--1ffff PC-Break-Controller (Processor-Types 6 and 7) The PC-Break-Controller of the CPU is used to provide Read-, Write- and Program-Breakpoints. For breaking at hardware breakpoints, the interrupt-mask has to be set to a level that the PBC interrupt is accepted. Before every start of the emulation, the PBC is activated in the Module Stop Register and the PBC interrupt priority is set to 7 by the monitor. In the serial version, it is helpful to use the PC-Break-Controller for program breakpoints in ROM and Flash areas. For doing this, the read-only area must be mapped as BOnchip. Then a program breakpoint is automatically converted to a hardware breakpoint. For example: map.bonchip 0--1ffff H8S and H8/300H Monitor 11

12 Monitor Files The different s-record monitor files are for the following applications: File Host Interface EPROM bus-size Address Mode romh8a.s1 ESI 8-bit advanced romh8aw.s1 ESI 16-bit advanced romh8as.s1 Serial --- advanced romh8n.s1 ESI 8-bit normal romh8nw.s1 ESI 16-bit normal romh8ns.s1 Serial --- normal romh8as.s1 and romh8ns.s1 are precompiled files for the serial version of the monitor with the following configuration settings: proctype mon_imask0 mon_imask1 scichannel scibrr scibase pllfactor H8S/265x 0x3 0x7 SCI0 0x0A 0xFFFF78 0x0 The general source file is romh8.asm. This source file should not be modified, it is only included for reference purposes. H8S and H8/300H Monitor 12

13 Address Layout The Rom Monitor is freely relocatable by reassembling the source. The communication area for the Eprom Simulator is located at the fixed address 1000 to 1FFF for 8-bit EPROMs. For 16-bit EPROMs the communication area is at address FFF. The serial version doesn t need a communication area. Communication with the host is done via one of the serial interfaces of the CPU. The monitor program consists of four parts: Vector Table Configuration Table Monitor Program Code Monitor Communication Area (ESI Version only) The '.s1' and '.asm' files contain the first three parts of the monitor. The address layout of the default monitor is as follows: 0x x016F 0x x032F 0x x03FF 0x x04FF 0x x0FFF 0x x17FF 0x x1FFF Vector Table Monitor Code Configuration Table Reserved for Vector Table of DTC-Controller (only H8S) Monitor Code (ESI Version) Monitor Code (Serial Version) Communication Area 8bit EPROM (ESI Version only) H8S and H8/300H Monitor 13

14 Vector Table For the first tests of a software, the '.s1' files can be loaded with vector and configuration table. When the vector table becomes part of the application, it is not loaded with the monitor. Instead the table is setup according to the application. Some vectors must be set up to point into the monitor program code. The entry points are located at the beginning of the monitor. vector # entry point usage x200 Power-On Reset x200 Manual Reset (only for H8S) x280 NMI (Manual Break of ESI Version) x280 Breakpoint Trap (can be changed) x280 PC Break Controller (PBC) x280 RXI (Manual Break of Serial Version) yyyy 0x300 Any unused vector may be handled by the monitor The Breakpoint Trap Vector can be configured by the SYStem.Option BrkVector command (0, 1, 2 or 3 can be selected for the vectors 8, 9, 10 and 11). The default is vector 8. Interrupt Control Mode of H8S The serial monitor doesn't change the interrupt control mode of the H8S, but the SCI control level is set to high and SCI priority is set to 0x7 before every start of the emulation. So, if the emulation shall be stopped by pressing the break button, the user must take care that the RXI interrupt isn't masked. If it is masked, then the emulation can be stopped by triggering an NMI. H8S and H8/300H Monitor 14

15 Configuration The configuration table of the monitor must always be located directly before the monitor main program code. The default location used in binary files is 330 (hex). Processor type (0x330) 0x1 = H8/300H 0x2 = H8S/265x (default) 0x3 = H8S/23xx 0x4 = H8S/224x 0x5 = H8S/21xx 0x6 = H8S/222x/223x 0x7 = H8S/262x/263x/264x U- and UI-Bit of Monitor Interrupt Mask (0x331) bit 0 = I-Bit (default = 1) bit 1 = UI-Bit (default = 1) I2..0 of Monitor Interrupt Mask (0x332) bit 2..0 = I2..0 (default = 0x7) The following settings are only needed for the serial version. The files romh8as.s1 and romh8ns.s1 are precompiled with the mentioned default settings. Program this precompiled or your own version to your target EPROM or Flash before starting the host driver. Used SCI Channel (0x334) 0x0 = SCI0 (default) 0x1 = SCI1 0x2 = SCI2 Value of the Bit Rate Register (0x335) 0xa = default (57.6 kbit/s with a 20 MHz clock) Base address of the used serial channel (0x338) 0xFFFF78 = default On-chip PLL multiplication factor (0x33C) 0x0 = PLL x1 (default) 0x1 = PLL x2 0x2 = PLL x4 0x3 = PLL off H8S and H8/300H Monitor 15

16 Specific SYStem Commands SYStem.CPU CPU type Format: SYStem.CPU <type> <mode>: H83001 H83002 Selects the processor type. The ROM monitor software requires also a modification in the configuration table for different processor types. SYStem.CpuAccess Run-time memory access (intrusive) Format: SYStem.CpuAccess Enable Denied Nonstop Default: Denied. Enable Denied Nonstop Allow intrusive run-time memory access. In order to perform a memory read or write while the CPU is executing the program, the debugger stops the program execution shortly. Each short stop takes ms depending on the speed of the debug interface and on the number of the read/write accesses required. A red S in the state line of the TRACE32 main window indicates this intrusive behavior of the debugger. Lock intrusive run-time memory access. Lock all features of the debugger that affect the run-time behavior. Nonstop reduces the functionality of the debugger to: Run-time access to memory and variables Trace display The debugger inhibits the following: To stop the program execution All features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints, etc.) H8S and H8/300H Monitor 16

17 SYStem.MemAccess Real-time memory access (non-intrusive). Format: SYStem.MemAccess CPU Denied <cpu_specific> SYStem.ACCESS (deprecated) CPU Denied (default) Real-time memory access during program execution to target is enabled. Real-time memory access during program execution to target is disabled. SYStem.Mode Establish the communication with the CPU Format: SYStem.Mode <mode> <mode>: Down NoDebug Go Up Default: Down. Selects the target operating mode. tbd. Down NoDebug Go Up The CPU is in reset. Debug mode is not active. Default state and state after fatal errors. The CPU is running. Debug mode is not active. Debug port is tristate. In this mode the target should behave as if the debugger is not connected. The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs. The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging. If the mode Go is selected, this mode will be entered, but the control button in the SYStem window jumps to the mode UP. H8S and H8/300H Monitor 17

18 SYStem.Option Advanced Advanced Format: SYStem.Option Advanced [ON OFF] Defines the address mode of the CPU. OFF ON Normal address mode (64 K). Advanced address mode (16 M). SYStem.Option BrkVector Breakpoint trap Format: SYStem.Option BrkVector <0..3> Defines the number of the TRAPA-Instruction used for breakpoints and single stepping. The default is TRAPA #0. SYStem.Option IMASKASM Disable interrupts while single stepping Format: SYStem.Option IMASKASM [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. H8S and H8/300H Monitor 18

19 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping Format: SYStem.Option IMASKHLL [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. H8S and H8/300H Monitor 19

20 General Settings and Restrictions General Restrictions Stack Memory The ROM debugger needs 44 bytes of memory on the current stack for starting and stopping the emulation. H8S and H8/300H Monitor 20

21 Memory Classes Memory Class D P Description Data Program H8S and H8/300H Monitor 21

22 Support Available Tools CPU ICE FIRE ICD DEBUG ICD MONITOR H8S/2319 YES YES H8S/2329 YES YES H8S/2339 YES YES H8S/2367 YES YES H8S/2368 YES YES H8S/2377 YES YES H8S/2378 YES YES H8S/2462 YES YES H8S/2463 YES YES H8S/2472 YES YES H8S/2646 YES H8SX/1642 YES YES H8SX/1644 YES YES H8SX/1648 YES YES H8SX/1648G YES YES H8SX/1648H YES YES H8SX/1663 YES YES H8SX/1664 YES YES H8SX/1668 YES YES H8SX/1668M YES YES H8SX/1668R YES YES H8SX/1725 YES YES H8SX/1725S YES YES ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR H8S and H8/300H Monitor 22

23 Compilers Compilers H8_300H Language Compiler Company Option Comment C GNU-C Free Software COFF H8/300H Foundation, Inc. C IARH8 IAR Systems AB UBROF H8/300H C CH38 Renesas Technology, SYSROF H8/300H Corp. C++ GNU-C++ Free Software Foundation, Inc. COFF H8/300H Compilers H8S Language Compiler Company Option Comment C ICCH8 IAR Systems AB UBROF H8S C CH38 Renesas Technology, SYSROF H8S Corp. C++ GNU Free Software COFF Foundation, Inc. C++ CH38 Renesas Technology, Corp. SYSROF Target Operating Systems Company Product Comment CMX Systems Inc. CMX-RTX CMX Systems Inc. CMX-TINY freertos FreeRTOS v7 Mentor Graphics Nucleus Corporation Vector oscan via ORTI - OSEK via ORTI Elektrobit Automotive ProOSEK via ORTI GmbH Quadros Systems Inc. RTXC 3.2 H8S and H8/300H Monitor 23

24 3rd Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows TA INSPECTOR Timing Architects GmbH Windows UNDODB Undo Software Linux VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE COVERAGE Vector Software Windows H8S and H8/300H Monitor 24

25 Products Product Information OrderNo Code LA-7528 MON-H8 LA-7528D MON-H8-SER-UD Text ROM Monitor for H8/300H and H8S family on ESI supports H8/300H and H8S includes HLL debugger, operation system, includes software for Windows ROM Monitor for H8/300H or H8S Serial Acc. UD supports H8S includes HLL debugger, operation system, licensed for one host system via USB dongle for Windows32, Windows64, Linux32, Linux64 and MAC OS X Order Information Order No. Code Text LA-7528 MON-H8 ROM Monitor for H8/300H and H8S family on ESI LA-7528D MON-H8-SER-UD ROM Monitor for H8/300H or H8S Serial Acc. UD H8S and H8/300H Monitor 25