ICE Emulator for 68000

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1 ICE Emulator for TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICE In-Circuit Emulator... ICE Target Guides... ICE Emulator for Warning... 3 Quick Start... 4 Troubleshooting... 5 Hang-Up 5 Dual-Port Errors 6 Configuration... 7 General Settings and Restrictions... 9 Restrictions 9 SYStem.Clock Clock generation 10 SYStem.Mode Select emulation modes 10 SYStem.Line CPU signals 11 SYStem.RESetOut RESET peripherals 11 SYStem.Option V33 Voltage sense 11 Memory Classes State Analyzer Keywords for the Trigger Unit 13 Keywords for the Display 15 Dequeueing 15 Emulation Frequency Support Compilers 17 3rd Party Tool Integration 18 Realtime Operation Systems 19 ICE Emulator for

2 ICE Emulator for Version 22-Mar-2018 SP:0017BE \\MCC\mcc\sieve MIX EI E:w.d.l addr/line code label mnemonic comment 571 flags[ k ] = FALSE; SP:0017BE 4212 clr.b (a2) 572 k += prime; SP:0017C0 D5C4 adda.l d4,a2 ; prime,a2 SP:0017C2 D684 add.l d4,d3 ; prime,k SP:0017C moveq #12,d0 ; #18,d0 SP:0017C6 B083 cmp.l d3,d0 ; k,d0 SP:0017C8 6CF4 bge $17BE E::w.v.chain %r %m ast ast.left E::w.v.ref 0x0 (0) (word = 0x0 NULL, flags = (1, 1, 1, 1, 1 count = 12346, k = 3 left = 0x5200 (word = 0x0, count = 12, prime = 3 right = 0x5600 (word = 0x0, count = 0, i = 0 field1 = 1, count = 0 field2 = 2), vint = 1 0x1 (1) (word = 0x0 NULL, count = 12, left = 0x5756 (word = 0x0, count = 34, right = 0x5680 (word = 0x0, count = 0, NOTE: This description is for the ONLY probe. This probe has been replaced by the new base module. For general informations about the In-Circuit Debugger refer to the ICE User s Guide (ice_user.pdf). All general commands are described in IDE Reference Guide (ide_ref.pdf) and General Commands and Functions. ICE Emulator for

3 Warning NOTE: Do not connect or remove probe from target while target power is ON. Power up: Switch on emulator first, then target Power down: Switch off target first, then emulator ICE Emulator for

4 Quick Start tbd. ICE Emulator for

5 Troubleshooting Hang-Up If you are not able to stop the emulation, there may be some typically reasons: Double Address Error No DTACK Signal Clock Error Interrupt Request Analyzer Function After a double address error the CPU is in halt state, use the SYStem.Up command to start again. Double address errors normally occur when the stack pointer is out of memory. If not TIMOUT is specified, the CPU cycle is not completed if the DTACK signal fails. On memory display windows BERR signals are not accepted. You can verify this state by checking the CYCLE signal with the counter function. If low, the CPU is stopped in the middle of the cycle. If request mode is selected, a dual-port error occurs and the emulator system changes to reset state. The clock line to the emulator is very critical. Check the driver and the clock on the emulation head. The device in the emulator is specified for 8 to 16.7 MHz. If running below 8 MHz calculation errors in the CPU may occur. Change the device in the emulator in this case. If all IPL signals are active low at the same time (NMI request) you can not use an asynchronous break. This interrupt level in usually used for fatal errors in target systems only. If only program breakpoints are used, no restriction in using interrupt level 7 is known. If you switch off the analyzer and the CPU has stopped operation, an invalid display occurs. Make a SYStem.Up command to see the true trace information. ICE Emulator for

6 Dual-Port Errors To realize the dual-port access (emulation memory) the BR-line of the CPU is used. Dual-port accesses are allowed only while no external request to the bus occurs and the CPU cycle is completed. If the emulation CPU is in RESET state of the CPU the system controller may always access the emulation memory. Dual-port errors may occur by the following conditions: 1. The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is generated. 2. External DMA requests (single cycles) are too long. To solve problems with dualport error first increase the SYStem.TimeReq value. Be sure that the SYStem.TimeOut value is bigger than the access time limit. If it is not possible to solve the problem by changing the values, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The internal dual-port access can increase the reaction time for external DMA requests. The performance reduction by the dual-port access is typically 1% with some data windows (dualported) on the screen and may be at max. 5% when using dynamic emulation memory. ICE Emulator for

7 Configuration The configuration between and is done by changing the CPU and the DIP-switches in the emulation head. To change to the cable must be changed also. Switch position ON = (+) OFF = (-) Switch position M MHz M Switch position M MHz M ICE Emulator for

8 Switch position M MHz M ICE Emulator for

9 General Settings and Restrictions Restrictions Memory Set-up All type in-circuit-emulators need memory in the supervisor stack area (SSP) to break correctly. If you get an invalid pc value after stopping the program, the SSP register may be outside the memory area. Register Set-up The SR register trace flag must not be set to 1. Emulation Frequency The probe uses a 16 MHz CPU device. The device is specified for 8 to 16.7 MHz. If running below 8 MHz calculation errors in the CPU may occur. Change the device in the emulator in this case. ICE Emulator for

10 SYStem.Clock Clock generation Format: SYStem.Clock <option> <option>: VCO High Mid Low VCO Low, Mid, High Variable frequency 1 35 MHz. 2.5, 5.0 or 10.0 MHz. SYStem.Mode Select emulation modes Format: SYStem.Mode <mode> <mode>: ResetDown ResetUp AloneInt AloneExt EmulInt EmulExt Reset Down Reset Up Alone Internal Alone External Target is down, all drivers are in tristate mode. Target has power, drivers are logically in inactive state, but not tristate. Probe is running with internal clock, driver inactive. This mode is used for 'standalone' operation. Probe is running with external clock, driver inactive. Emulation Internal Emulation External Probe is running with internal clock, strobes to target are generated. Probe is running with external clock, strobes to target are activated. In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor. ICE Emulator for

11 SYStem.Line CPU signals Format: SYStem.Line <option> <option>: FCode <class> BusReq [ON OFF] If no real-time emulation occurs then the CPU's status lines and the strobe lines must contain certain values in order that no memory accesses are triggered (inactive). However, depending upon the target system used, certain exceptions to this rule may become necessary. FCode BusReq CPU status lines are inactive. Default setting for this status is the same as for memory-read in user mode (USERDATA READ). Under normal conditions DMA accesses are only permitted if the emulator is executing a real-time program. If constant DMA is required then this function must be set. sys.s br on ; Set DMA function SYStem.RESetOut RESET peripherals Format: SYStem.RESetOut This function triggers the CPU RESET command which, in turn, initializes the peripherals. sys.resetout ; Initialize peripherals SYStem.Option V33 Voltage sense Format: SYStemOption V33 [ON OFF] The threshold level for the power-down sense is reduced to 2.8 V for operation with 3.3 V targets. ICE Emulator for

12 Memory Classes Memory Class Description FC0 Function-Code 0 FC1 UD FC2 UP USER-DATA USER-DATA USER-PROGRAM USER-PROGRAM FC3 Function-Code 3 FC4 Function-Code 4 FC5 SD FC6 SP SUPERVISOR-DATA SUPERVISOR-DATA SUPERVISOR-PROGRAM SUPERVISOR-PROGRAM FC7 Function-Code 7 CPU U S D P C E A USR CPU Function-Code User Supervisor Data Program Memory access by CPU Emulation memory access Absolute (physical) memory access User defined memory access (monitor extension) ICE Emulator for

13 State Analyzer Keywords for the Trigger Unit DMACycle DMA cycle Read CPU read cycle TimeOut DTACK Timeout (not HA120) Write CPU write cycle Wait0 Wait6 Waitstates WaitX Waitstates greater 6 CPU - FC7 Interrupt acknowledge FC0 FC7 Function code 0 to 7 IPL0 IPL2 Interrupt priority level lines SupervisorData Supervisor data area (FC5) SupervisorProgram Supervisor program area (FC6) UserData User data area (FC1) UserProgram User program area (FC2) VMA VMA cycle AutoVECtor FC7 * R * VMA Data UD + SD IACK FC7 * R IR IPL0 + IPL1 + IPL2 IR1 IR6 Interrupt request 1 to 6 IR7 - NMI Interrupt request 7, or NMI Program SP + UP ReadData R * D Supervisor SP + SD User UP + UD WriteData W * D BYTE Byte transfer WORD Word transfer LDS Lower data strobe UDS Upper data strobe ICE Emulator for

14 For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit Programming Guide (analyzer_prog.pdf). ICE Emulator for

15 Keywords for the Display WR Write line LDS Lower Data Strobe UDS Upper Data Strobe DMA DMA cycle between this and last record VMA VMA cycle IR Interrupt request level IPL.0 Interrupt request line 0 IPL.1 Interrupt request line 1 IPL.2 Interrupt request line 2 BR Bus request BG Bus grant BGACK Bus grant acknowledge BERR Bus access error VPA VPA cycle HALT Halt cycle RES Reset cycle Wait Number of inserted wait cycles, for more than 6 a 'X' appears. Dequeueing The disassembled lines in the analyzer are displayed prior to the resulting data cycles. This dequeueing fails for commands which have not a constant number of data cycles. Problems with Prefetches: short forward conditional branches to addresses already prefetched ICE Emulator for

16 Emulation Frequency The emulation probe is designed to run with CPU's up to 16.6 MHz. ICE Emulator for

17 Support Compilers Language Compiler Company Option Comment ADA ALSYS-ADA IEEE limited support (IEEE) ADA TELESOFT-ADA Telesoft IEEE limited support (IEEE) ASM RTOS IEP GmbH SYM/LOC Source level debugging ASM ASM68K Mentor Graphics Corporation IEEE Source level debugging ASM VERSADOS-ASM NXP Semiconductors VERSADOS symbols only ASM OS-9-ASSEMBLER Radisys Inc. ROF Source level debugging ASM AS68 TASKING IEEE C HP C HP no type/locals info C ORGANON CAD-UL BOUND ElectronicServices GmbH C C68K Cosmic Software COSMIC C GNU-C Free Software ELF/DWARF Foundation, Inc. C GNU-C Free Software COFF Foundation, Inc. C GNU-C Free Software Foundation, Inc. ELF/DWARF C GREEN-HILLS-C Greenhills Software Inc. COFF C ICC68K Introl Corporation ICOFF C MCC Mentor Graphics IEEE Corporation C HT-68K Microchip Technology HITECH Inc. C HICROSS-68K NXP Semiconductors HICROSS C CC68K NXP Semiconductors COFF C ULTRA-C Radisys Inc. ROF OS/9 compilers C OS/9-C Radisys Inc. ROF C CROSSCODE-C SDSI SDS C SCC68K Sierra COFF C SUN3-CC Oracle Corporation DBX C ICC68K TASKING COFF C ICC68K TASKING IEEE C TT-68K TASKING IEEE ICE Emulator for

18 Language Compiler Company Option Comment C TCC68K TASKING AOUT only source and syms C TEKTRONIX-C Tektronix COMFOR C D-CC Wind River Systems IEEE C D-CC Wind River Systems ELF/DWARF C++ ORGANON-C++ CAD-UL BOUND ElectronicServices GmbH C++ GNU-C++ Free Software DBX Foundation, Inc. C++ GNU-C++ Free Software ELF/DWARF Foundation, Inc. C++ CCC68K Mentor Graphics IEEE Corporation C++ HICROSS-68K NXP Semiconductors HICROSS C++ CODEWARRIOR NXP Semiconductors ELF/DWARF C++ CROSSCODE-C++ SDSI SDS C++ D-C++ Wind River Systems ELF/DWARF MODULA MOD68K Introl Corporation ICOFF MODULA MCS2 Multichannelsystems COFF GmbH MODULA MCDS NXP Semiconductors MCDS PASCAL MPC Mentor Graphics IEEE Corporation PEARL RTOS IEP GmbH SYM/LOC no type/locals info 3rd Party Tool Integration CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ICE Emulator for

19 CPU Tool Company Host ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows ECU-TEST TraceTronic GmbH Windows UNDODB Undo Software Linux TA INSPECTOR Vector Windows VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE Vector Software Windows COVERAGE 68K OS68 DEBUGGER Enea OSE Systems - 68K SDT CMICRO IBM Corp. Windows 68K DIAB RTA SUITE Wind River Systems Windows Realtime Operation Systems Company Product Comment Atego Ldt. AdaWorld ARTK KadakProducts Ltd. AMX Oracle Corporation ChorusOS CMX Systems Inc. CMX-RTX Synopsys, Inc MQX 2.40 and 2.50, 3.6 MTOS-UX Mentor Graphics Nucleus PLUS Corporation Radisys Inc. OS-9 Enea OSE Systems OSE Classic (OS68) ICE Emulator for

20 Company Product Comment Enea OSE Systems OSE Delta 4.x and 5.x RealTime Craft (XEC68k) Quadros Systems Inc. RTXC 3.2 IBM Corp. SDT-Cmicro - uclinux Kernel Version 2.4 and 2.6, 3.x Mentor Graphics VRTX32 Corporation Mentor Graphics VRTXmc Corporation Mentor Graphics VRTXsa Corporation Wind River Systems VxWorks 5.x and 6.x ICE Emulator for

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Simulator for Z80+ TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for Z80+... 1 TRACE32 Simulator License... 3 Quick Start of the