Simulator for PowerPC

Transcription

1 Simulator for PowerPC TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for PowerPC... 1 TRACE32 Simulator License... 4 Quick Start of the Simulator... 5 Peripheral Simulation... 7 Troubleshooting... 7 FAQ... 7 Memory Classes... 8 General SYStem Commands... 9 SYStem.CPU Select CPU type 9 SYStem.CpuAccess Run-time memory access (intrusive) 9 SYStem.MemAccess Real-time memory access (non-intrusive) 10 SYStem.Mode Establish the communication with the simulator 10 SYStem.Option DisMode Simulator operation mode 11 SYStem.Option DUALPORT Run-time memory access for all windows 11 SYStem.Option IMASKASM Disable interrupts while single stepping 12 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 12 SYStem.Option MMUSPACES Enable space IDs 12 SYStem.Option.NOTRAP Use alternative software breakpoint instruction 13 SYStem.Option OVERLAY Enable overlay support 14 CPU specific MMU Commands MMU.DUMP Page wise display of MMU translation table 15 MMU.List Compact display of MMU translation table 16 MMU.SCAN Load MMU table from CPU 17 Support Available Tools 19 Compilers 19 Target Operating Systems 21 3rd Party Tool Integrations 22 Products Product Information 23 Simulator for PowerPC 1

2 Order Information 23 Simulator for PowerPC 2

3 Simulator for PowerPC Version 06-Nov-2017 All general commands are described in the IDE Reference Guide (ide_ref.pdf) and General Commands Reference. Simulator for PowerPC 3

4 TRACE32 Simulator License [build DVD 02/2016] The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License. For more information, see Simulator for PowerPC 4

5 Quick Start of the Simulator To start the simulator, proceed as follows: 1. Select the device prompt for the ICD Debugger and reset the system. B:: RESet The device prompt B:: is normally already selected in the command line. If this is not the case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start directly after booting TRACE Specify the CPU specific settings. SYStem.CPU <cpu_name> The default values of all other options are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target. Simulator for PowerPC 5

6 3. Enter debug mode. SYStem.Up This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers. 4. Load the program. Data.LOAD.format <filename> ; load program and symbols The format of the Data.LOAD command depends on the file format generated by the compiler. Refer to Supported Compilers to find the command that is necessary for your compiler. A detailed description of the Data.LOAD command and all available options is given in the reference guide. 5. Start-up example A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII file format) and executed with the command DO <filename>. B:: WinCLEAR SYStem.CPU <cpu_name> SYStem.Up Data.LOAD.format <filename> Register.Set pc main PER.view ; Select the ICD device prompt ; Clear all windows ; Select CPU type ; Reset the target and enter ; debug mode ; Load the application ; Set the PC to function main ; Show clearly arranged peripherals ; in window *) Data.List ; Open source code window *) Register /SpotLight ; Open register window *) Frame.view /Locals /Caller Var.Watch %Spotlight flags ast ; Open the stack frame with ; local variables *) ; Open watch window for ; variables *) *) These commands open windows on the screen. The window position can be specified with the WinPOS command. Simulator for PowerPC 6

7 Peripheral Simulation For more information, see API for TRACE32 Instruction Set Simulator (simulator_api.pdf). Troubleshooting No information available FAQ No information available Simulator for PowerPC 7

8 Memory Classes The following memory classes are available: Memory Class P D SPR DCR PMR IC DC NC Description Program Data Special Purpose Register Device Control Register Performance Control Register Instruction Cache Data Cache No Cache (only physically memory) If the cache is disabled, memory accesses to the memory classes IC or DC are realized by TRACE32-ICD as reads and writes to physical memory. Simulator for PowerPC 8

9 General SYStem Commands SYStem.CPU Select CPU type SYStem.CPU <cpu> <cpu>: SYStem.CpuAccess Run-time memory access (intrusive) SYStem.CpuAccess Enable Denied Nonstop Default: Denied. Enable Denied Nonstop Allow intrusive run-time memory access. Since a non-intrusive run-time memory access (SYStem.MemoryAccess CPU) is available for all TRACE32 instruction set simulators, there is no need for an intrusive run-time memory access. Lock intrusive run-time memory access. Lock all features of the debugger that affect the run-time behavior. Nonstop reduces the functionality of the debugger to: run-time access to memory and variables trace display The debugger inhibits the following: to stop the program execution all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.) Simulator for PowerPC 9

10 SYStem.MemAccess Real-time memory access (non-intrusive). SYStem.MemAccess CPU Denied <cpu_specific> SYStem.ACCESS (deprecated) CPU Denied (default) Real-time memory access during program execution to target is enabled. Real-time memory access during program execution to target is disabled. SYStem.Mode Establish the communication with the simulator SYStem.Mode <mode> <mode>: Down NoDebug Go Up Default: Down. Selects the target operating mode. Down NoDebug Go Up The CPU is in reset. Debug mode is not active. Default state and state after fatal errors. The CPU is running. Debug mode is not active. Debug port is tristate. In this mode the target should behave as if the debugger is not connected. The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs. The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging. If the mode Go is selected, this mode will be entered, but the control button in the SYStem.state window jumps to the mode Up. Simulator for PowerPC 10

11 SYStem.Option DisMode Simulator operation mode SYStem.Option DisMode <mode> <mode>: ACCESS AUTO FLE VLE MPC5XXX/SPC5XX only. This command sets the operation mode for the simulator. AUTO (default) ACCESS FLE VLE Behavior depending on CPU selection. VLE/FLE operation for VLE/FLE-only processors, others: see ACCESS Default: Standard PowerPC (FLE) instruction set. Simulator supports mixed FLE/VLE code execution if MMU simulation is enabled. Simulator is configured to execute code compiled for the standard PowerPC instruction set (fixed length encoding). Simulator is configured to execute code compiled for VLE (variable length encoding). SYStem.Option DUALPORT Run-time memory access for all windows SYStem.Option DUALPORT [ON OFF] Default: OFF. Dualport access of memory while simulation in running. Simulator for PowerPC 11

12 SYStem.Option IMASKASM Disable interrupts while single stepping SYStem.Option IMASKASM [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. SYStem.Option IMASKHLL Disable interrupts while HLL single stepping SYStem.Option IMASKHLL [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. NOTE: Do not enable this option for code that disables MSR_EE. The debugger will disable MSR_EE while the CPU is running and restore it after the CPU stopped. If a part of the application is executed that disables MSE_EE, the debugger cannot detect this change and will restore MSE_EE. SYStem.Option MMUSPACES Enable space IDs SYStem.Option MMUSPACES [ON OFF] SYStem.Option MMUspaces [ON OFF] (deprecated) SYStem.Option MMU [ON OFF] (deprecated) Default: OFF. Enables the use of space IDs for logical addresses to support multiple address spaces. A space ID is a 16- bit memory space identifier which extends a logical TRACE32 address. With space IDs, TRACE32 can handle multiple address spaces in the debugger address translation. Simulator for PowerPC 12

13 Space IDs are defined within a loaded TRACE32 OS awareness extension. Often, space IDs are directly derived from the OS process ID. Be aware that this depends on the OS and the loaded awareness extension. NOTE: SYStem.Option MMUSPACES should not be used if only one translation table is used on the target. If a debug session requires space IDs, you must observe the following sequence of steps: 1. Activate SYStem.Option MMUSPACES. 2. Load the symbols with Data.LOAD. Otherwise, the internal symbol database of TRACE32 may become inconsistent. Examples: ;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x012A: Data.dump D:0x012A:0xC00208A ;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x0203: Data.dump D:0x0203:0xC00208A SYStem.Option.NOTRAP Use alternative software breakpoint instruction SYStem.Option NOTRAP <type> <type>: ON OFF FPU ILL Defines which instruction is used to implement software breakpoints. OFF ON ILL FPU Use TRAP instructions as software breakpoint (default setting). Using illegal opcode as breakpoint instruction, TRAP instruction available for use in application. Not supported in simulator. Same effect as ON. Simulator for PowerPC 13

14 SYStem.Option OVERLAY Enable overlay support SYStem.Option OVERLAY [ON OFF WithOVS] Default: OFF. ON OFF WithOVS Activates the overlay extension and extends the address scheme of the debugger with a 16 bit virtual overlay ID. Addresses therefore have the format <overlay_id>:<address>. This enables the debugger to handle overlaid program memory. Disables support for code overlays. Like option ON, but also enables support for software breakpoints. This means that TRACE32 writes software breakpoint opcodes both to the execution area (for active overlays) and to the storage area. In this way, it is possible to set breakpoints into inactive overlays. Upon activation of the overlay, the target s runtime mechanisms copies the breakpoint opcodes to the execution area. For using this option, the storage area must be readable and writable for the debugger. SYStem.Option OVERLAY ON Data.List 0x2:0x11c4 ; Data.List <overlay_id>:<address> Simulator for PowerPC 14

15 CPU specific MMU Commands MMU.DUMP Page wise display of MMU translation table MMU.DUMP <table> [<range> <addr> <range> <root> <addr> <root>] MMU.<table>.dump (deprecated) <table>: PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> <cpu_specific_tables> Displays the contents of the CPU specific MMU translation table. If called without parameters, the complete table will be displayed. If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter. The optional <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory. PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> Display the current MMU translation table entries of the CPU. This command reads all tables the CPU currently uses for MMU translation and displays the table entries. Display the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and displays its table entries. Display the MMU translation table entries of the given process. In MMU based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and displays its table entries. See also the appropriate OS awareness manuals: RTOS Debugger for <x>. For information about the parameters, see What to know about Magic Numbers, Task IDs and Task Names (general_ref_t.pdf). CPU specific tables: ITLB DTLB Displays the contents of the Instruction Translation Lookaside Buffer. Displays the contents of the Data Translation Lookaside Buffer. Simulator for PowerPC 15

16 TLB Displays the contents of the Translation Lookaside Buffer. TLB0 Displays the contents of the Translation Lookaside Buffer 0. TLB1 Displays the contents of the Translation Lookaside Buffer 1. TLB2 Displays the contents of the Translation Lookaside Buffer 2. BAT PTE Displays the contents of the BAT table. Displays the contents of the PTE table. MMU.List Compact display of MMU translation table MMU.List <table> [<range> <addr> <range> <root> <addr> <root>] MMU.<table>.List (deprecated) <table>: PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> <space_id>:0x0 Lists the address translation of the CPU-specific MMU table. If called without address or range parameters, the complete table will be displayed. If called without a table specifier, this command shows the debugger-internal translation table. See TRANSlation.List. If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter. <root> PageTable The optional <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory. List the current MMU translation of the CPU. This command reads all tables the CPU currently uses for MMU translation and lists the address translation. Simulator for PowerPC 16

17 KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> List the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and lists its address translation. List the MMU translation of the given process. In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and lists its address translation. See also the appropriate OS awareness manuals: RTOS Debugger for <x>. For information about the parameters, see What to know about Magic Numbers, Task IDs and Task Names (general_ref_t.pdf). MMU.SCAN Load MMU table from CPU MMU.SCAN <table> [<range> <address>] MMU.<table>.SCAN (deprecated) <table>: PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> ALL <cpu_specific_tables> Loads the CPU-specific MMU translation table from the CPU to the debugger-internal translation table. If called without parameters, the complete page table will be loaded. The loaded address translation can be viewed with TRANSlation.List. If the command is called with either an address range or an explicit address, page table entries will only be loaded if their logical address matches with the given parameter. Simulator for PowerPC 17

18 PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> ALL Load the current MMU address translation of the CPU. This command reads all tables the CPU currently uses for MMU translation, and copies the address translation into the debugger-internal translation table. Load the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the table of the kernel and copies its address translation into the debugger-internal translation table. Load the MMU address translation of the given process. In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and copies its address translation into the debugger-internal translation table. See also the appropriate OS awareness manual: RTOS Debugger for <x>. For information about the parameters, see What to know about Magic Numbers, Task IDs and Task Names (general_ref_t.pdf). Load all known MMU address translations. This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debuggerinternal translation table. See also the appropriate OS awareness manual: RTOS Debugger for <x>. CPU specific tables: TLB1 Loads the translation table 1from the CPU to the debugger internal translation table. Simulator for PowerPC 18

19 Support Available Tools CPU ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR MPC5200 YES YES YES MPC5200B YES YES YES Compilers Language Compiler Company Option Comment ADA GNAT PRO AdaCore ELF/DWARF not all ADA constructs/dwarf ADA GNAT Free Software ELF/DWARF Foundation, Inc. C CXPPC Cosmic Software ELF/DWARF C XCC-V GAIO Technology Co., Ltd. SAUF C GREEN-HILLS-C Greenhills Software Inc. ELF/DWARF C MCCPPC Mentor Graphics ELF/DWARF Corporation C CC NXP Semiconductors XCOFF C ULTRA-C Radisys Inc. ROF C HIGH-C Synopsys, Inc ELF/DWARF C DCPPC TASKING ELF/DWARF C D-CC Wind River Systems IEEE C D-CC Wind River Systems COFF C D-CC Wind River Systems ELF/DWARF C++ GCC Free Software Foundation, Inc. ELF/DWARF C++ GREEN-HILLS- C++ Greenhills Software Inc. ELF/DWARF C++ CCCPPC Mentor Graphics Corporation ELF/DWARF Simulator for PowerPC 19

20 Language Compiler Company Option Comment C++ MSVC Microsoft Corporation EXE/CV5 WindowsCE C++ HIGH-C++ Synopsys, Inc ELF/DWARF C++ D-C++ Wind River Systems ELF/DWARF C++ GCCPPC Wind River Systems ELF/STABS C/C++ GNAT PRO AdaCore ELF/DWARF C/C++ GCC HighTec EDV-Systeme ELF/DWARF GmbH C/C++ CODEWARRIOR NXP Semiconductors ELF/DWARF GCC GCC Free Software ELF/DWARF Foundation, Inc. JAVA FASTJ Wind River Systems ELF/DWARF Simulator for PowerPC 20

21 Target Operating Systems Company Product Comment KadakProducts Ltd. AMX Oracle Corporation ChorusOS CMX Systems Inc. CMX-RTX DDC-I, Inc. DEOS implemented by DDC-I ecoscentric Limited ECOS 1.3, 2.0 and 3.0 Elektrobit Automotive Elektrobit tresos via ORTI GmbH ETAS GmbH ERCOSEK via ORTI Evidence Erika via ORTI freertos FreeRTOS v7 HIPPEROS S.A. HIPPEROS implemented by HIPPEROS - Linux Kernel Version 2.4 and 2.6, 3.x, 4.x MontaVista Software, LLC Linux 3.0, 3.1, 4.0, 5.0 LynuxWorks Inc. LynxOS 3.1.0, 3.1.0a, 4.0 NXP Semiconductors MQX 3.x and 4.x Synopsys, Inc MQX 2.40 and NetBSD MISPO Co. Ltd. NORTi Mentor Graphics Nucleus PLUS Corporation Radisys Inc. OS-9 Enea OSE Systems OSE Delta 4.x and 5.x - OSEK via ORTI NXP Semiconductors OSEKturbo via ORTI/former MetrowerksOSEK Sysgo AG PikeOS Elektrobit Automotive ProOSEK via ORTI GmbH Wind River Systems psos+ 2.1 to 2.5, 3.0, with TRACE32 QNX Software Systems QNX 6.0 to RTEMS RTEMS up to 4.12 Quadros Systems Inc. RTXC 3.2 Quadros Systems Inc. RTXC Quadros Sciopta Sciopta Micro Digital Inc. SMX 3.4 to 4.0 Express Logic Inc. ThreadX 3.0, 4.0, 5.0 Micrium Inc. uc/os-ii 2.0 to uitron HI7000, RX4000, NORTi,PrKernel Mentor Graphics VRTXsa Corporation Wind River Systems VxWorks 5.x to 7.x Simulator for PowerPC 21

22 3rd Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows TA INSPECTOR Timing Architects GmbH Windows UNDODB Undo Software Linux VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE Vector Software Windows COVERAGE POWERPC OSE ILLUMINATOR Enea OSE Systems Windows POWERPC DIAB RTA SUITE Wind River Systems Windows Simulator for PowerPC 22

23 Products Product Information OrderNo Code LA-2801L SIMULATOR-PPC-FL Text 1 User Float. Lic. TRACE32 PPC Simulator Floating license to use the TRACE32 Instruction Set Simulator for automated tests via script language PRACTICE or via the TRACE32 Remote API supports PowerPCs for Windows32, Windows64, Linux32, Linux64 and Solaris, other platforms on request floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ) Order Information Order No. Code Text LA-2801L SIMULATOR-PPC-FL 1 User Float. Lic. TRACE32 PPC Simulator Simulator for PowerPC 23