PIC18FXX2 Registers. Hyperlinked Index

Transcription

1 PIC18FXX2 Registers This document provides a concise summary of the names and bit definitions for the PIC18FXX2 Special Function Registers, Configuration Registers and Device ID Registers. Hyperlinked Index Notation 2 Page Special Function Registers Special Function Register Names 3 Core SFRs Bit Names 4 Peripheral SFRs Bit Names 5 CPU Related 6 WREG (Accumulator), STATUS (Flags) Program Counter 6 PCLATU, PCLATH, PCL Hardware Multiplier 7 PRODH, PRODL Stack Access 7 TOSU, TOSH, TOSL, STKPTR Table Pointer 8 TBLPTRU, TBLPTRH, TBLPTRL, TABLAT Interrupt System 9 INTCON, INTCON2, INTCON3, PIR1, PIR2, PIE1, PIE2, IPR1, IPR2 Bank Select Register for Banked (Direct) Addressing 16 BSR File Select Registers for Indirect Addressing 16 INDF0, POSTINC0, POSTDEC0, PREINC0, PLUSW0, FSR0H, FSR0L, INDF1, POSTINC1, POSTDEC1, PREINC1, PLUSW1, FSR1H, FSR1L, INDF2, POSTINC2, POSTDEC2, PREINC2, PLUSW2, FSR2H, FSR2L Timers 19 Timer0: TMR0H, TMR0L, T0CON 19 Timer1: TMR1H, TMR1L, T1CON 20 Timer2: TMR2, PR2, T2CON 21 Timer3: TMR3H, TMR3L, T3CON 22 Miscellaneous Control/Status Registers 23 OSCCON, LVDCON, WDTCON, RCON Master Synchronous Serial Port (MSSP) 25 SSPBUF, SSPADD, SSPSTAT (SPI mode), SSPCON (SPI mode), SSPSTAT (I 2 C mode), SSPCON (I 2 C mode) Analog to Digital Converter 30 ADRESH, ADRESL, ADCON0, ADCON1 Capture/Compare/PWM (CCP) Modules 32 CCP1: CCP1H, CCP1L, CCP1CON 32 CCP2: CCP2H, CCP2L, CCP2CON 33 USART Module 34 SPBRG, RCREG, TXREG, TXSTA, RCSTA EEPROM 36 EEADR, EEDATA, EECON1, EECON2 I/O Ports 38 PortA: PORTA, LATA, TRISA 38 PortB: PORTB, LATB, TRISB 39 PortC: PORTC, LATC, TRISC 41 PortD: PORTD, LATD, TRISD 42 PortE: PORTE, LATE, TRISE 43 Configuration, Device Revision and Device ID Registers Configuration Register Summary 45 CONFIG0H: Clock Configuration 45 CONFIG2L: Brown-out Detect and Power-on Reset 45 CONFIG2H: Watchdog Timer 46 CONFIG3H: CCP2 Multiplex 46 CONFIG5L: Code Protection Bits 46 CONFIG5H: EEPROM and Boot Block Code Protection Bits 47 CONFIG6L: FLASH Write Protection Bits 47 CONFIG6H: EEPROM/Boot Block/Configuration Register Write Protect Bits 47 CONFIG7L: Table Read Protection Bits 48 CONFIG7H: Boot Block Table Read Protection Bit 48 DEVID1: Device Revision and ID Register 1 48 DEVID2: Device ID Register 2 48 File: PIC18F452 SFRs.doc Created: DCR, 06/03/ :12:00

2 Notation The COURIER font denotes literal names of registers or bits. These names are also defined in the Microchip assembler and compiler include files. Bit names are denoted by angle brackets < > for example, T0CON<TMR0ON> is the Timer0 On bit TMR0ON of the Timer0 Control special function register T0CON. A range of registers or bits is denoted by a colon : for example, SSPCON1<SSPM3:SSPM0> are the 4 Synchronous Serial Port Mode bits SSPM3, SSPM2, SSPM1, SSPM0 of the Synchronous Serial Port Control1 special function register SSPCON1. A bit function that is asserted low (negative logic) is denoted by a hash mark #. For example, D/#A is the Data/notAddress bit of the SSPSTAT register. This is normally written using an overbar: D/A in datasheets. Readable/Writable Special function register bits may be Readable and/or Writable: R: Readable bit U-0: Unimplemented bit always reads as 0 W: Writable bit Reset Status Values are given below for each register following a Power-On (PO) or Brown-Out (BO) Reset, or a Master Clear (MCLR). Codes used are: 0: bit is cleared 1: bit is set q: bit value depends on condition. u: bit value is unchanged by the reset. x: bit value is unknown it could be either 0 or 1 Configuration Bits Configuration register bits may be Readable and/or Programmable. Codes used are: C: bit resets to 1, but can subsequently be cleared R: readable P: programmable U: unimplemented bit, read as 0 -n: value when device is un-programmed u: unchanged from programmed state Page numbers refer to the Microchip PIC18FXX2 Data Sheet 2002, document DS39564B. Shaded areas are not implemented, or not relevant to the particular mode. Special Function Registers This section summarises the PIC18FXX2 special function registers, arranged in approximate numerical order of address, from 0xFFF to 0xF80, but modified to group the SFRs by their primary function. 2 of 48

3 Table 1: PIC18F2XX Special Function Register Names Address Name Address Name Address Name Address Name 0xFFF TOSU 0xFDF INDF2 (3) 0xFBF CCPR1H 0xF9F IPR1 0xFFE TOSH 0xFDE POSTINC2 (3) 0xFBE CCPR1L 0xF9E PIR1 0xFFD TOSL 0xFDD POSTDEC2 (3) 0xFBD CCP1CON 0xF9D PIE1 0xFFC STKPTR 0xFDC PREINC2 (3) 0xFBC CCPR2H 0xF9C 0xFFB PCLATU 0xFDB PLUSW2 (3) 0xFBB CCPR2L 0xF9B 0xFFA PCLATH 0xFDA FSR2H 0xFBA CCP2CON 0xF9A 0xFF9 PCL 0xFD9 FSR2L 0xFB9 0xF99 0xFF8 TBLPTRU 0xFD8 STATUS 0xFB8 0xF98 0xFF7 TBLPTRH 0xFD7 TMR0H 0xFB7 0xF97 0xFF6 TBLPTRL 0xFD6 TMR0L 0xFB6 0xF96 TRISE (2) 0xFF5 TABLAT 0xFD5 T0CON 0xFB5 0xF95 TRISD (2) 0xFF4 PRODH 0xFD4 0xFB4 0xF94 TRISC 0xFF3 PRODL 0xFD3 OSCCON 0xFB3 TMR3H 0xF93 TRISB 0xFF2 INTCON 0xFD2 LVDCON 0xFB2 TMR3L 0xF92 TRISA 0xFF1 INTCON2 0xFD1 WDTCON 0xFB1 T3CON 0xF91 0xFF0 INTCON3 0xFD0 RCON 0xFB0 0xF90 0xFEF INDF0 (3) 0xFCF TMR1H 0xFAF SPBRG 0xF8F 0xFEE POSTINC0 (3) 0xFCE TMR1L 0xFAE RCREG 0xF8E 0xFED POSTDEC0 (3) 0xFCD T1CON 0xFAD TXREG 0xF8D LATE (2) 0xFEC PREINC0 (3) 0xFCC TMR2 0xFAC TXSTA 0xF8C LATD (2) 0xFEB PLUSW0 (3) 0xFCB PR2 0xFAB RCSTA 0xF8B LATC 0xFEA FSR0H 0xFCA T2CON 0xFAA 0xF8A LATB 0xFE9 FSR0L 0xFC9 SSPBUF 0xFA9 EEADR 0xF89 LATA 0xFE8 WREG 0xFC8 SSPADD 0xFA8 EEDATA 0xF88 0xFE7 INDF1 (3) 0xFC7 SSPSTAT 0xFA7 EECON2 0xF87 0xFE6 POSTINC1 (3) 0xFC6 SSPCON1 0xFA6 EECON1 0xF86 0xFE5 POSTDEC1 (3) 0xFC5 SSPCON2 0xFA5 0xF85 0xFE4 PREINC1 (3) 0xFC4 ADRESH 0xFA4 0xF84 PORTE (2) 0xFE3 PLUSW1 (3) 0xFC3 ADRESL 0xFA3 0xF83 PORTD (2) 0xFE2 FSR1H 0xFC2 ADCON0 0xFA2 IPR2 0xF82 PORTC 0xFE1 FSR1L 0xFC1 ADCON1 0xFA1 PIR2 0xF81 PORTB 0xFE0 BSR 0xFC0 0xFA0 PIE2 0xF80 PORTA Notes 1: Unimplemented registers will always read as 0. 2: This register is not available on PIC18F2X2 devices. 3: This is not a physical register. 3 of 48

4 ` Table 2: Core Special Function Registers Related to CPU and Addressing File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TOSU Top-of-Stack upper Byte (TOS<20:16>) TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF Return Stack Pointer PCLATU Holding Register for PC<20:16> PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch PRODH Product Register High Byte xxxx xxxx 71 PRODL Product Register Low Byte xxxx xxxx 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF x 75 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP RBIP INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a 50 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a 50 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a 50 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a 50 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register). Offset by value in WREG. n/a 50 FSR0H Indirect Data Memory Address Pointer 0 High Byte FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 50 WREG Working Register xxxx xxxx n/a INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a 50 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a 50 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a 50 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a 50 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register). Offset by value in WREG. n/a 50 FSR1H Indirect Data Memory Address Pointer 1 High Byte FSR1L xxxx xxxx 50 BSR Bank Select Register INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a 50 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a 50 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a 50 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a 50 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register). Offset by value in WREG. n/a 50 FSR2H Indirect Data Memory Address Pointer 2 High Byte FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50 STATUS N OV Z DC C ---x xxxx 52 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Notes 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and will always read as '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. Details on page: 4 of 48

5 Table 3: Peripheral Special Function Registers Control Peripherals File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 of 48 Value on POR, BOR TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte xxxx xxxx 105 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS OSCCON SCS LVDCON IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL WDTCON SWDTE RCON IPEN R I TO PD POR BOR qq 53, 28, 84 TMR1H Timer1 Register High Byte xxxx xxxx 107 TMR1L Timer1 Register Low Byte xxxx xxxx 107 T1CON RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 Register PR2 Timer2 Period Register T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 125 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode SSPSTAT SMP CKE D/A P S R/W UA BF SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN ADRESH A/D Result Register High Byte xxxx xxxx 187,188 ADRESL A/D Result Register Low Byte xxxx xxxx 187,188 ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON ADCON1 ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 121, 123 CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 121, 123 CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 121, 123 CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 121, 123 CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M TMR3H Timer3 Register High Byte xxxx xxxx 113 TMR3L Timer3 Register Low Byte xxxx xxxx 113 T3CON RD16 CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON SPBRG USART1 Baud Rate Generator RCREG USART1 Receive Register , 178, 180 TXREG USART1 Transmit Register , 176, 179 TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D x 167 EEADR Data EEPROM Address Register , 69 EEDATA Data EEPROM Data Register EECON2 Data EEPROM Control Register 2 (not a physical register) , 69 EECON1 EEPGD CFGS FREE WRERR WREN WR RD xx-0 x IPR2 EEIP BCLIP LVDIP TMR3IP CCP2IP PIR2 EEIF BCLIF LVDIF TMR3IF CCP2IF PIE2 EEIE BCLIE LVDIE TMR3IE CCP2IE IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE TRISE (3) IBF OBF IBOV PSPMODE Data Direction bits for PORTE TRISD (3) Data Direction Control Register for PORTD TRISC Data Direction Control Register for PORTC TRISB Data Direction Control Register for PORTB TRISA TRISA6(1) Data Direction Control Register for PORTA LATE (3) Read PORTE Data Latch, Write PORTE Data Latch xxx 99 LATD (3) Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 95 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 93 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 90 LATA LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 87 PORTE (3) Read PORTE pins, Write PORTE Data Latch PORTD (3) Read PORTD pins, Write PORTD Data Latch xxxx xxxx 95 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 93 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 90 PORTA RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Notes 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear ( 0 ). Details on page:

6 CPU Related WREG: Working Register (Accumulator) 0xFE8 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The WREG bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u STATUS: Status (Flags) Register 0xFD8 p. 52 U-0 U-0 U-0 R/W R/W R/W R/W R/W Bit Names N OV Z DC C PO/BO Reset x x x x x MCLR Reset u u u u u bit 4 bit 3 bit 2 bit 1 bit 0 N: Negative bit. 1: Result was negative 0: Result was positive OV: Overflow bit. 1: Overflow of bit 7 occurred during signed arithmetic operation 0: No overflow occurred Z: Zero bit. 1: Result of operation was zero 0: Result of operation was not zero DC: Digit Carry bit. 1: Carry-out from the 4 th low order bit of result occurred 0: No carry from the 4 th low order bit of result occurred C: Carry bit. 1: Carry-out from the MSB of result occurred on addition (OR No borrow occurred on subtraction) 0: Carry from the MSB of result did not occur on addition (OR Borrow occurred on subtraction) Program Counter (PC) Register 21 bits PCLATU: Program Counter Latch Register, Upper Byte PCLATH: Program Counter Latch Register, High Byte PCL: Program Counter Register, Low Byte 0xFFB 0xFFA 0xFF9 p. 39 R/W R/W R/W Byte Names PCLATU PCLATH PCL 0xFFB 0xFFA 0Xff9 PO/BO Reset MCLR Reset The PC register is a 21-bit register that stores the address of the next program instruction to be fetched. 6 of 48

7 Hardware Multiplication Product of Multiplication Register 16 bits PRODH: Product of Multiplication Register, High Byte PRODL: Product of Multiplication Register, Low Byte 0xFF4 0xFF3 p. 71 R/W R/W Bit Names PRODH PRODL 0xFF4 0xFF3 PO/BO Reset xxxx xxxx xxxx xxxx MCLR Reset uuuu uuuu uuuu uuuu The PRODH:PRODL register is a 16-bit register that receives the result of an 8x8 hardware multiply. Stack Access Top Of Stack (TOS) Register 21 bits TOSU: Top Of Stack Upper Register (TOS<20:16>) TOSH: Top Of Stack Higher Register (TOS<15:8) TOSL: Top Of Stack Lower Register (TOS<7:0>) 0xFFF 0xFFE 0xFFD p. 37 R/W R/W R/W Byte Names TOSU TOSH TOSL 0xFFF 0xFFE 0xFFD PO/BO Reset MCLR Reset STKPTR: Return Stack Pointer Register 0xFFC p. 38 R/W R/W U-0 R/W R/W R/W R/W R/W Bit Names STKFUL STKUNF - STKPTR4 STKPTR3 STKPTR2 STKPTR1 STKPTR0 PO/BO Reset MCLR Reset bit 7 bit 6 STKFUL: Stack Full Flag bit. Note: Can only be cleared by user software or a POR. 1: Stack is full (31 entries) or has overflowed. 0: Stack has not become full or has overflowed. STKUNF: Stack Overflow Flag bit. Note: Can only be cleared by user software or a POR. 1: Stack underflow has occurred. 0: Stack has not underflowed. bit 5 Not implemented reads as 0. bit 4-0 STKPTR4:STKPTR0: Stack pointer value bits. This 5-bit field contains the hardware stack pointer value, between 0 and 31 inclusive. 7 of 48

8 Table Pointer Table Pointer (TBLPTR) Register 22 bits TBLPTRU: Table Pointer Register, Upper Byte TBLPTRH: Table Pointer Register, High Byte TBLPTRL: Table Pointer Register, Low Byte 0xFF8 0xFF7 0xFF6 p. 58 R/W R/W R/W Byte Names TBLPRTU TBLPRTH TBLPRTL 0xFF8 0xFFA7 0XFF6 PO/BO Reset MCLR Reset The TABLPTR register is a 22-bit register used to hold a (21-bit) program memory address during transfers between program memory and data RAM. Note: Set bit 21 to enable access to the device configuration bits. TABLAT: Table Latch Register 0xFF5 p. 58 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TABLAT bits are not individually named. PO/BO Reset MCLR Reset The TABLAT register is an 8-bit register used to hold data during transfers between program memory and data RAM. It is the ONLY register that is accessible from both Program Memory and Data Memory. 8 of 48

9 Interrupt System INTCON: Interrupt Control Register 0xFF2 p. 75 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names GIE / PEIE / TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF GIEH GIEL PO/BO Reset x MCLR Reset u bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 GIE/GIEH: Global Interrupt Enable bit. When RCON<IPEN> = 0: 1: Enables response to all unmasked interrupts. 0: Disables response to all interrupt requests. When RCON<IPEN> = 1 1: Enables response to high-priority interrupts. 0: Disables response to all high-priority interrupts. PEIE/GIEL: Peripheral Interrupt Enable bit. When RCON<IPEN> = 0: 1: Enables response to all unmasked peripheral interrupt requests. 0: Disables response to any peripheral interrupt request. When RCON<IPEN> = 1 1: Enables response to all low-priority interrupts. 0: Disables response to all low-priority interrupts. 0: Low priority. TMR0IE: Timer0 Overflow Interrupt Enable bit. 1: Enables the Timer0 overflow interrupt. 0: Disables the Timer0 overflow interrupt. INT0IE: INT0 External Interrupt Enable bit. 1: Enables the INT0 external interrupt. 0: Disables the INT0 external interrupt. RBIE: RB Port Change Interrupt Enable bit. 1: Enables the RB port change interrupt. 0: Disables the RB port change interrupt. TMR0IF: TMR0 Overflow Interrupt Flag bit. 1: Timer0 register has overflowed. Note: Clear this bit in software. 0: Timer0 register did not overflow. INT0IF: INT0 External Interrupt Flag bit. 1: An INT0 external interrupt occurred. Note: Clear this bit in software. 0: An INT0 external interrupt did not overflow. RBIF: RB Port B Change Interrupt Flag bit. 1: At least on of the Port B pins RB7:RB4 changed state. Note: Clear this bit in software. 0: None of the Port B pins RB7:RB4 changed state. 9 of 48

10 INTCON2: Interrupt Control Register 2 0xFF1 p. 76 R/W R/W R/W R/W U-0 R/W U-0 R/W Bit Names RBPU INTEDG0 INTEDG1 INTEDG2 - T0IP - RBIP PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 2 bit 0 RPBU: PORTB Pull-up Resistor Enable bit. Note: Negative logic. 1: All PORTB pull-up resistors are disabled. 0: PORTB pull-up resistors are enabled by individual port latch values. INTEDG0: External Interrupt0 Edge Select bit. 1: Interrupt on rising edge. 0: Interrupt on falling edge. INTEDG1: External Interrupt1 Edge Select bit. 1: Interrupt on rising edge. 0: Interrupt on falling edge. INTEDG2: External Interrupt2 Edge Select bit. 1: Interrupt on rising edge. 0: Interrupt on falling edge. TMR0IP: TMR0 Overflow Interrupt Priority bit 1: High priority. 0: Low priority. RBIP: RB Port Change Interrupt Priority bit 1: High priority. 0: Low priority. INTCON3: Interrupt Control Register 3 0xFF0 p. 77 R/W R/W U-0 R/W R/W U-0 R/W R/W Bit Names INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF PO/BO Reset MCLR Reset bit 7 bit 6 bit 4 bit 3 bit 1 bit 0 INT2IP: INT2 External Interrupt Priority bit. 1: High priority. 0: Low priority. INT1IP: INT1 External Interrupt Priority bit. 1: High priority. 0: Low priority. INT2IE: INT2 External Interrupt Enable bit. 1: Enables the INT2 external interrupt. 0: Disables the INT2 external interrupt. INT1IE: INT1 External Interrupt Enable bit. 1: Enables the INT1 external interrupt. 0: Disables the INT1 external interrupt. INT2IF: INT2 External Interrupt Flag bit. 1: An INT2 external interrupt request has occurred. Clear in software before enabling interrupt response. 0: An INT2 external interrupt has not been requested. INT1IF: INT1 External Interrupt Flag bit. 1: An INT1 external interrupt request has occurred. Clear in software before enabling interrupt response. 0: An INT1 external interrupt has not been requested. 10 of 48

11 PIR1: Peripheral Interrupt Request (Flag) Register 1 0xF9E p. 79 R/W R/W R R R/W R/W R/W R/W Bit Names PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSPIF: Parallel Slave Port Interrupt Flag bit. Note: Must always be 0 on 18F2X2 devices. 1: A PSP read or write has taken place. Clear this bit in software following a PSP R/W. 0: No read or write has occurred. ADIF: A/D Converter Interrupt Flag bit 1: An A/D conversion has completed. Clear this bit in software following an A/D conversion. 0: No A/D conversion has occurred. RCIF: USART Receive Interrupt Flag bit 1: The USART receive buffer, RCREG, is full. This bit is cleared when RCREG is read. 0: The USART receive buffer is empty. TXIF: USART Transmit Interrupt Flag bit 1: The USART transmit buffer, TXREG, is empty. This bit is cleared when TXREG is written. 0: The USART receive buffer is full. SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1: The transmission or reception is complete. Clear this bit in software following a SSP event. 0: Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode: 1: A TMR1 register capture has occurred. Clear this bit in software. 0: NoTMR1 register capture has occurred. Compare Mode: 1: A TMR1 register compare match capture has occurred. Clear this bit in software. 0: No TMR1 register compare match capture has occurred. PWM Mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1: TMR2 to PR2 match has occurred. Clear this bit in software following a TMR2 to PR2 match event. 0: No TMR2 to PR2 match has occurred. TMR1IF: TMR1 Overflow Interrupt Flag bit 1: TMR1 register has overflowed. Clear this bit in software following a TMR1 overflow. 0: TMR1 register has not overflowed. 11 of 48

12 PIR2: Peripheral Interrupt Request (Flag) Register 2 0xFA1 p. 79 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names EEIF BCLIF LVDIF TMR3IF CCP2IF PO/BO Reset MCLR Reset bit 4 EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit. 1: The Write operation is complete. Clear this bit in software, so that another (future) write operation completion can be detected. 0: The Write operation is in progress, or has not been started. bit 3 BCLIF: Bus Collision Interrupt Flag bit. 1: A bus collision has occurred. Clear this bit in software, so that another (future) bus collision can be detected. 0: No bus collision has occurred. bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit. 1: A low voltage condition has occurred. Clear this bit in software, so that another (future) low voltage condition can be detected. 0: The device voltage is above the Low Voltage Detect trip point. bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit. 1: TMR3 register has overflowed. Clear this bit in software, so that another overflow can be detected. 0: TMR3 register has not overflowed. bit 0 CCP2IF: CCP2 Interrupt Flag bit. Capture Mode: 1: A TMR1 register capture has occurred. Clear this bit in software. 0: NoTMR1 register capture has occurred. Compare Mode: 1: A TMR1 register compare match capture has occurred. Clear this bit in software. 0: No TMR1 register compare match capture has occurred. PWM Mode: Unused in this mode 12 of 48

13 PIE1: Peripheral Interrupt Enable Register 1 0xF9D p. 80 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSPIE: Internal Reference Voltage Stable bit. 1: Enables the PSP read/write interrupt. 0: Disables the PSP read/write interrupt. ADIE: A/D Conversion Interrupt Enable bit. 1: Enables the PSP read/write interrupt. 0: Disables the PSP read/write interrupt. RCIE: USART Receive Interrupt Enable bit. 1: Enables the UART receive interrupt. 0: Disables the UART receive interrupt. TXIE: USART Transmit Interrupt Enable bit. 1: Enables the UART transmit interrupt. 0: Disables the UART transmit interrupt. SSPIE: Master Synchronous Serial Port Interrupt Enable bit. 1: Enables the MSSP interrupt. 0: Disables the MSSP interrupt. CCP1IE: CCP1 Interrupt Enable bit. 1: Enables the CCP1 interrupt. 0: Disables the CCP1 interrupt. TMR2IE: TMR2 to PR2 Match Interrupt Enable bit. 1: Enables the TMR2 to PR2 match interrupt. 0: Disables the TMR2 to PR2 match interrupt. TMR1IE: Timer1 Overflow Interrupt Enable bit. 1: Enables the TMR1 overflow interrupt. 0: Disables the TMR1 overflow interrupt. 13 of 48

14 PIE2: Peripheral Interrupt Enable Register 2 0xFA0 p. 81 U-0 U-0 U-0 R/W R/W R/W R/W R/W Bit Names EEIE BCLIE LVDIE TMR3IE CCP2IE PO/BO Reset MCLR Reset bit 4 bit 3 bit 2 bit 1 bit 0 EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit. 1: Enabled. 0: Disabled. BCLIE: Bus Collision Interrupt Enable bit. 1: Enabled. 0: Disabled. LVDIE: Low Voltage Detect Interrupt Enable bit. 1: Enabled. 0: Disabled. TMR3IE: TMR3 Overflow Interrupt Enable bit. 1: TMR3 Overflow Interrupt Enabled. 0: TMR3 Overflow Interrupt Disabled. CCP2IE: CCP2 Interrupt Enable bit. 1: CCP2 Interrupt Enabled. 0: CCP2 Interrupt Disabled. 14 of 48

15 IPR1: Peripheral Interrupt Priority Register 1 0xF9F p. 82 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit. Note: Must always be 1 on 18F2X2 devices. 1: High priority. 0: Low priority. ADIP: A/D Converter Interrupt Priority bit 1: High priority. 0: Low priority. RCIP: USART Receive Interrupt Priority bit 1: High priority. 0: Low priority. TXIP: USART Transmit Interrupt Priority bit 1: High priority. 0: Low priority. SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1: High priority. 0: Low priority. CCP1IP: CCP1 Interrupt Priority bit 1: High priority. 0: Low priority. TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1: High priority. 0: Low priority. TMR1IP: TMR1 Overflow Interrupt Priority bit 1: High priority. 0: Low priority. IPR2: Peripheral Interrupt Priority Register 2 0xFA2 p. 83 U-0 U-0 U-0 R/W R/W R/W R/W R/W Bit Names EEIP BCLIP LVDIP TMR3IP CCP2IP PO/BO Reset MCLR Reset bit 4 bit 3 bit 2 bit 1 bit 0 EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit 1: High priority. 0: Low priority. BCLIP: Bus Collision Interrupt Priority bit 1: High priority. 0: Low priority. LVDIP: Low Voltage Detect Interrupt Priority bit. 1: High priority. 0: Low priority. TMR3IP: TMR3 Overflow Interrupt Priority bit 1: High priority. 0: Low priority. CCP2IP: CCP2 Interrupt Priority bit 1: High priority. 0: Low priority. 15 of 48

16 Bank Select Register for (Banked) Direct Addressing BSR: Bank Select Register 0xFE0 p. 49 U-0 U-0 U-0 U-0 R/W R/W R/W R/W Bit Names BSR3 BSR2 BSR1 BSR0 PO/BO Reset MCLR Reset bit 3-0 BSR3:BSR0: Bank select bits. This 4-bit field contains the upper 4 bits of the 12-bit data RAM address, allowing one of 16 banks of 256 data RAM addresses to be selected. File Select Registers for Indirect Addressing INDF0 0xFEF INDF0 is associated with using FSR0 for indirect addressing of data memory. INDF0 has the value of FSR0. It is not a physical register. See p. 50. POSTINC0 0xFEE POSTINC0 is associated with using FSR0 for indirect addressing of data memory. POSTINC0 is the value of FSR0 post-incremented. It is not a physical register. POSTDEC0 0xFED POSTDEC0 is associated with using FSR0 for indirect addressing of data memory. POSTDEC0 is the value of FSR0 post-decremented. It is not a physical register. PREINC0 0xFEC PREINC0 is associated with using FSR0 for indirect addressing of data memory. PREINC0 is the value of FSR0 pre-incremented. It is not a physical register. PLUSW0 0xFEB PLUSW0 is associated with using FSR0 for indirect addressing of data memory. PLUSW0 is the value of FSR0 offset (increased) by the value in WREG. It is not a physical register. See p. 50. FSR0: File Select Register 0 (Indirect Data Memory Address Pointer 0, 12 bits) FSR0H: High Byte (4 bits) FSR0L: Low Byte (8-bits) 0xFEA 0xFE9 p. 50 R/W R/W Byte Names FSR0H FSR0L 0xFEA 0xFE9 PO/BO Reset ---- xxxx xxxx xxxx MCLR Reset ---- uuuu uuuu uuuu This register is used for indirect addressing of the data memory. A read or write to the FSR1 = FSR1H:FSR1L register is a read or write to the data memory address pointed to by the FSR1 register. 16 of 48

17 INDF1 0xFE7 INDF1 is associated with using FSR1 for indirect addressing of data memory. INDF1 has the value of FSR1. It is not a physical register. See p. 50. POSTINC1 0xFE6 POSTINC1 is associated with using FSR1 for indirect addressing of data memory. POSTINC1 is the value of FSR1 post-incremented. It is not a physical register. POSTDEC1 0xFE5 POSTDEC1 is associated with using FSR1 for indirect addressing of data memory. POSTDEC1 is the value of FSR1 post-decremented. It is not a physical register. PREINC1 0xFE4 PREINC1 is associated with using FSR1 for indirect addressing of data memory. PREINC1 is the value of FSR1 pre-incremented. It is not a physical register. PLUSW1 0xFE3 PLUSW1 is associated with using FSR1 for indirect addressing of data memory. PLUSW1 is the value of FSR1 offset (increased) by the value in WREG. It is not a physical register. See p. 50. FSR1: File Select Register 1 (Indirect Data Memory Address Pointer 1, 12 bits) FSR1H: High Byte (4 bits) FSR1L: Low Byte (8-bits) 0xFE2 0xFE1 p. 50 R/W R/W Byte Names FSR1H FSR1L 0xFE2 0xFE1 PO/BO Reset ---- xxxx xxxx xxxx MCLR Reset ---- uuuu uuuu uuuu This register is used for indirect addressing of the data memory. A read or write to the FSR1 = FSR1H:FSR1L register is a read or write to the data memory address pointed to by the FSR1 register. 17 of 48

18 INDF2 0xFDF INDF2 is associated with using FSR2 for indirect addressing of data memory. INDF2 has the value of FSR2. It is not a physical register. See p. 50. POSTINC2 0xFDE POSTINC2 is associated with using FSR2 for indirect addressing of data memory. POSTINC2 is the value of FSR2 post-incremented. It is not a physical register. POSTDEC2 0xFDD POSTDEC2 is associated with using FSR2 for indirect addressing of data memory. POSTDEC2 is the value of FSR2 post-decremented. It is not a physical register. PREINC2 0xFDC PREINC2 is associated with using FSR2 for indirect addressing of data memory. PREINC2 is the value of FSR2 pre-incremented. It is not a physical register. PLUSW2 0xFDB PLUSW2 is associated with using FSR2 for indirect addressing of data memory. PLUSW2 is the value of FSR2 offset (increased) by the value in WREG. It is not a physical register. See p. 50. FSR2: File Select Register 2 (Indirect Data Memory Address Pointer 2, 12 bits) FSR2H: High Byte (4 bits) FSR2L: Low Byte (8-bits) 0xFDA 0xFD9 p. 50 R/W R/W Byte Names FSR2H FSR2L 0xFDA 0xFD9 PO/BO Reset ---- xxxx xxxx xxxx MCLR Reset ---- uuuu uuuu uuuu This register is used for indirect addressing of the data memory. A read or write to the FSR2 = FSR2H:FSR2L register is a read or write to the data memory address pointed to by the FSR2 register. 18 of 48

19 Timer0 TMR0H: Timer0 Module High Byte Register 0xFD7 p. 105 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR0H bits are not individually named. PO/BO Reset MCLR Reset u u u u u u u u TMR0L: Timer0 Module Low Byte Register 0xFD6 p. 105 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR0L bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u T0CON: Timer0 Module Control Register 0xFD5 p. 103 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 TMR0ON: Timer0 On/Off Control bit. 1: Enables Timer0. 0: Stops Timer0. T08BIT: Timer0 8-bit/16-bit Control bit. 1: Timer0 is configured as an 8-bit timer/counter. 0: Timer0 is configured as a 16-bit timer/counter. T0CS: Timer0 Clock Source Select bit. 1: Transition on T0CKI pin. 0: Internal instruction cycle clock output (CLKO). T0SE: Timer0 Source Edge Select bit. 1: Increment on high-to-low transition on T0CKI pin. 0: Increment on low-to-high transition on T0CKI pin. PSA: Timer0 Prescaler Assignment bit. 1: TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0: Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits. This 3-bit field selects one of the eight Timer0 prescale values (input clock divisor values), between 2 and 256. See datasheet. 19 of 48

20 Timer1 TMR1H: Holding Register for the MSB of the 16-bit Timer1 Register 0xFCF p. 107 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR1H bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u TMR1L: Holding Register for the LSB of the 16-bit Timer1 Register 0xFCE p. 107 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR1L bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u T1CON: Timer1 Module Control Register 0xFCD p. 107 R/W U-0 R/W R/W R/W R/W R/W R/W Bit Names RD16 - T1CKPS1 T1CKPS0 T1OSCEN #T1SYNC TMR1CS TMR1ON PO/BO Reset MCLR Reset u - u u u u u u bit 7 RD16: 16-bit Read/Write Mode Enable bit. 1: Enables register Read/Write of Timer1 in one 16-bit operation. 0: Enables register Read/Write of Timer1 in two 8-bit operations. bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits. This 2-bit field selects one of the four Timer1 prescale values (input clock divisor values), between 1 and 8. See datasheet. bit 3 T1OSCEN: Timer1 Oscillator Enable bit. 1: Timer1 Oscillator is enabled. 0: Timer1 Oscillator is shut-off. Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 #T1SYNCH: Timer1 External Clock Input Synchronization Select bit. Note: Negative logic. When TMR1CS = 1: 1: Do not synchronize external clock input. 0: Synchronize external clock input. When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit. 1: External clock from pin RC0/T1OSO/T1CKI (on the rising edge). 0: Internal clock (F OSC /4). bit 0 TMR1ON: Timer1 On bit. 1: Enables Timer1. 0: Stops Timer1. 20 of 48

21 Timer2 TMR2: Timer2 Module Register 0xFCC p. 111 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR2 bits are not individually named. PO/BO Reset MCLR Reset PR2: Timer2 Period Register 0xFCB p. 112 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The PR2 bits are not individually named. PO/BO Reset MCLR Reset T2CON: Timer2 Module Control Register 0xFCA p. 111 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names - TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 PO/BO Reset MCLR Reset bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits. This 2-bit field selects one of the four Timer1 postscale values (output divisor values), between 1 and 16. See datasheet. bit 2 TMR2ON: Timer2 On bit. 1: Timer2 is On. 0: Timer2 is Off. bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits. This 2-bit field selects one of the three Timer2 prescale values (input clock divisor values): 1, 4 or 16. See datasheet. 21 of 48

22 Timer3 TMR3H: Holding Register for the MSB of the 16-bit Timer3 Register 0xFB3 p. 113 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR3H bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u TMR3L: Holding Register for the LSB of the 16-bit Timer3 Register 0xFB2 p. 113 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TMR3L bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u T3CON: Timer3 Module Control Register 0xFB1 p. 113 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 #T3SYNC TMR3CS TMR3ON PO/BO Reset MCLR Reset u u u u u u u u bit 7 RD16: 16-bit Read/Write Mode Enable bit. 1: Enables register Read/Write of Timer3 in one 16-bit operation. 0: Enables register Read/Write of Timer3 in two 8-bit operations. bit 6, 3 T3CCP2, T3CCP1: Timer3 and Timer1 to CCPx Enable bits. This 2-bit field configures the clock sources (Timer1 or Timer3) that are used as timebases for CCP1 and CCP2. See datasheet. bit 5, 4 T3CKPS1, T3CKPS0: Timer3 Input Clock Prescale Select bits. This 2-bit field selects one of the four Timer3 prescale values (input clock divisor values): 1, 2, 4 or 8. See datasheet. bit 2 #T3SYNCH: Timer3 External Clock Input Synchronization Select bit. Note: Not usable if the system clock comes from Timer1 or Timer3. Note: Negative logic. When TMR3CS = 1: 1: Do not synchronize external clock input. 0: Synchronize external clock input. When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit. 1: External clock input from Timer1 oscillator or T1CKI pin, on the rising edge after the first falling edge. 0: Internal clock (F OSC /4). bit 0 TMR3ON: Timer3 On bit. 1: Enables Timer3. 0: Stops Timer3. 22 of 48

23 Miscellaneous Control Registers OSCCON: Oscillator Control Register 0xFD3 p. 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W Bit Names SCS PO/BO Reset MCLR Reset bit 0 SCS: System Clock Switch bit. 1: Switch to Timer1 oscillator/clock pin 0: Use primary oscillator/clock input pin Note: System Clock Switch bit is enabled only if CONFIG1H<OSCSEN> = 0 and T1CON<T1OSCEN> = 1 LVDCON: Low Voltage Detect Control Register 0xFD2 p. 191 U-0 U-0 R R/W R/W R/W R/W R/W Bit Names - - IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 PO/BO Reset MCLR Reset bit 5 bit 4 IVRST: Internal Reference Voltage Stable bit 1: LVD logic will generate the interrupt flag at the specified voltage range 0: LVD logic will not generate the interrupt flag do not enable the LVD interrupt LVDEN: Low Voltage Detect Power Enable bit 1: Enables LVD, powers up LVD circuit 0: Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low Voltage Detection Level bits This 4-bit field sets the range of voltage within which a low voltage level is detected. See datasheet. WDTCON: Watchdog Timer Control Register 0xFD1 p. 203 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W Bit Names SWDTEN PO/BO Reset MCLR Reset bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1: Watchdog Timer is on 0: Watchdog Timer is off if CONFIG2H<WDTEN> = 0 23 of 48

24 RCON: Reset Control Register 0xFD0 p. 53, 28, 84 R/W U-0 U-0 R/W R/W R/W R/W R/W Bit Names IPEN - - RI TO PD POR BOR PO/BO Reset q q MCLR Reset q q q u u bit 7 IPEN: Interrupt Priority Enable bit 1: Enable priority levels on interrupts 0: Disable priority levels on interrupts (PIC16CXX compatibility mode) bit 4 RI: Not RESET Instruction Flag bit. Note: Negative logic. 1: The RESET instruction was not executed 0: The RESET instruction was executed, causing a device RESET. Set this bit in software after a RESET occurs, so that execution of another (future) RESET instruction can be detected. bit 3 TO: Not Watchdog Time-out Flag bit. Note: Negative logic. 1: After power-up, or by execution of the CLRWDT or SLEEP instructions. 0: A WDT time-out has occurred bit 2 PD: Not Power-down Detection Flag bit. Note: Negative logic. 1: After power-up, or by execution of the CLRWDT instruction 0: By execution of the SLEEP instruction bit 1 POR: Not Power-on Reset Status bit. Note: Negative logic. 1: A Power-on Reset has not occurred 0: A Power-on Reset has occurred. Set this bit in software after a POR occurs, so that another (future) POR event can be detected. bit 0 BOR: Not Brown-out Reset Status bit. Note: Negative logic. 1: A Brown-out Reset has not occurred 0: A Brown-out Reset has occurred. Set this bit in software after a BOR occurs, so that another (future) BOR event can be detected. 24 of 48

25 MSSP Module SSPBUF: Synchronous Serial Receive/Transmit Buffer 0xFC9 p. 125 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The SSBUF bits are not individually named. PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u SSPADD: MSSP Address Register 0xFC8 p. 134 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The SSPADD bits are not individually named. PO/BO Reset MCLR Reset Note: Holds the slave device address when the MSSP is configured in I 2 C Slave mode. Note: When the MSSP is configured in I 2 C Master mode, the low 7 bits act as the baud rate generator reload value. SSPSTAT: MSSP Status Register (in SPI Mode) 0xFC7 p. 126 R/W R/W R R R R R R Bit Names SMP CKE D/#A P S R/#W UA BF PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SMP: Sample bit. In SPI Master mode: 1: Input data sampled at end of data output time. 0: Input data sampled at middle of data output time. In SPI Slave mode: 1: Illegal. 0: SMP must be cleared when SPI is used in Slave mode. CKE: SMBus Select bit. When CKP = 1: 1: Data transmitted on falling edge of SCK. 0: Data transmitted on rising edge of SCK. When CKP = 0: 1: Data transmitted on rising edge of SCK. 0: Data transmitted on falling edge of SCK. D/#A: Data / #Address bit. Not used in SPI mode. P: Stop bit. Not used in SPI mode. S: Start bit. Not used in SPI mode. R/#W: Read / #Write bit Information. Not used in SPI mode. UA: Update Address. Not used in SPI mode. BF: Buffer Full Status bit. (Receive mode only). In SPI Receive mode: 1: Receive complete, SSPBUF is full. 0: Receive not complete, SSPBUF is empty. 25 of 48

26 SSPCON1: MSSP Control Register1 (in SPI Mode) 0xFC6 p. 127 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 WCOL: Write Collision Detect bit. (Transmit mode only) 1: The SSPBUF register was written to while it is still transmitting the previous word. Clear this bit in software after a collision occurs, so that another (future) collision can be detected. 0: No collision. SSPOV: Receive Overflow Flag bit.. In SPI Slave mode: 1: A new byte was received while the SSPBUF register was still holding the previous data. In case of overflow, the previous data in the SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid SSPOV being set. Clear this bit in software after an overflow occurs, so that another (future) overflow can be detected. 0: No overflow. In SPI Master mode: Note: In SPI Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. SSPEN: Synchronous Serial Port Enable bit. 1: Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins. 0: Disables serial port and configures these pins as I/O port pins. CKP: Clock Polarity Select bit. 1: IDLE state for clock is a high level. 0: IDLE state for clock is a low level. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode bits. This 4-bit field sets the MSSP to one of the six SPI operating modes. See datasheet. Note: Only SSPCON1 is used in SPI mode SSPCON2 is not used. 26 of 48

27 SSPSTAT: MSSP Status Register (in I 2 C Mode) 0xFC7 p. 135 R/W R/W R R R R R R Bit Names SMP CKE D/#A P S R/#W UA BF PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SMP: Slew Rate Control bit. In I 2 C Master or Slave mode: 1: Slew rate control disabled for Standard Speed mode (100 khz and 1 MHz) 0: Slew rate control enabled for High Speed mode (400 khz) CKE: SMBus Select bit. In I 2 C Master or Slave mode: 1: Enable SMBus specific inputs 0: Disable SMBus specific inputs D/#A: Data / #Address bit. In I 2 C Master mode: Reserved. In I 2 C Slave mode: 1: Indicates that the last byte received or transmitted was data. 0: Indicates that the last byte received or transmitted was address. P: Stop bit. 1: Indicates that a STOP bit has been detected last. Note: This bit is cleared on RESET and when SSPEN is cleared. 0: STOP bit was not detected last. S: Start bit. 1: Indicates that a start bit has been detected last. Note: This bit is cleared on RESET and when SSPEN is cleared. 0: START bit was not detected last. R/#W: Read / #Write bit Information (I 2 C mode only). In I 2 C Slave mode: Note: The R/#W bit holds the R/#W bit information following the last address match. This bit is only valid from the address match to the next I 2 C START, STOP, or #ACK bit. 1: Read. 0: Write. In I 2 C Master Mode: Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. 1: Transmit is in progress. 0: Transmit is not in progress. UA: Update Address (10-bit Slave mode only). 1: Indicates that the user needs to update the address in the SSPADD register. 0: Address does not need to be updated. BF: Buffer Full Status bit. In I 2 C Transmit mode: 1: Receive complete, SSPBUF is full. 0: Receive not complete, SSPBUF is empty. In I 2 C Receive mode: 1: Data transmit in progress (does not include the I 2 C #ACK and STOP bits), SSPBUF is full 0: Data transmit complete (does not include the I 2 C #ACK and STOP bits), SSPBUF is empty. 27 of 48

28 SSPCON1: MSSP Control Register1 (in I 2 C Mode) 0xFC6 p. 136 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 WCOL: Write Collision Detect bit. In I 2 C Master Transmit mode: 1: A write to the SSPBUF register was attempted while the I 2 C conditions were not valid for a transmission to be started. Clear this bit in software after a collision occurs, so that another (future) collision can be detected. 0: No collision. In I 2 C Slave Transmit mode: 1: The SSPBUF register was written to while it was still transmitting the previous word. Clear this bit in software after a collision occurs, so that another (future) collision can be detected. 0: No collision. In I 2 C Receive mode (Master or Slave modes): This is a don t care bit in I 2 C Receive mode. SSPOV: Receive Overflow Flag bit. In I 2 C Receive mode: 1: A byte is received while the SSPBUF register is still holding the previous byte. Clear this bit in software after an overflow occurs, so that another (future) overflow can be detected. 0: No overflow. In I 2 C Transmit mode: This is a don t care bit in I 2 C Transmit mode. SSPEN: Synchronous Serial Port Enable bit. 1: Enables the serial port and configures the SDA and SCL pins as the serial port pins. Note: When enabled, the SDA and SCL pins must be properly configured as input or output. 0: Disables serial port and configures these pins as I/O port pins. CKP: SCK Release Control bit. In I 2 C Slave mode: 1: Release clock. 0: Holds clock low (clock stretch), used to ensure data setup time. In I 2 C Master mode: This is a don t care bit in I 2 C Master mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode bits. This 4-bit field sets the MSSP to one of the six I 2 C operating modes. See datasheet. 28 of 48

29 SSPCON2: MSSP Control Register2 (I 2 C Mode only) 0xFC5 p. 137 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN PO/BO Reset MCLR Reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 GCEN: General Call Enable bit (Slave mode only) 1: Enable interrupt when a general call address (0000h) is received in the SSPSR. 0: General call address disabled. ACKSTAT: Acknowledge Status bit (Master Transmit mode only). 1: Acknowledge was not received from slave. 0: Acknowledge was received from slave. ACKDT: Acknowledge Data bit (Master Receive mode only). 1: Not Acknowledge. 0: Acknowledge. ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only). 1: Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0: Acknowledge sequence IDLE. RCEN: Receive Enable bit (Master mode only). 1: Enables Receive mode for I 2 C. 0: Receive IDLE. PEN: STOP Condition Enable bit (Master mode only). 1: Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0: STOP condition IDLE. RSEN: Internal Reference Voltage Stable bit 1: Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0: Repeated START condition IDLE. SEN: Write Collision Detect bit. In I 2 C Master mode: 1: Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0: START condition IDLE. In I 2 C Master mode: 1: Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled). 0: Clock stretching is enabled for slave transmit only. (Legacy mode). Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I 2 C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Note: SSPCON2 is not used in SPI mode. 29 of 48