Mid-Range Family Peripheral Configuration with C Programming

Transcription

1 Mid-Range Family Peripheral Configuration with C Programming MCU 2 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28

2 Objectives At the end of this class you will: Understand the basic PICmicro peripherals and their associated registers Have HANDS ON experience initializing Mid-Range peripherals using the XC8 C compiler Understand interrupts and polling Write your own application code from scratch Slide 2

3 To get the most from this Class Ideally you should be familiar with the following: Writing simple programs in C Basic Mid-Range family Instruction set Data and Program memory organization MPLAB Integrated Development Environment Microchip ICD 2 debugger Slide 3

4 Agenda Brief review of Mid-Range Architecture, Instruction Set and Tools Using XC8 s C compiler with MPLAB Lab-Using PICC with MPLAB X IDE Interrupts on the Mid-Range PICmicro Lab-External Interrupt Lab Peripheral discussion: Input/Output Ports Timers Timer Timer Lab2-Timer Lab Timer2 Lab3-Timer2 Lab Slide 4

5 Agenda (cont.) Capture / Compare / PWM Module (CCP) Lab4-PWM & Lab5-Output Compare Labs Analog Comparator Analog to Digital Converters (ADC) Lab6-ADC Lab Addressable Universal Asynchronous & Synchronous Receiver & Transmitter (AUSART) I 2 C with the Master Synchronous Serial Port Wrap-Up and additional questions Slide 5

6 Mid-Range Family Basic Architecture and Development Tools 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 6

7 Microchip s MCU Families /E Slide 7

8 Mid-Range PIC Block Diagram PROGRAM MEMORY Non-Volatile (Flash) Holds program instructions that tell CPU what to do Oscillator PIC6 Core Working STATUS OPTION ALU CPU The Brains Performs all instruction, logic, and mathematical processing DATA MEMORY Volatile (SRAM) Holds data under the control of instructions Slide 8

9 Mid-Range PIC Block Diagram PROGRAM MEMORY Oscillator PIC6 Core Working STATUS OPTION DATA MEMORY I/O PORTS BIT ADC ALU CPU Peripherals Hang Off the Data Bus COMPARATORS TIMERS EEPROM Cap/ Com/ PWM SPI / I 2 C VOLTAGE REF USART Slide 9

10 Flash Program Memory PROGRAM MEMORY Page Page Page 2 Page 3 Stores the instructions (your code) Tells the CPU what to do The amount of Program Memory is device specific All Instructions are 4-bits wide instruction = Program Memory Address Divided into pages Slide

11 Flash Program Memory Why do we need Program Memory paging? PROGRAM MEMORY h 7FFh 8h Page With a 4 bit instruction, only bits can be used to specify a program memory address in a single cycle FFFh h 7FFh 8h Page Page Opcode GOTO Instruction in Program Memory 2 = 248 addresses FFFh Page 3 Slide

12 SRAM Data Memory Divided into BANKs # of banks is device dependent (4 banks max) 2 groups of Registers: Special Function Registers (SFR) Control CPU and Peripheral functions General Purpose Registers (GPR) Store user defined variables Data Memory SFR GPR Bank Slide 2

13 Data Memory Banks h Special Function Registers 8h Special Function Registers h Special Function Registers 8h Special Function Registers Note Data Memory Addresses General Purpose Registers General Purpose Registers General Purpose Registers General Purpose Registers 28 Bytes 7Fh FFh Accesses 7h 7Fh 7Fh Accesses 7h 7Fh FFh Accesses 7h 7Fh Bank Bank Bank 2 Bank 3 Slide 3

14 Data Memory Banks Why do we need Data Memory banks? h DATA MEMORY SFR With a 4 bit instruction, only 7 bits can be used to specify a data memory address in a single cycle The STATUS register holds additional bits (RP, RP, IRP) used to select of 4 data banks. GPR Byte Oriented Instruction (i.e. ADDWF) Opcode 2 7 = 28 addresses 7Fh Bank Slide 4

15 A B C D INDF TMR PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON Data Memory SFRs Special Function Registers Bank Bank Bank 2 Bank A 8B INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON A B INDF TMR PCL STATUS FSR PORTB PCLATH INTCON INDF OPTION_REG PCL STATUS FSR TRISB PCLATH INTCON PIR 8C PIE C EEDATA 8C EECON PIR2 8D PIE2 D EEADR 8D EECON A 8B See data sheet for actual SFR locations Slide 5

16 Status Register bit 7 bit IRP RP RP TO PD Z DC C Reset Status Bits RP PD TO Power Down (SLEEP instr executed?) Time Out (WDT Timeout?) RP C DC Z ALU Status Bits Carry (Byte Overflow?) Digit Carry (Nibble (4 bit) Overflow?) Zero (Is the ALU Result s?) Slide 6

17 Status Register bit 7 bit IRP RP RP TO PD Z DC C Data Memory bank select bit (Indirect Addressing) Data Memory bank select bits (Direct Addressing) IRP RP RP RP BANKS & RP RP BANK BANKS & 2 BANK BANK2 BANK3 Slide 7

18 PIC6 Instruction Set 35 single word instructions All are single cycle except for program branches Byte Oriented Operations addwf f,d Add W and f andwf f,d AND W with f clrf f Clear f clrw - Clear W comf f,d Complement f decf f,d Decrement f decfsz f,d Decrement f, Skip if incf f,d Increment f incfsz f,d Increment f, Skip if iorwf f,d Inclusive OR W with f movf f,d Move f movwf f Move W to f nop - No Operation rlf f,d Rotate Left f through Carry rrf f,d Rotate Right f through Carry subwf f,d Subtract W from f swapf f,d Swap nibbles in f xorwf f,d Exclusive OR W with f Bit Oriented Operations bcf f,b Bit Clear f bsf f,b Bit Set f btfsc f,b Bit Test f, Skip if Clear btfss f,b Bit Test f, Skip if Set Literal and Control Operations addlw k Add literal and W andlw k AND literal with W call k Call subroutine clrwdt - Clear Watchdog Timer goto k Go to address iorlw k Inclusive OR literal with W movlw k Move literal to W retfie - Return from interrupt retlw k Return with literal in W return - Return from Subroutine sleep - Go into standby mode sublw k Subtract W from literal xorlw k Exclusive OR literal with W Slide 8

19 PICmicro Development Tools 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 9

20 MPLAB X Integrated Development Environment Slide 2

21 MPLAB X IDE Unified Development Platform Single, unified, graphical user interface Supports all Microchip 8, 6 and 32-bit MCUs Supports Microchip C & C++ compilers, simulators, emulators, debuggers and starter kits FREE Supports many third-party compilers, RTOS, simulators, debuggers, programmers, etc. Based on open-source NetBeans platform Runs under Windows, Linux, and Mac OS X Slide 2

22 MPLAB X IDE (Integrated Development Environment) Integrates Microchip and third party tools Compilers, Assemblers In-Circuit Debuggers Simulators Emulators Code Editor Programmers Slide 22

23 The MPLAB X Ecosystem In-Circuit Debug Tool Feature Comparison Feature PICkit 3 ICD 3 REAL ICE USB Speed Full High High Power to Target HW Breakpoints SW Breakpoints Stopwatch Trace Data Capture Logic Probe / Trigger Slide 23

24 MPLAB ICD 2 In Circuit Debugger & Programmer MPLAB ICD 2 is a low cost, real-time debugger and programmer. Reads and Writes Program, Data and E 2 memory Real time debugging Step through instructions while monitoring data memory registers Programs configuration bits Slide 24

25 PICDEM 2 Plus Board 9V to 5V regulator LEDs Analog Pot 6 x 2 LCD Module RS232 Connecto r ICD Connecto r Piezo Buzzer I 2 C Based Temp Sensor 8, 28 and 4- pin DIP sockets Push button Switches Slide 25

26 XC8 C Compiler with MPLAB X 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 26

27 MPLAB XC Compilers Unified Compiler Platform MPLAB XC8 8-bit Architecture MPLAB XC6 6-bit Architecture MPLAB XC32 32-bit Architecture MPLAB XC Suite All PIC MCUs and dspic DSCs Straightfoward line of C compilers that provide the best execution speed and code size for all PIC MCUs and dspic DSCs Slide 27

28 OPTIMIZATIONS Compiler Editions Compiler License Cost Evaluation PRO Optimizations for 6 days then Free Compiller All devices and memory supported Commercial Use Permitted XC8 Pro XC8 Standard Free Optimized All devices and memory supported Commercial Use Permitted Workstation $995 Network $,295 Workstation $495 Network $595 Standard Optimized 2-25% better than Free All devices and memory supported Commercial Use Permitted PRO Optimized ~5% better than Free All devices and memory supported Commercial Use Permitted FREE FREE $495 $995 Slide 28

29 Using C Language Advantages Faster Development Cycle Algorithms more easily written in C Easier to Develop Code Bank Switching and Paging handled by compiler Easier to Debug Code C s implementation of control structures and decision branches well tested Disadvantages Higher Memory Utilization C Takes more Program Memory space than Assembly in most applications Program Execution Time More instructions per task = more time per task Execution time of C programs needs to be verified Time critical tasks are typically coded in assembly Slide 29

30 Configuring Registers with PICC INTCON (Interrupt Control Register) GIE PEIE TMRIE INTE RBIE TMRIF INTF RBIF bit 7 bit Example: Enable Global Interrupts and Timer Interrupts 3 ways to do this. INTCON = xa; /* write all bits in INTCON * register using hex */ 2 INTCON = b; //write all bits using binary 3 GIE = ; //set the Global Interrupt bit TMRIE = ; //set the Timer Interrupt bit Slide 3

31 Mixing Assembly with C Assembly code can be inserted into C code 2 ways to do this. asm( movlw h ); asm( movwf 2h ); // Insert one assembly // instruction at a time 2 #asm movlw h movwf 2h #endasm // Insert a block of // instructions using the // #asm directive Slide 3

32 Manipulating C Objects in Assembler #include <xc.h> Defines an 8-bit register called var unsigned char var; void main (void) { TRISB = X; var = ; Underscore needed in order to #asm manipulate in assembly rlf _var rlf _var //move 2 bits to the left #endasm } PORTB = var; while(); Slide 32

33 Lab : My First Project 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 33

34 Lab : XC8 and MPLAB IDE Goals: Work with XC8 and MPLAB X IDE environment to create a C-Based Project To Do: Follow the slides Expected Result: Successfully build the project and program the device LED RB should blink Slide 34

35 Lab : PICC and MPLAB X IDE Create and name a new project Slide 35

36 Double Click Current Compiler Lab : XC8 and MPLAB X IDE Select the Language Toolsuite Select XC8 Compiler Slide 36

37 Lab : XC8 and MPLAB X IDE Select the device for this project Click Configure and Select Device Slide 37

38 Lab : PICC and MPLAB IDE Set the Core Configuration Bits Set all Configuration Bit as shown Click Generate Source Code to Output Slide 38

39 Lab : XC8 and MPLAB X IDE Header files and MPLAB MPLAB IDE does not use files placed in the Header Files folder when building. Consider it a means to document a project's dependency on a header file, and a convenient method to access these files. If you want to use header files, they must be included in the source code. Slide 39

40 Modify main.c file void main(void) { unsigned int i; Lab : XC8 and MPLAB X IDE /* Configure the oscillator for the device */ ConfigureOscillator(); /* Initialize I/O and Peripherals for application */ InitApp(); PORTB = x; ADCON = x6; TRISB = x; } while() { /* TODO <INSERT USER APPLICATION CODE HERE> */ RB = ; for(i=;i<xfff;i++); RB = ; for(i=;i<xfff;i++); } Slide 4

41 Lab : XC8 and MPLAB X IDE Building the project Slide 4

42 Interrupts 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 42

43 Polling and Interrupts Often we would like the processor to perform a task if a specific event occurs Two methods to check if this event has occurred: Polling: Continuously check for event at various points in the code Interrupts: INTERRUPTS the Main program and starts an Interrupt Service Routine when an event occurs Slide 43

44 Polling Example RA = ; //Set bit of PORTA while(rb == ); //Loop while bit //of PORTB is RA = ; //Clear bit of PORTA RA = Set PORTA bit Test (poll) for a on PORTB bit Clear PORTA bit if RBO = No RB =?? Yes RA = Slide 44

45 Interrupt Example //=====Main Routine=========== void main (void) { } //==Interrupt Service Routine== void interrupt isr (void) { } Main program code Interrupt Service Routine (ISR) ISR completed Main( ) program execution Execute ISR( ) no interrupt interrupt flag set Slide 45

46 Enabling Interrupts Processor must be told that interrupts will be used A number of registers with interrupt enable bits do this: Interrupt Control (INTCON) Peripheral Interrupt Enable (PIE) Peripheral Interrupt Enable 2 (PIE2) Slide 46

47 TMR2IE TMR2IF Timer External interrupt Change on a PORTB pin TMRIE TMRIF INTE INTF RBIE RBIF Interrupt Logic Bits located in the INTCON register Interrupt GIE ADIE ADIF Other peripherals PEIE Global interrupt enable Peripheral interrupt enable Slide 47

48 bit 7 INTCON Register (Core Interrupts) bit GIE PEIE TMRIE INTE RBIE TMRIF INTF RBIF Enable Bits GIE PEIE TMRIE INTE RBIE Description Global Interrupt Enable Peripheral Interrupt Enable Timer Interrupt Enable External Interrupt Enable PORTB change Interrupt Enable Must be set to use any interrupts Must be set to use any peripheral interrupts Flags will set even if interrupts aren t enabled! Flag Bits TMRIF INTF RBIF Description Timer Overflow Interrupt Flag RB/INT External Interrupt Flag PORTB Change Interrupt Flag Slide 48

49 Enabling a Core Interrupt (External Interrupt) void interrupt isr (void) { //clear External Interrupt //flag to enable interrupts //after this ISR INTF = ; } //<ISR code> prog mem address prog mem address Program Counter Stack void main (void) { <code to set up PORTB > // initialize INTCON INTCON = b; //enable an external //interrupt on the INT pin INTE = ; //enable global interrupts GIE = ; INTCON GIE GIE bit automatically cleared by hardware INTE GIE bit automatically set when ISR completes INTF Interrupt detected on RB/INT pin } while() ; //loop forever Slide 49

50 Peripheral Interrupts Two registers ENABLE interrupts for peripherals Peripheral Interrupt Enable (PIE) Peripheral Interrupt Enable 2 (PIE2) Two registers display peripheral REQUESTS for an interrupt (Flags) Peripheral Interrupt Request (PIR) Peripheral Interrupt Request 2 (PIR2) Flags will set even if interrupts are not enabled!! Slide 5

51 PIE and PIR Registers* PIE Register (Peripheral Interrupt Enables) ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMRIE PIR Register (Peripheral Interrupt Requests) ADIF RCIF TXIF SSPIF CCPIF TMR2IF TMRIF Enable ADIE RCIE TXIE SSPIE CCPIE TMR2IE TMRIE Flag ADIF RCIF TXIF SSPIF CCPIF TMR2IF TMRIF Condition ADC conversion complete AUSART receive buffer is full AUSART transmit buffer is full I 2 C or SPI Interrupt Timer register capture or compare match Timer2 value and PR2 period value match Timer register has overflowed *Check individual data sheets for bit locations. Slide 5

52 PIE2 and PIR2 Registers* PIE2 Register (Interrupt Enables) OSCFIE C2IE CIE EEIE BCLIE ULPWUIE CCP2IE PIR2 Register (Interrupt Flags) OSCFIF C2IF CIF EEIF BCLIF ULPWUIF CCP2IF Enable OSCFIE C2IE CIE EEIE BCLIE ULPWUIE CCP2IE Flag OSCFIF C2IF CIF EEIF BCLIF ULPWUIF CCP2IF Condition System Oscillator Failed Comparator2 output changed Comparator output changed Write operation completed Bus collision occurred in MSSP I 2 C mode Wake-up condition occurred Timer Capture or Compare match occurred *Check individual data sheets for bit locations. Slide 52

53 Enabling a Peripheral Interrupt (Timer) void interrupt isr (void) { //Clear the interrupt flag TMRIF = ; // <ISR code> } //ISR completes void main (void) { //clear the interrupt flag TMRIF = ; //enable Timer interrupt TMRIE = ; //Enable peripheral and //global interrupts PEIE = ; GIE = ; // <code to set up Timer> while(); //loop forever } while(); address while(); address INTCON GIE PEIE PIE PIR GIE bit automatically cleared by hardware GIE bit automatically set when ISR completes Program Counter Stack TMRIE TMRIF Slide 53 Interrupt detected on RB/INT pin

54 Interrupt Latency Interrupt Latency: Time from interrupt event to execution of instruction at address 4h Synchronous interrupts (typically internal) latency is 3 instruction cycles (Tcy) Asynchronous interrupts (typically external) latency is 3 4 instruction cycles ISR main() CPU EXECUTION TRACE Slide 54

55 Interrupt Priority Mid-Range PIC microcontrollers treat all Interrupts with the same priority The user must do the following: Determine source of interrupt Determine the order in which the interrupts are serviced. Slide 57

56 Interrupt Priority Example void interrupt isr (void) { //Check various interrupt flags and respond //accordingly //If the RBIF flag is set, then perform the PORTB_ISR subroutine if (RBIF) PORTB_ISR ( ); //If TMR2IF flag is set, then perform the Timer2_ISR subroutine if (TMR2IF) Timer2_ISR ( ); //If the TMRIF flag is set, then perform the Timer_ISR subroutine if (TMRIF) Timer_ISR ( ); } Slide 58

57 External Interrupt Hands on Lab 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 59

58 External Interrupts The objective of this is to: Learn how to set up and enable an external interrupt on the Mid-Range PIC Become more familiar with the MPLAB IDE, the PICdem2 Plus and the ICD 2 Write 3 lines of code Build and debug the project Slide 6

59 External Interrupt Lab Overview Interrupt Vector Call debounce delay function Increment Count variable Clear IF Return to Main Main Program Clear Variables Initialize PORTB (RB) for S3 input Enable Interrupts No Operation NOP Slide 6

60 Lab Specifics The S3 switch is connected to the RBO/INT pin on PORTB The push_count register will display the # of times S3 has been pushed. Use MPLAB and the ICD to set a breakpoint in the code to view the changing value of the register named push_count Slide 62

61 What you need to know The function of the INTCON register bits Jumper J6 must be removed in order for the INTE pin to work A subroutine called debounce is given masks the mechanical bouncing of S3 How to setup break points and a Watch Window in MPLAB Slide 63

62 External Interrupt Lab Solution Slide 64

63 Peripherals 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 65

64 Mid-Range Family Peripherals I/O Ports Timers (,, 2) Capture/Compare/PWM Comparators Analog-to-Digital Converter AUSART I 2 C and SPI Serial Interface Slide 66

65 Input/Output (I/O) Ports 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 67

66 I/O Overview Up to 35 bi-directional Input/Output pins some multiplexed with peripheral functions After Reset: Analog capable pins come up as Analog Digital I/O pins come up as Digital Input Direct, single cycle bit manipulation High drive capability 25mA source or sink Slide 68

67 PORTx and TRISx Registers Every PORT (A, B, C, D, E) will have a corresponding direction register TRISx PORTB Register RB7 RB6 RB5 RB4 RB3 RB2 RB RB Data Configures Data Direction PORTB Tri-State Register (TRISB) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB TRISB = corresponding PORTB pin is an INPUT = corresponding PORTB pin is an OUTPUT Slide 69

68 Configuring Analog Inputs as Digital I/O s with digital and analog capabilities default to analog on reset Slide 7

69 Configuring Analog Inputs as Digital Two ways to configure Analog inputs as Digital ) Analog Select Registers (ANSEL and ANSELH) For devices with > 8 analog pins Analog Select Register (ANSEL) ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS ANS Analog Select High Register (ANSELH) ANS3 ANS2 ANS ANS ANS9 ANS8 = Pin assigned as Analog Input = Digital I/O OR 2) ADC Control register (ADCON) For devices with 8 or less analog pins ADC Control Register (ADCON) Port Configuration Bits ADFM ADCS2 PCFG3 PCFG2 PCFG PCFG Slide 7

70 Configuring Analog Inputs as Digital PCFG <3:> AN7 AN6 AN5 AN4 AN3 AN2 AN Vdd AN ADC Control Register (ADCON) Port Configuration Bits ADFM ADCS2 PCFG3 PCFG2 PCFG PCFG Slide 72

71 Initializing Digital I/O with ADCON register (PIC6F877A) Example: Initializing PORTB bits RB<7:4> as digital inputs and RB<3:> as digital outputs //---configure PORTB for digital PORTB = x; //Clear PORTB ADCON = x6; //Configure as all digital //---Set up direction of each PORTB pin TRISB = b; // = input, = output Slide 73

72 Initializing Digital I/O with ANSEL and ANSELH registers (PIC6F887) Example: Initializing PORTB bits RB<7:4> as digital inputs and RB<3:> as digital outputs //---configure PORTB for digital PORTB = x; //Clear PORTB ANSLEH = x; //Configure as all digital ANSEL = x; //---Set up direction of each PORTB pin TRISB = b; // = input, = output Slide 74

73 PORTB Interrupt & Weak Pull-Up Options All PORTB pins have Interrupt-on-Change and Weak Pull-Up options Weak Pull-Up PORTB Register (WPUB) WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB WPUB = Pull-up enabled = Pull-up disabled Interrupt-On-Change PORTB Register (IOCB) IOCB7 IOCB6 IOCB5 IOCB4 ICOB3 IOCB2 IOCB IOCB = Interrupt-on-change enabled = Interrupt-on-change disabled Interrupt Control Register (INTCON) HIGH LOW GIE PEIE TMRIE INTE RBIE TMRIF INTF RBIF Devices without WPUB register use RBPU bit in OPTION register Devices without IOCB rely on RBIE bit in INTCON RBIF *PORTB must first be read/written and then RBIF can be cleared in software RB3 RB4 Slide 75

74 Timers 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 76

75 Timers can be used as: A Timer To Time an Event on an Input To Generate an output clock or waveform Event counter Count an event Timer Applications TMR Start Timing Stop Timing Slide 77

76 Timer Comparison TIMER TIMER TIMER2 SIZE OF REGISTER 8-bits (TMR) 6-bits (TMRH:TMRL) 8-bits (TMR2) CLOCK SOURCE (Internal) Fosc/4 (instruction clock) Fosc/4 (instruction clock) Fosc/4 (instruction clock) CLOCK SOURCE (External ) TCKI pin TCKI pin or Timer oscillator (TOSC) None CLOCK SCALING AVAILABLE (Resolution) Prescaler 8-bits (:2 :256) Prescaler 3-bits (, 2, 4, 8) Prescaler (:,:4,:8) Postscaler (: :6) Interrupt Event and Flag Location On overflow FFh h (TMRIF in INTCON) On overflow FFFFh h (TMRIF in PIR) TMR2 matches PR2 (TMR2IF in PIR2) CAN WAKE PIC FROM SLEEP? NO YES NO Slide 78

77 Timer Operation DATA BUS Fosc/4 TCKI pin scaled clock synchronize TMR Watchdog Timer OPTION register prescaler WDT out PS2 PS PS TMR RATE :2 :4 RBPU INTEDG TOCS TOSE PSA PS2 PS PS :8 :6 Prescaler Rate Select Bits TMR Clock Source Select = TOCK, = Fosc/4 Source Edge Select Prescaler Assignment = prescaler assigned to WDT = prescaler assigned to Timer = increment TMR on high-to-low transition = increment TMR on low-to-high transition :32 :64 :28 :256 Slide 79

78 Timer Operation DATA BUS Fosc/4 TCKI pin scaled clock synchronize TMR Watchdog Timer prescaler WDT out If the external clock source (TOCKI) is used it will be synchronized to the internal clock Timer is readable or writeable INTCON register TMRIF Timer interrupt flag is set on TMR roll-over (FF to ) Slide 8

79 //Make sure the Timer count //register (TMR) is clear TMR = X; Timer Initialization //Disable the Timer interrupt //and clear the flag bit TIE = ; TIF = ; /*Setup the following in the OPTION_REG Timer increment from internal clock with a prescaler of :6*/ OPTION = b; /*The TMR interrupt is disabled, do polling on the Timer overflow flag bit*/ While (!TIF); <continue> TMR INTCON TMRIE OPTION_REG TMRIF TOCS Selects Timer Clock Source (External or Internal) Timer Incrementing This interrupt flag will set on Timer overflow even if interrupts are disabled PSA Prescaler Assignment (WDT or TMR) PS<2:> Prescaler value = :6 Slide 8

80 Timer Operation TOSI TOS T OSC prescaler synchronize TCKI pin Fosc/4 Timer Control Register (TCON) TMRH TGINV TMRGE TCKPS TCKPS TOSCEN TSYNC TMRCS TMRON TMRL Enable TMRON TCKPS TCKPS scale :8 :4 :2 : LP Oscillator Enable = TOSC selected = TCKI can be used Clock Source Select = External (TCKI) = Internal (F OSC /4) Timer On = Enable Timer Slide 82

81 Timer Operation TOSI TOS T OSC prescaler synchronize TCKI pin Fosc/4 Timer Control Register (TCON) TMRH TGINV TMRGE TCKPS TCKPS TOSCEN TSYNC TMRCS TMRON TMRL Enable TMRON Timer Gate Enable and Timer Gate Invert are available on some devices Timer External Clock Input Synchronization = do not synchronize external clock input = synchronize external clock input with internal clock (Fosc/4) Slide 83

82 Timer Interrupt Setup TMRH TMRL void main (void) { //Clear the Timer interrupt flag TMRIF = ; //Enable Timer interrupt TMRIE = ; Overflow sets flag and starts ISR PIR PIE //Enable Global and Peripheral Interrupts PEIE = ; GIE = ; } INTCON GIE PEIE TMRIF TMRIE Slide 84

83 Timer Initialization //Make sure the TMR registers are clear TMRH = X; TMRL = X; //Make sure the TMRIF flag in PIR //is cleared TMRF = ; /*Setup TCON register for internal clock with :8 prescaler, Timer is stopped and T osc is disabled*/ TCON = b; //Start Timer incrementing TMRON = ; TMRH //The TMR interrupt is disabled, do polling //on the TMRIF overflow bit while(!tmrif); Input clock prescale bits (TCKPS<:>) //Continue TMRL PIR (Peripheral Interrupt Request) TCON (Timer Control) TMRIF Slide 85 Timer oscillator enable bit (TOSCEN) TMRON Clock source select bit (TMRCS)

84 Timer Lab 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 86

85 Timer Lab Objective of this lab is to become familiar with the operation of Timer AND To gain experience enabling Peripheral Interrupts Slide 87

86 Lab Overview Interrupt Vector Save Context Clear IF Reload Timer Toggle LED Main Program Initialize PORTB Initialize Timer clock source and pre-scaler: Timer interrupts every, Instruction cycles 5 th Int.? YES Toggle LED 3 Restore Context NO Enable Timer, Global and Peripheral Interrupts NOP Main Loop Retfie Slide 88

87 Lab Specifics The code for the lab is in C:\RTC\MCU_2\Lab2-TMR Within LAB2-TMR.c complete the following Set Timer clock source to Fosc/4 Set Timer pre-scaler to 2 Load Timer with x3cb (65,356 5,) Start Timer Enable Timer, Global and Peripheral Interrupts Slide 89

88 What you need to know Register Operations of INTCON, TCON, TMRH, TMRL and PIE With a value of x3cb and a pre-scaler of 2, Timer will overflow every, cycles The interrupt vector code to toggle the LEDs has been provided Place Jumper J6 ON Slide 9

89 Timer Solution Slide 9

90 Question: Answer: Lab Questions Was Timer still running during the time it took to service the Interrupt? Yes Question: Answer: What effect did this have on the value to be placed to reload TMRL and TMRH? Everything to be precise the latency of reloading Timer should be considered. Slide 92

91 Timer2 Operation Fosc/4 TOUTPS3 TOUTPS2 TOUTPS TOUTPS SCALE Prescaler :, :4, :6 TMR2 :8 PR2 Timer2 Control Register (T2CON) :6 :7 :9 COMPARATOR : :2 :3 :4 :5 :6 TOUTPS3 TOUTPS2 TOUTPS TOUTPS TMR2ON T2CKPS T2CKPS : :2 :3 :4 :5 : TMR2 OUTPUT Postscaler : :6 Timer2 clock prescaler Timer2 clock postscaler T2CKPS Timer2 ON = Timer2 enabled X :6 Slide 94 T2CKPS Scale : :4

92 Timer2 Operation Fosc/4 Prescaler :, :4, :6 TMR2 Start Timer2 Counting TMR2 OUTPUT COMPARATOR Postscaler : :6 Load Period Register Timer2 Control Register (T2CON) PR2 PIR TMR2IF TOUTPS3 TOUTPS2 TOUTPS TOUTPS TMR2ON T2CKPS T2CKPS Flag set on first match with postscaler = : Timer2 ON = Timer2 enabled Slide 95

93 /*Disable the Timer2 interrupts in the PIE register. Make sure the Timer2 interrupt flag in PIR is cleared. */ TMR2IE = ; TMR2IF = ; /*Setup T2CON register for: Postscaler = :5 Prescaler = :6 Timer2 is off */ T2CON = b; //Make sure the TMR2 register is clear TMR2 = X; //Load the period register PR2 = b; //Start Timer2 incrementing TMR2ON = ; Timer2 Initialization TMR2 (Timer2 Counter) PR2 (Period Register Timer2) PIE (Peripheral Interrupt Enable) PIR (Peripheral Interrupt Request) T2CON (Timer2 Control) Flag is set Timer2 Incrementing TMR2IE TMR2IF //The Timer2 interrupt is disabled, //do polling on the interrupt flag while(!tmr2if); Postscaler = :5 (TOUTPS<3:>) TMR2ON Prescaler = :6 (T2CKPS<:>) Slide 96

94 Capture/Compare/PWM Module 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 97

95 Capture/Compare/PWM (CCP) Overview Capture Times the duration of an external event using an input CCP pin MODE Timer Resource Compare Capture Timer Changes an output pin or generates an interrupt Compare Timer when a specific amount of time has passed PWM Timer 2 Pulse Width Modulation (PWM) Creates a reconfigurable, steady duty-cycle, square wave output at a defined frequency Provides enhanced features for various bridge connectivity Slide 99

96 CCP Control Register CCP Control Register (CCPCON) PM PM CCPX CCPY CCPM3 CCPM2 CCPM CCPM CCPxM3 BIT CCPM<3:> CCP<X:Y> PM<:> CCPxM2 FUNCTION CCPxM CCPxM CCP Mode Selected CCP Mode Select Bits configure the module as Input Capture, Capture/Compare/PWM off (resets CCP module) Output Compare, or PWM PWM duty cycle 2 LSB s (8 MSB s located in CCPRL) These PWM output configuration bits are Unused available (reserved) for Enhanced CCP (ECCP) modules only. They provide Capture mode, half-bridge every falling or edge full-bridge output steering control. Unused (reserved) Compare mode, toggle output on match Capture mode, every rising edge Capture mode, every 4th rising edge Capture mode, every 6th rising edge Compare mode, set output on match Compare mode, clear output on match Compare mode, generate software interrupt on match Compare mode, trigger special event x x PWM mode Slide

97 Capture Mode CCPx Prescaler, 4, 6 Edge Detect and TMRH CCPxM3 CCPxM2 CCPxM CCPxM MODE CCPxIF in PIRx TMRL Capture every falling Single edge Buffered Capture every rising edge System Clock (Fosc) Capture every 4 th rising edge CCPRxH CCPRxL Capture every 6 th rising edge PM PM CCPX CCPY CCPM3 CCPM2 CCPM CCPM CCPxCON Slide 3

98 Capture Initialization ;Turn off CCP module CCPCON = x; ;Make sure Timer is off TMRON = ; ;Clear Timer registers TMRH = x; TMRL = x; ;Disable all interrupts for CCP CCPIF = ; CCPIE = ; ;Set CCP pin for input TRISC2 = ; CCP Pin 43 2 th rd nd st Rising Edge Detected!! ;Set Capture for every 4 th rising edge CCPCON = b ; ;Start Timer incrementing TMRON = ; ;Test the interrupt flag for capture while (!CCPIF); TMRH TMRL CCPRH CCPRL PIR CCPIF CCPCON TCON Current Timer Value TIMER INCREMENTING!! Captured! TMRON Slide 4

99 Compare Mode TMRH TMRL CCPxIF in PIRx CCPxM3 CCPxM2 CCPxM CCPxM MODE COMPARATOR Set output on match (CCPxIF is set) Does TMRH:TMRL = Clear output OUTPUT on match (CCPxIF is set) CCPRxH:CCPRxL YES Generate software LOGIC interrupt on CCPx match (CCPxIF is set CCP pin unaffected) CCPRxH?? CCPRxL NO Trigger special event (CCPxIF is set, CCP resets TMR or TMR2 and starts an A/D conversion if enabled) Special Event Trigger PM PM CCPX CCPY CCPM3 CCPM2 CCPM CCPM Slide 6

100 Compare Initialization //Turn off the CCP module CCPCON = x; //Turn off Timer TMRON = ; //Clear Timer result registers TMRH = x; TMRL = x; //Disable CCP interrupt and make sure //its flag is clear CCPIE = ; CCPIF = ; //Make CCP pin output TRISC2 = ; //Initialize Compare to set output on match CCPCON = b; //Load compare value into CCPRH:CCPRL CCPRH = b; CCPRL = x; //Start Timer incrementing TMRON = ; //Test CCPIF for Timer match with CCPRx While (!CCPIF) TMRH TMRL CCPRH CCPRL TCON CCPCON PIR TMRON CCPIF Slide 7

101 PWM Mode Generates a Pulse-Width Modulated (PWM) signal on the CCP and CCP2 pins Duty cycle, period and resolution determined by the following registers Register PR2 T2CON CCPRxL CCPxCON Description Period Register Timer2 Control Duty Cycle Register CCP Control Register Slide 8

102 PWM Operation CCPRL CCPRH TMR2 COMPARATOR 8 CCPX:CCPY bits in CCPCON Period Start R Latch S CCP Output Pin CCP pin COMPARATOR PR2 8 TMR2 Reset to s Determines Period TMR2 is concatenated with 2 bits from F OSC, or 2 bits from Prescaler to create a bit time base Slide 9

103 PWM Operation CCPRL CCPRH TMR2 Determines Duty Cycle Double Buffer COMPARATOR COMPARATOR PR2 8 8 CCPX:CCPY bits in CCPCON Period Start R Latch S CCP Output Pin CCP pin TMR2 is concatenated with 2 bits from F OSC, or 2 bits from Prescaler to create a bit time base Slide

104 PWM Operation CCPRL CCPRH TMR2 COMPARATOR COMPARATOR PR2 8 8 CCPX:CCPY bits in CCPCON R Latch S Period Period Start CCP Output Pin CCP pin TMR2 is concatenated with 2 bits from F OSC, or 2 bits from Prescaler to create a bit time base Slide

105 PWM Operation CCPRL CCPRH TMR2 Determines Duty Cycle Double Buffer COMPARATOR 8 CCPX:CCPY bits in CCPCON Period Start R Latch S Period CCP Output Pin CCP pin Period 2 COMPARATOR PR2 8 TMR2 Reset to s TMR2 is concatenated with 2 bits from F OSC, or 2 bits from Prescaler to create a bit time base Slide 2

106 //Turn off CCP pin by making it an input TRISC2 = ; //Turn off Timer2 TMR2ON = ; //Clear Timer2 TMR2 = x; PWM Initialization //Set up Period and Duty Cycle PR2 = b; //Load a Period Value CCPRL = b; //Load a Duty Cycle Value //Configure CCP module for PWM // and LSB s of Duty Cycle = b CCPCON = b; //Turn CCP pin back on (make it an output) TRISC2 = ; //Start the PWM by turning on Timer2 //Configure Prescaler and Postscaler to :) T2CON = b; TMR2 PR2 CCPRL CCPCON T2CON duty cycle LSBs DCB<:> PWM Mode CCPM <3:> Prescaler bits TOUTPS<3:> TMR2ON Prescaler bits T2CKPS<:> Slide 3

107 Pulse Width Modulation (PWM) Lab 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 4

108 PWM Lab Objectives Become familiar with the CCP module configuration and operation in PWM mode Gain additional exposure to Timer2 configuration Slide 5

109 PWM Lab Overview The PWM waveform is output on the CCP pin (RC2) that will emit a tone on the PICdem2 plus onboard buzzer. When the lab is completed, a 5% duty cycle at a period of 256/(Fosc/4) will drive the buzzer Slide 6

110 PWM Lab Overview Main Code Load PR2 value Set up RC2 as output pin Load CCPRL for 5% duty cycle Configure CCP as 8-bit PWM Turn on Timer2 w/ : pre scaler NOP Slide 7

111 PWM Lab Specifics Code for the lab is in C:\RTC\MCU_2\Lab4-PWM Complete the following sections Configure PORTC pin 2 ( CCP) as an output Set CCP in PWM mode Clear CCPX and CCPY (8-bit PWM) Configure Timer2 with : pre-scaler Slide 8

112 What you need to know The code to load PR2 (Timer2) and to set a 5% duty cycle has been provided. These values can be seen in the code The CCP pin is RC2 (Pin 2 of PORTC) on the PIC6F877 Registers needed to complete this lab are: TRISC T2CON CCPCON Slide 9

113 PWM Lab Solution Slide 2

114 PWM Lab Questions Question: Why didn t we have to enable the interrupts for the PWM to work? Answer: PWM will run concurrently with the PICmicro MCU without slowing the processor down Slide 2

115 Comparators 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 22

116 Comparator Overview Comparator Module: Compares analog input voltage to a reference and outputs a digital result Vref Analog Input (Vin) Reference Voltage (Vref) Vin + Vout Comp - Output (Vout) Slide 23

117 Comparator Reference Voltage Voltage Reference can be either: External from a device pin Internally generated with the Voltage Reference Module Provides 6 selectable voltages from to 75% of VDD Some devices can also scale V REF+ and V REF- Some devices also have a fixed reference (.6V) Independent of VDD V REF+ VRSS = 8R R R R R VRR VRSS = V DD CV REF 5 8R To Comparators and ADC Module CV REF VROE VREN 4 VR<3:> VRSS = VRSS = V REF- Slide 24

118 Comparator Interrupts An Interrupt occurs when the comparator output changes Some devices share one flag for both comparators Some devices have independent flags Must read the comparator output before clearing interrupt flags Outputs found in the comparator control register (CMCON or CMxCON Slide 25

119 Comparators and Sleep Mode Comparators remain active in Sleep A Comparator output change will wake-up core After wake-up, the instruction following the SLEEP instruction or an Interrupt Service Routine (ISR) is executed Slide 26

120 Analog-to-Digital Converter (ADC) 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 27

121 ADC Overview Analog-to-Digital Converter Module Converts analog input signal into an 8 or -bit binary value Selectable internal or external reference voltage Interrupt can be generated after conversion is completed The interrupt can wake the PICmicro from SLEEP Analog Input ADC Digital Output Slide 28

122 ADC Control Registers The ADC implements two control ADCON registers ADCON and ADCON F OSC/2 Devices with > 8 analog inputs do not have same bits shown below ADC Control Register (ADCON) ADCS ADCS CHS2 CHS CHS GO/DONE ADON BIT ADCS:ADCS <ADCS2> FUNCTION F OSC to T AD Conversion Select bits Use with ADCS2 in ADCON ADCON <ADCS:ADSC> F OSC to T AD Clock Conversion F OSC/8 F OSC/32 FRC (ADC RC Osc) F OSC/4 F OSC/6 F OSC/64 FRC (ADC RC Osc) CHS2:CHS GO/DONE ADON Analog Channel Select bits = A/D Conversion in progress = A/D Conversion is completed Enables the ADC module Slide 3

123 ADC Control Registers The ADC implements two control registers ADCON and ADCON Devices with > 8 analog inputs do not have same bits shown below ADC Control Register (ADCON) ADFM ADCS2 PCFG3 PCFG2 PCFG PCFG BIT ADFM ADCS2 PCFG<3:> FUNCTION ADC Result Registers Format bit = Right Justified, = Left Justified F OSC to T AD Conversion Select bit Use with ADCS<:> in ADCON Port Configuration Bits Configures I/O as analog or digital Slide 3

124 ADC Result Registers bit ADC result in is placed in two registers ADRESH and ADRESL Left or Right Justified Determined by Format Select bit (ADFM) in ADCON register ADRESH MSB ADRESL LSB Left Justified (ADFM = ) ADRESH MSB ADRESL LSB Right Justified (ADFM = ) Slide 32

125 ADC Operation PCFG <3:> F OSC AN7 AN6 AN5 AN4 Conversion clock scaler AN3 AN2 AN Vdd AN AN AN AN2 AN3 AN4 AN5 AN6 AN7 F OSC to T AD Conversion ADCON Holding Capacitor ADCS ADCS CHS2 CHS CHS GO/DONE ADON ADCON ADFM ADCS2 PCFG3 PCFG2 PCFG PCFG ADFM Channel Select V REF+ pin ADRESH ADRESL Left Justified Right Justified V REFpin Slide 34 T AD Start Conversion Complete GO/DONE ADC Vss Port Config Bits

126 Input Signal Acquisition Time Acquisition Time Conversion Time time (ADRESH : ADRESL) VC VIN ADC Acquisition Time allows Hold Capacitor to fully charge to VIN SOURCE time RS < k CHOLD 2pF + VC - V REF- or VSS Acquisition Time is determined by Pin Capacitance and Source impedance (recommend <k ) V Slide 35

127 Conversion Time (ADRESH : ADRESL) ADC Result VC Acquisition Time Acquisition Conversion Time time VIN time ADC Conversion Clock cycles (TAD) ADC time CHOLD 2pF + VC - V REF- or VSS Slide 36

128 ADC Lab Question Question: Instead of waiting for TMR2IF to be set in the main program, could we start the ADC from within an interrupt routine? Answer: YES Slide 37

129 Midrange Peripherals Wrap Up 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 57

130 Peripherals Class Wrap-up We created a C-project in MPLAB that used HITECH s PICC Lite compiler We learned the following peripherals: I/O ports Interrupt structure and processing Timers (Timer, Timer, Timer2) CCP Module ( Output Compare, Input Capture, PWM) Comparators and Analog-to-Digital Converters Voltage Reference AUSART Serial Port I 2 C using the MSSP module Slide 58

131 Resources Visit and follow the links for: 24/7 technical support Application Notes Web Seminars Code examples Datasheets and Much More! Slide 6

132 Thank You!! 26 Microchip Technology Incorporated. All Rights Reserved. 2ASP Rev. January Slide 28 6

133 Trademarks The Microchip name and logo, the Microchip logo, Accuron, dspic, KeeLoq, microid, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfpic and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dspicdem, dspicdem.net, dspicworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In- Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rflab, rfpicdem, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. Slide 62