MEMORY RAS CONFIGURATION

Transcription

1 MEMORY RAS CONFIGURATION USER'S GUIDE Revisio 1.0

2 The iformatio i this User s Maual has bee carefully reviewed ad is believed to be accurate. The vedor assumes o resposibility for ay iaccuracies that may be cotaied i this documet, ad makes o commitmet to update or to keep curret the iformatio i this maual, or to otify ay perso or orgaizatio of the updates. Please Note: For the most up-to-date versio of this maual, please see our website at Super Micro Computer, Ic. ("Supermicro") reserves the right to make chages to the product described i this maual at ay time ad without otice. This product, icludig software ad documetatio, is the property of Supermicro ad/ or its licesors, ad is supplied oly uder a licese. Ay use or reproductio of this product is ot allowed, except as expressly permitted by the terms of said licese. IN NO EVENT WILL Super Micro Computer, Ic. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA. Ay disputes arisig betwee maufacturer ad customer shall be govered by the laws of Sata Clara Couty i the State of Califoria, USA. The State of Califoria, Couty of Sata Clara shall be the exclusive veue for the resolutio of ay such disputes. Supermicro's total liability for all claims will ot exceed the price paid for the hardware product. FCC Statemet: This equipmet has bee tested ad foud to comply with the limits for a Class A digital device pursuat to Part 15 of the FCC Rules. These limits are desiged to provide reasoable protectio agaist harmful iterferece whe the equipmet is operated i a commercial eviromet. This equipmet geerates, uses, ad ca radiate radio frequecy eergy ad, if ot istalled ad used i accordace with the maufacturer s istructio maual, may cause harmful iterferece with radio commuicatios. Operatio of this equipmet i a residetial area is likely to cause harmful iterferece, i which case you will be required to correct the iterferece at your ow expese. Califoria Best Maagemet Practices Regulatios for Perchlorate Materials: This Perchlorate warig applies oly to products cotaiig CR (Magaese Dioxide) Lithium coi cells. Perchlorate Material-special hadlig may apply. See WARNING: Hadlig of lead solder materials used i this product may expose you to lead, a chemical kow to the State of Califoria to cause birth defects ad other reproductive harm. The products sold by Supermicro are ot iteded for ad will ot be used i life support systems, medical equipmet, uclear facilities or systems, aircraft, aircraft devices, aircraft/emergecy commuicatio devices or other critical systems whose failure to perform be reasoably expected to result i sigifi cat ijury or loss of life or catastrophic property damage. Accordigly, Supermicro disclaims ay ad all liability, ad should buyer use or sell such products for use i such ultra-hazardous applicatios, it does so etirely at its ow risk. Furthermore, buyer agrees to fully idemify, defed ad hold Supermicro harmless for ad agaist ay ad all claims, demads, actios, litigatio, ad proceedigs of ay kid arisig out of or related to such ultra-hazardous use or sale. Maual Revisio 1.0 Release Date: December 22, 2017 Uless you request ad receive writte permissio from Super Micro Computer, Ic., you may ot copy ay part of this documet. Iformatio i this documet is subject to chage without otice. Other products ad compaies referred to herei are trademarks or registered trademarks of their respective compaies or mark holders. Copyright 2017 by Super Micro Computer, Ic. All rights reserved. Prited i the Uited States of America

3 Memory RAS Cofi guratio Chapter 1 Itroductio About This User Guide This user's guide is writte for system itegrators, IT techicias, ad kowledgeable ed users. It provides iformatio o memory RAS support ad cofi guratio o a Supermicro motherboard or system. Itroductio to Reliability, Availability ad Serviceability Reliability, Availability, ad Serviceability (RAS) is a computer-egieerig architecture that promotes reliability egieerig, high availability, ad serviceability desig. For product reliability, computer compoets or systems are desiged to maitai cosistet performace based o the specifi catios without deviatios or errors. For system availability, a compoet or server will always fuctio as it should, ad it will also be costatly available for use with miimal dowtime. For computer serviceability, a compoet or a system ca be maitaied or repaired with ease. With full implemetatio of RAS ito our product desig ad system itegratio, Supermicro's computer systems are egieered to provide you with the highest stadards i quality, performace, availability, ad usability at all times. Itroductio to Memory RAS Cofiguratio As a world's server maufacturer leader, Supermicro has itegrated memory RAS features ito our products to ehace data itegrity ad system performace ad to prevet data alteratio or data loss caused by electroic trasactios for may years. Additioally, we've also built i layers of data-checkig, error-detectio, ad error-correctio mechaisms for memory error recovery to maximize storage ad etwork security. The memory RAS capabilities that have bee implemeted ito our products iclude memory mirrorig, ehaced Error Checkig ad Correctio (ECC), memory scrubbig, ad memory sparig. I additio to these highly effi ciet memory protectio mechaisms that are embedded i the itegrated memory cotrollers of Supermicro computers, we've utilized the latest techology available i the idustry to further ehace data itegrity ad system security for our systems. These ew advaced RAS features iclude: SDDC: Sigle Device Data Correctio SDDC+1: SDDC_Plus_Oe DDDC: Double Device Data Correctio ADDDC: Adaptive Double Device Data Correctio 3

4 Super Memory RAS Cofi guratio User's Guide Cotactig Supermicro Headquarters Address: Super Micro Computer, Ic. 980 Rock Ave. Sa Jose, CA U.S.A. Tel: +1 (408) Fax: +1 (408) (Geeral Iformatio) (Techical Support) Website: Europe Address: Super Micro Computer B.V. Het Sterrebeeld 28, 5215 ML 's-hertogebosch, The Netherlads Tel: +31 (0) Fax: +31 (0) (Geeral Iformatio) (Techical Support) (Customer Support) Website: Asia-Pacific Address: Super Micro Computer, Ic. 3F, No. 150, Jia 1st Rd. Zhoghe Dist., New Taipei City 235 Taiwa (R.O.C) Tel: +886-(2) Fax: +886-(2) Website: 4

5 Memory RAS Cofi guratio Table of Cotets Chapter 1 Itroductio Chapter 2 Itel ECC Mode Commo Techology SDDC...6 SDDC DDDC...8 DDDC ADDDC...9 ADDDC+1 (Adaptive Double Device Data Correctio Plus Oe)...9 ADDDC (Adaptive Double Device Correctio) Bak...10 ADDDC (Adaptive Double Device Correctio) Rak...11 Physical/Logical DRAM Map, Rak VLS...12 Memory RAS DIMM Limitatio...12 Chapter 3 Cofigurig Memory RAS Features i the BIOS Setup Utility 5

6 Super Memory RAS Cofi guratio User's Guide Chapter 2 Itel ECC Mode Commo Techology SDDC Sigle Device Data Correctio (SDDC) checks ad corrects sigle-bit or multiple-bit (4-bit max.) memory faults that affect a etire sigle x4 DRAM device. SDDC Algorithm Overview (1 of 3) Memory Write with CRC ad Parity bits ecodig ½ Cache Lie = 256 bits = 32B Geerate CRC-16 Polyomial imc 256 bits +16 Bits CRC = 272 bits (34B) Geerate Eve Parity 16 bits 272 bits +16 Parity = 288 bits (36B) CRC Parity = 576 (Full Cachelie + CRC + Parity) 8 bursts each with 72b (576b per chael) 4 DCLKs X4 Burst7 Burst6 Burst5 Burst4 Burst3 18 Devices X4 Burst7 Burst6 Burst5 Burst4 Burst3 1Rx4 RDIMM 18 Devices P C D14 D15 D12 D13 D10 D11 D8 D9 D6 D7 D4 D5 D2 D3 D1 Burst2 Burst1 Burst0 Burst2 Burst1 Burst0 6

7 Memory RAS Cofi guratio SDDC + 1 SDDC+1, which is the ehaced feature to SDDC, will spare the faulty DRAM device out after a SDDC evet has occurred. After the evet, the SDDC+1 ECC mode is activated to protect agaist ay additioal memory failure caused by a sigle-bit error i the same memory rak. SDDC+1 Algorithm with Device Taggig 1. Before Device Taggig 1. Normal Memory Write/Read P C D14 D15 D12 D13 D10 D11 D8 D9 D6 D7 D4 D5 D2 D3 D1 2. Example: Device hard failure. 1. Corrected Error Cout would reach threshold quickly. Write Trasactio: Normal Read Trasactio: Normal 2. BIOS/SMM detects the failed DRAM Device. Triggers Device Taggig. After Device Taggig imc After Device Taggig P C D14 D12 D10 D15 D13 D11 Write Trasactio: Normal D8 D9 D6 D7 D4 D5 D2 D3 D1 Read Trasactio: Replace bits With Parity-device bits device data is replaced with that of Parity Device. 2. imc does ormal error Checkig. 3. Itel Xeo Scable Processor Family: error, logs error ad sigal MCE. imc 7

8 Super Memory RAS Cofi guratio User's Guide DDDC Double Device Data Correctio (DDDC) provides error checkig ad correctio to protect agaist memory failures occurred to two, sequetial, ad x4 DRAM devices due to harderrors o DIMM modules. DDDC is supported oly with x4 DRAMs ad with two chaels i the lockstep mode. (This feature is ot supported for x8 DRAM device-based DIMM.) Memory DDDC+1 Algorithm Overview (2 of 3) Normal Write/Read Operatio 1. Normal Memory Write/Read CRC Spare device Parity JC Buffer CH0 CH1 C0 D14 D12 D10 C1 D15 D13 D11 S P D30 D28 D26 D31 D29 D27 D8 D9 D6 D7 D4 D5 D2 D3 D24 D22 D20 D18 D25 D23 D21 D19 Memory DDDC Device S arig Operatio D1 D16 D17 2. Example: Device hard failure. 1. Corrected Error Cout would reach threshold quickly. SMI is triggered. 2. BIOS/SMM detects the failed DRAM Device. Triggers DDDC Device Sparig evet. JC Buffer CH0 CH1 C0 C1 P D14 D12 D15 D13 D30 D28 D31 D29 D10 D11 D26 D27 D8 D9 D6 D7 D24 D22 D25 D23 D4 D5 D20 D21 D2 D3 D18 D19 D1 D16 D17 3. DDDC Device Sparig Egie copies data from to spare device. SMI is triggered upo completio. After DDDC Device Sparig Memory write / read after DDDC Device Sparig JC Buffer CH0 CH1 C0 D14 D12 D10 C1 D15 D13 D11 P D30 D28 D26 D31 D29 D27 D8 D9 D6 D7 D4 D5 D2 D3 D1 D24 D22 D20 D18 D16 D25 D23 D21 D19 D17 1. imc disable ay further DDDC device sparig evet.. 2. Normal Memory Write/Read operatios always use Spare device istead of Device. 8

9 Memory RAS Cofi guratio DDDC+1 Double Device Data Correctio (DDDC) Plus Oe allows the error correctio code to correct a error caused by the failure of two DRAM devices or by a sigle-bit error that is beyod a device failure i the lockstep mode. Memory DDDC+1 Algorithm Overview (3 of 3) Memory write/read after DDC Device Sparig JC Buffer CH0 CH1 Memory Write/Read after DDDC Device Sparig ad Device Taggig JC Buffer CH0 CH1 C0 D14 D12 D10 C1 D15 D13 D11 P C0 D14 D12 D10 C1 D15 D13 D11 P D30 D28 D26 D31 D29 D27 D30 D28 D26 D31 D29 D27 D8 D9 D8 D9 D6 D7 D6 D7 D4 D5 D4 D5 D2 D3 D2 D3 D1 D24 D22 D20 D18 D16 D25 D23 D21 D19 D17 D1 D24 D22 D20 D18 D16 D25 D23 D21 D19 D17 1. Normal Memory Write/Read with Spare Device as. 2. Example: Device D1 hard failure (secod device). 1. Corrected Error Cout would reach threshold quickly. 2. BIOS/SMM detects the failed DRAM Device D1. Triggers Device Taggig. After DDDC Device Sparig Memory Write operatio: Uchaged. Still usig spare device. Memory read operatio: D1 device data is replaced with that of Parity Device. imc does ormal error checkig. Upo detectig error, logs error ad corrects SBE. I case of MBE, logs error ad sigal MCE. ADDDC Adaptive Double Device Data Correctio (ADDDC), which is a ehaced feature to DDDC, will ot issue a performace pealty before a device fails. Please ote that virtual lockstep mode will oly start to work for ADDDC after a faulty DRAM module is spared out at Bak or Rak graularity. ADDDC+1 (Adaptive Double Device Data Correctio Plus Oe) Adaptive Double Device Data Correctio Plus Oe (ADDDC+1), which is a improved feature of ADDDC, will allow the error correctio code to correct a error caused by the failure of two DRAM devices or by a sigle-bit error that is beyod a device failure i the lockstep mode. ADDDC+1 will ot issue a performace pealty before a device fails. Please ote that virtual lockstep mode will oly start to work for ADDDC after a faulty DRAM module is spared out at Bak graularity or Rak graularity. 9

10 Super Memory RAS Cofi guratio User's Guide ADDDC (Adaptive Double Device Correctio) Bak If ADDDC Bak is implemeted, a memory failure will oly occur to a DRAM bak ad will ot occur to the whole device because a bak graularity of a DRAM regio will eter ito virtual lockstep (VLS) alog with a buddy bak, allowig the cotet of the bak of a failig DRAM device to be copied over to the bak of the spare buddy device as soo as a error occurs to a good DIMM. Adaptive DDDC (MR), Bak Virtual lockstep First Strike Rak A, Device 0, Bak 0 Rak A B a k I D 0 1 X4 Device ID Actio: VLS the failed Bak, map out Device 0, Bak 0 by copyig Cotet to bak 0 i spare DRAM Device. Rak A X4 Device ID Rak B X4 Device ID B a k I D

11 Memory RAS Cofi guratio ADDDC (Adaptive Double Device Correctio) Rak If ADDDC Rak is implemeted, device sparig at a rak graularity will be eabled to allow the cotet of the whole DRAM device to be copied to a spare device whe a secod saved DRAM device istalled i aother bak of the same memory chael fails. Adaptive DDDC (MR), Secod Strike Rak A Secod Strike Rak A, Device 0, Bak 1 Rak A X4 Device ID Rak B X4 Device ID B a k I D A 1 Actio: Upgrade Bak to Rak VLS. (reverse VLS, Re do Rak A VLS. Device 0 all Baks is ow copied over to spare DRAM Device) Rak A X4 Device ID Rak B X4 Device ID B a k I D SDDC + 1 SDDC + 1 will occur if ADDDC spare is eabled i the BIOS meu. This will oly happe whe aother sigle device failure occurs after a "ADDDC Rak' evet, ad the curret ECC mode ca correct a additioal sigle bit error after SDDC spare is completed; SDDC + 1 will occur if ADDDC spare is disabled, SDDC plus oe is eabled i the BIOS meu, ad VLS is disabled. This mode is eabled after a sigle DRAM device failure has occurred ad the process of 'device spare' is completed. It ca correct a additioal sigle bit error i the ECC mode. SDDC + 1 will occur whe a correctable memory error withi oe DRAM device bak exceeds the threshold, ad ADDDC Bak Virtual Lock Step is active. Subsequetly, a correctable memory error i ay other bak will trigger "ADDDC Rak Virtual Lock Step", ad it will trigger SDDC+1 i ay other DRAM device as well. 11

12 Super Memory RAS Cofi guratio User's Guide Physical/Logical DRAM Map, Rak VLS Physical/logical DRAM Map, Rak VLS Logical DRAM Physical DRAM Logical DRAM Bak Bak Lower half cache lie 1S-LH 1s- Upper half cache UH lie P L 18 0 P+L 18 Lower half cache mapped lie out Upper half cache lie NF- UH NF- LH 3 Rak A N Lower half cache lie Upper half cache lie Rak 18 B N 18 Post Rak VLS: DRAM 0 is mapped out, Rak B device 17 holds Data Parity+Locator is combied ito Device 16. Memory RAS DIMM Limitatio Memory RAS DIMM Limitatio DRAM Type x4 DRAM DIMMS x8 DRAM DIMM SDDC(+1) Support Support (Note *1) ADDDC(+1) Support Not Support Note 1: x8 Sigle Device Data Correctio (SDDC) ad SDDC+1 are supported oly via 'static virtual lockstep'. Please be sure to eable Static Virtual Lockstep Mode i the BIOS setup utility. Please be sure to istall at least oe x8dimm module with two logical RANKs or two x8 DIMM modules with a sigle RANK each i a DDR chael. Note 2: SDDC (+1) ad ADDDC (+1) are ot compatible with Mirrorig ad Rak Sparig. Whe Mirror or Rak Sparig is eabled, either ADDDC or SDDC will ot be supported. 12

13 Chapter 3 Cofigurig Memory RAS Features i the BIOS Setup Utility To cofi gure the SDDC+1/ADDDC RAS settigs i the BIOS, follow the istructios below: 1. Power o your computer ad hit the <Delete> key cotiuously to eter the BIOS setup utility upo bootup as the scree show below. 2. Usig the arrow keys, select the <Advaced> meu o the top of the scree ad hit <Eter> to eter the Advaced submeu. 13

14 3. Usig the dow arrow key, scroll dow to select the Chipset Cofi guratio submeu ad hit <Eter> as show below. 4. Select North Bridge ad hit <Eter>. The followig scree will display. 14

15 5. Use the arrow key to select Memory Cofi guratio ad hit <Eter>. The followig scree will display. 6. Usig the dow arrow key, scroll dow to select Memory RAS Cofi guratio from the scree above ad hit <Eter>. The followig scree will display: 15

16 7. Select SDDC Plus Oe ad hit <Eter>. The optios for SDDC Plus Oe will display as show below. Usig the arrow keys select Eable ad hit <Eter>. 8. Scroll dow to ADDDC Sparig ad hit <Eter>. Select Eable ad hit <Eter> as show below. 16

17 9. Oce you've set both items: SDDC Plus Oe ad ADDDC Sparig to Eable, press the <F4> key o the top of your keyboard to save your cofi guratio settigs ad exit the BIOS setup utility as show below. 10. Reboot your system for the ew cofi guratio settigs to take effect. 17