Unit I. Introduction Microcontrollers and Embedded processors Overview of the 8051 Inside the 8051 Addressing Modes
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1 Unit I Introduction Microcontrollers and Embedded processors Overview of the 8051 Inside the 8051 Addressing Modes
2 Basic Introduction
3 Basic Introduction (contd.)
4 Basic Introduction (contd.)
5 Microcontroller and embedded processors (Difference between Microprocessor and microcontroller (contd.))
6 Microcontroller and embedded processors (Difference between Microprocessor and microcontroller (contd.))
7 Microcontroller and embedded processors (A Brief about embedded system) What is Embedded System? An embedded system is closely integrated with the main system It may not interact directly with the environment For example A microcomputer in a car ignition control An embedded product uses a microprocessor or microcontroller to do one task only There is only one application software that is typically burned into ROM
8 Microcontroller and embedded processors (A Brief about embedded system (contd.))
9 Microcontroller and embedded processors (Three criteria in Choosing a Microcontroller) meeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit availability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support wide availability and reliable sources of the microcontrollers
10 Overview of 8051 (8051 Basic Component) Intel Introduced 8051, reffered as MCS-51, in K bytes internal ROM 128 bytes internal RAM Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters One serial interface 8051 by other manufacturers are code compatible CPU I/O Port RAM Timer ROM Serial COM Port A single chip Microcontroller
11 Overview of 8051 (Other 8051 features) only 1 On chip oscillator (external crystal) 6 interrupt sources (2 external, 3 internal, Reset) 64K external code (program) memory(only read)psen 64K external data memory(can be read and write) by RD,WR Code memory is selectable by EA (internal or external) We may have External memory as data and code Full duplex serial data transmitter/receiver 4 Register banks and 8 bit program status word and stack pointer Direct bit and byte addressability Interrupt structure with two priority levels Signed overflow detection and parity computation Integrated boolean processor for control applications Full depth stack for subroutine return linkage and data storage.
12 Chapter 2 1. Inside the Addressing Modes
13 1.2.1 Inside the 8051
14 Inside the 8051(contd.)
15 Inside the 8051(contd.)
16 Inside the 8051(contd.)
17 Inside the 8051(contd.)
18 Inside the 8051(contd.)
19 Inside the 8051(contd.)
20 Addressing Modes
21 Addressing Modes (Immediate addressing mode)
22 Addressing Modes (Immediate addressing mode (contd.))
23 Addressing Modes (Register addressing mode)
24 Addressing Modes (Accessing Memory Direct addressing mode)
25 Addressing Modes (Accessing Memory SFR Registers and Their Addresses)
26 Addressing Modes (Accessing Memory SFR Registers and Their Addresses (contd.))
27 Addressing Modes (Accessing Memory SFR Registers and Their Addresses (contd.))
28 Addressing Modes (Accessing Memory SFR Registers and Their Addresses (contd.)) Example:-
29 Addressing Modes (Accessing Memory Stack & Direct addressing mode)
30 Addressing Modes (Accessing Memory Register Indirect addressing mode)
31 Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.)) Advantage of register indirect addressing mode:-
32 Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.))
33 Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.))
34 Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.)) Limitation of register indirect addressing mode:-
35 Addressing Modes (Accessing Memory Indexed addressing mode and on chip ROM access)
36 Addressing Modes (Accessing Memory Indexed addressing mode and on chip ROM access (contd.))
37 Addressing Modes (Accessing Memory Indexed addressing mode and on chip ROM access (contd.))
38 Unit - II Introduction to 8051 assembly programming Assembling and running an 8051 program The program counter and ROM space in the data types and directives 8051 flag bits and the PSW register 8051 register banks and stack Bit addressability Jump loop and call instructions 8051 I/O programming I/O bit manipulation programming
39 Chapter Introduction to 8051 assembly programming 2. Assembling and running an 8051 program 3. The program counter and ROM space in the 8051
40 Introduction to 8051 assembly programming
41 Introduction to 8051 assembly programming (contd.)
42 Introduction to 8051 assembly programming (contd.)
43 Assembling and running an 8051 program
44 Assembling and running an 8051 program (contd.)
45 Assembling and running an 8051 program (contd.)
46 2.1.2 Assembling and running an 8051 program (contd.) (Steps to create a program)
47 Assembling and running an 8051 program (contd.)
48 The program counter and ROM space in the 8051
49 The program counter and ROM space in the 8051 (contd.) Power Up : -
50 The program counter and ROM space in the 8051 (contd.) Placing code in ROM
51 The program counter and ROM space in the 8051 (contd.) Placing code in ROM (contd.)
52 The program counter and ROM space in the 8051 (contd.) Executing Program
53 The program counter and ROM space in the 8051 (contd.) Executing Program (contd.)
54 The program counter and ROM space in the 8051 (contd.) ROM memory map in 8051 family
55 Chapter data types and directives flag bits and the PSW register register banks and stack
56 data types and directives
57 data types and directives (contd.)
58 data types and directives (contd.)
59 data types and directives (contd.)
60 data types and directives (contd.)
61 flag bits and the PSW register
62 flag bits and the PSW register (contd.)
63 flag bits and the PSW register (contd.)
64 flag bits and the PSW register (contd.)
65 flag bits and the PSW register (contd.)
66 flag bits and the PSW register (contd.)
67 register banks and stack
68 register banks and stack (contd.)
69 register banks and stack (contd.)
70 register banks and stack (contd.)
71 register banks and stack (contd.)
72 register banks and stack (contd.)
73 register banks and stack (contd.) Stack
74 register banks and stack (contd.) Stack
75 register banks and stack (contd.) Stack
76 register banks and stack (contd.) Stack
77 register banks and stack (contd.) Stack
78 register banks and stack (contd.) Stack
79 register banks and stack (contd.) Stack
80 register banks and stack (contd.) Stack
81 Addressing Modes (contd.) Accessing Memory Indexed addressing mode and on chip ROM access Continued from Unit 1
82 Addressing Modes (contd.) Accessing Memory Indexed addressing mode and on chip ROM access Continued from Unit 1
83 Addressing Modes (contd.) Accessing Memory Indexed addressing mode and on chip ROM access Continued from Unit 1
84 Chapter - 3 1) Bit addressability 2) Jump loop and call Instruction 3) 8051 I/O programming 4) I/O bit manipulation programming
85 Bit Addressability
86 Bit Addressability
87 Bit Addressability (contd.)
88 Bit Addressability (contd.)
89 Bit Addressability (contd.)
90 Bit Addressability (contd.)
91 Bit Addressability (contd.)
92 Bit Addressability (contd.)
93 Bit Addressability (contd.)
94 Bit Addressability (contd.)
95 Bit Addressability (contd.)
96 Bit Addressability (contd.)
97 Bit Addressability (contd.)
98 Jump, Loop and Call Instructions
99 Loop: Jump, Loop and Call Instructions
100 Jump, Loop and Call Instructions (contd.) Nested Loop:-
101 Jump, Loop and Call Instructions (contd.) Conditional Jump:-
102 Jump, Loop and Call Instructions (contd.) Conditional Jump (contd.):-
103 Jump, Loop and Call Instructions (contd.) Conditional Jump (contd.):-
104 Jump, Loop and Call Instructions (contd.) Unconditional Jump:-
105 Jump, Loop and Call Instructions (contd.) Unconditional Jump (contd.):- [Calculating Short Jump Address]
106 Jump, Loop and Call Instructions (contd.) Unconditional Jump (contd.):- [Calculating Short Jump Address]
107 Jump, Loop and Call Instructions (contd.) Call Instruction:-
108 Jump, Loop and Call Instructions (contd.) Call Instruction (LCALL):-
109 Jump, Loop and Call Instructions (contd.) Call Instruction-LCALL (contd.):-
110 Jump, Loop and Call Instructions (contd.) Call Instruction and Stack:-
111 Jump, Loop and Call Instructions (contd.) Call Instruction and Stack Use PUSH/POP in subroutine:-
112 Jump, Loop and Call Instructions (contd.) Call Instruction and Stack calling subroutine:-
113 Jump, Loop and Call Instructions (contd.) Call Instruction ACALL:-
114 Jump, Loop and Call Instructions (contd.) Call Instruction ACALL (contd.):-
115 Jump, Loop and Call Instructions (contd.) Time Delay:-
116 Time Delay (contd.): Jump, Loop and Call Instructions (contd.)
117 Jump, Loop and Call Instructions (contd.) Time Delay Calculation:-
118 Jump, Loop and Call Instructions (contd.) Time Delay Calculation increase delay using NOP:-
119 Jump, Loop and Call Instructions (contd.) Time Delay Calculation Large delay using nested loop:-
120 Jump, Loop and Call Instructions (contd.) Time Delay Calculation For other 8051 chips:-
121 Jump, Loop and Call Instructions (contd.) Time Delay Calculation For other 8051 chips (contd.):-
122 Jump, Loop and Call Instructions (contd.) Time Delay Calculation For other 8051 chips (contd.):-
123 I/O Programming
124 I/O Programming (contd.): 8051 Foot Print P1.0 P1.1 P1.2 P1.3 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031) (8751) (8951)
125 I/O Programming (contd.):
126 I/O Programming (contd.):
127 I/O Programming (contd.):
128 I/O Programming (contd.):
129 I/O Programming (contd.):
130 I/O Programming (contd.):
131 I/O Programming (contd.):
132 I/O Bit Manipulation Programming
133 I/O Bit Manipulation Programming
134
135
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