What is "Computer Architecture" ECE 4680 Computer Architecture and Organization. Lecture 1: A Short Journey to the World of Computer Architecture

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1 ece4680 Lect Intro. February 6, 2002 What i "Computer Architecture" ECE 4680 Computer Architecture and Organization Lecture : A Short Journey to the World of Computer Architecture Baic Idea and Definition Major Component of Software/Hardware Computer Revolution Co-ordination of level of abtraction Application Compiler Intr. Set Proc. Operating Sytem Digital Deign Circuit Deign I/O ytem Merit of Abtraction/Layer/Hierarchy Intruction Set Architecture Under a et of rapidly changing Force : technology, application, ming Language, operating ytem, hitory ece4680 Lect Intro.2 February 6, 2002 Technology Trend: Clock rate Technology Trend: Tranitor Count Growth Clock rate (MHz),000 R00 Pentium 0 i8086 i80286 i80386 i8080 i8008 i % per year ---> today PC i yeterday Supercomputer Tranitor,000,000 0,000,000,000,000,000 i80286 R00 Pentium i80386 R3000 R2000 i8086 0,000 i8080 i8008 i4004, % per year, order of magnitude more contribution in 2 decade - More and more function can be performed by a CPU - Similar tory for torage: capacity increaed by 0x over ten year, peed only 2x ece4680 Lect Intro.3 February 6, 2002 ece4680 Lect Intro.4 February 6, 2002 Technology => dramatic change Trend Proceor logic capacity: about 30% per year clock rate: about 20% per year capacity: about 60% per year (4x every 3 year) peed: about 0% per year Cot per bit: improve about 25% per year capacity: about 60% per year 0 Supercomputer Mainframe 0 Minicomputer Microproceor Year ece4680 Lect Intro.5 February 6, 2002 ece4680 Lect Intro.6 February 6, 2002

2 ece4680 Lect Intro.7 February 6, 2002 Proceor (SPEC) 350 performance now improve ~ 50% per year (2x every.5 year) CPU and LAN Relative RISC CPU (pec) RISC introduction Ye a r Inte l x86 35%/yr MIPS M/20 DEC Alpha Mb FDDI Gb ATM 0 Mb LAN Year Did RISC win the technology battle and loe the market war? ece4680 Lect Intro.8 February 6, 2002 Moore Law Moore Law (965) The number of tranitor on a microchip double about every 8-24 month, The peed of a microproceor double about every 8-24 month, The price of a microchip drop about 48% every 8-24 month, auming the performance metric (proceor peed or memory capacity) of the chip tay the ame. Official Definition of Moore Law: ece4680 Lect Intro.9 February 6, Notation and Convention for Number H P CPrefix Appendix: Abbreviation Notation Meaning and Convention Numeric for Number Value Amill m One thouandth 0 3 micro µ One millionth nano n One billionth pico p One trillionth 0 5 femto f One quadrillionth 0 atta a One quintillionth kilo K (or k) Thouand mega M Million 6 20 giga G Billion 9 30 tera T Trillion 2 40 peta P Quadrillion 5 50 exa E Quintillion Even the meaure unit i changing!!! ece4680 Lect Intro.0 February 6, 2002 How they predict the future Popular Science, 949 "Computer in the future may weight no more than.5 ton" Computer Arch. = Intruction Set Arch. + Organization Computer Deign Thoma Waton, Chairman of IBM, 943 "I think there i a world market for maybe five computer" Ken Olen, founder and preident of Digital Equipment Corp, 957 "There i no reaon anyone would want a computer in their home" Charle H. Duell, Commiioner, U.S. Office of patent "Everything that can be invented ha been invented" Bill Gate, 98 "640K ought to be enough for anybody" Intruction Set Deign Machine Language Compiler View "Computer Architecture" "Intruction Set Proceor" "Building Architect" Computer Hardware Deign Machine Implementation Logic Deigner' View "Proceor Architecture" "Computer Organization" "Contruction Engineer" ece4680 Lect Intro. February 6, 2002 ece4680 Lect Intro.2 February 6, 2002

3 ece4680 Lect Intro.3 February 6, 2002 Intruction Set Architecture... the attribute of a [computing] ytem a een by the programmer, i.e. the conceptual tructure and functional behavior, a ditinct from the organization of the data flow and control the logic deign, and the phyical implementation. Amdahl, Blaw, and Brook, 964 SOFTWARE -- Organization of mable Storage -- Data Type & Data Structure: Encoding & Repreentation -- Intruction Format -- Intruction (or Operation Code) Set -- Mode of Addreing and Acceing Data Item and Intruction -- Exceptional Condition MIPS R3000 Intruction Set Architecture Intruction Categorie Load/Store Computational Jump and Branch Floating Point - coproceor Management Special R0 - R3 PC HI LO Intruction Format OP r rt rd a funct OP r rt immediate OP target ece4680 Lect Intro.4 February 6, 2002 Organization Example Organization ISA Level FU & Interconnect Logic Deigner' View -- Capabilitie & Characteritic of Principal Functional Unit (e.g., Regiter, ALU, Shifter, Logic Unit, etc. -- Way in which thee component are interconnected -- nature of information flow between component -- logic and mean by which uch information flow i controlled. Choreography of FU to realize the ISA Regiter Tranfer Level Decription TI SuperSPARC tm TMS390Z50 in Sun SPARCtation20 Floating-point Unit Integer Unit Int SuperSPARC Ref MMU Bu Interface Data Store Buffer Module L2 $ CC L64852 control M-S Adapter DMA Card Ethernet STDIO erial kbd moue audio RTC Boot PROM ece4680 Lect Intro.5 February 6, 2002 ece4680 Lect Intro.6 February 6, 2002 Meaurement and Evaluation Level of Repreentation Analyi Creativity Deign Cot / Analyi Architecture i an iterative proce -- earching the pace of poible deign -- at all level of computer ytem High Level Language Compiler Aembly Language Aembler Machine Language temp = v[k]; v[k] = v[k+]; v[k+] = temp; lw $5, 0($2) lw $6, 4($2) w $6, 0($2) w $5, 4($2) Good Idea Mediocre Idea Bad Idea Control Signal Spec Machine Interpretation ece4680 Lect Intro.7 February 6, 2002 ece4680 Lect Intro.8 February 6, 2002

4 ece4680 Lect Intro.9 February 6, 2002 ECE468: Coure Overview ECE468:So what' in it for me? Computer Deign Intruction Set Deign Computer Hardware Deign Machine Language Machine Implementation\ Compiler View Logic Deigner' View "Computer Architecture" "Proceor Architecture" "Intruction Set Proceor" "Computer Organization" "Building Architect" Contruction Engineer Few people deign computer! Very few deign intruction et! Many people deign computer component. Very many people are concerned with computer function, in detail. In-depth undertanding of the inner-working of modern computer, their evolution, and trade-off preent at the hardware/oftware boundary. Inight into fat/low operation that are eay/hard to implementation hardware Experience with the deign proce in the context of a large complex (hardware) deign. Functional Spec --> Control & Datapath Learn how to completely deign a correct ingle proceor computer. No magic required to deign a computer Foundation for tudent apiring to work in computer architecture. Other: olidifie an intuition about why hardware i a it i. ece4680 Lect Intro.20 February 6, 2002 The Level of Organization SIMM Bu Computer MSBI Bu SPARC Proceor Control Datapath Device Input Output & Moue External Bu ece4680 Lect Intro.2 February 6, 2002 ece4680 Lect Intro.22 February 6, 2002 The Underlying Network Proceor and MSBI Proceor Bu: Bu Standard I/O Bu: Sun High Speed I/O Bu: Bu Module SuperSPARC Proceor Regiter Internal Datapath Control Low Speed I/O Bu: External Bu External ece4680 Lect Intro.23 February 6, 2002 ece4680 Lect Intro.24 February 6, 2002

5 ece4680 Lect Intro.25 February 6, 2002 Input and Output (I/O) Device Bu: Standard I/O Device SIMM SIMM SIMM SIMM SIMM Slot 4 SIMM Slot 5 SIMM Slot 6 SIMM Slot 7 Bu : High Speed I/O Device External Bu: Low Speed I/O Device SIMM Bu & Moue External Bu ece4680 Lect Intro.26 February 6, 2002 Standard I/O Device High Speed I/O Device = Small Computer Sytem Interface A tandard interface (IBM, Apple, HP, Sun... etc.) Computer and I/O device communicate with each other The hard dik i one I/O device reide on the Bu i SUN own high peed I/O bu SS20 ha four lot where we can plug in I/O device Example: graphic accelerator, video adaptor,... etc. High peed and low peed are relative term Bu ece4680 Lect Intro.27 February 6, 2002 ece4680 Lect Intro.28 February 6, 2002 Slow Speed I/O Device The are only four lot in SS20-- eat are expenive The peed of ome I/O device i limited by human reaction time--very very low by computer tandard Example: and moue No reaon to ue up one of the expenive lot Summary ISA--Principle of abtraction Hiding detail from the level above Both oftware deigner and hardware deigner comply with All computer conit of five component Proceor: () datapath and (2) control (3) (4) Input device and (5) Output device Not all memory are created equally : fat (expenive) memory are placed cloer to the proceor Main memory: le expenive memory--we can have more Input and output (I/O) device ha the meiet organization & Moue External Bu Wide range of peed: graphic v. keyboard Wide range of requirement: peed, tandard, cot... etc. Leat amount of reearch (o far) ece4680 Lect Intro.29 February 6, 2002 ece4680 Lect Intro.30 February 6, 2002