14:332:331. Lecture 1

Transcription

1 14:332:331 Computer Architecture and Assembly Language Fall 2003 Lecture 1 [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] 331 W01.1

2 Course Administration Instructor: Yanyong Zhang Core 518 Hours: TF am TAs: TBD Labs: Everyone will be using your ece account. Texts:Computer Organization and Design: The Hardware/Software Interface, Second Edition, Patterson and Hennessy VHDL Starter s Guide, Yalamanchili 331 W01.2

3 Course Administration Course web page Please check the course web page regularly (at least once before class) for announcements, assignments, etc. Class mailing list Please post s on this list only when you want to talk to the whole class. If you only want to talk to the instructor, or a TA, please do not abuse the mailing list. I will be using the list to distribute the announcements and answer some common questions. Please report if you have not got my test message. Please report if you want to use another account. WebCT is available for you to check your grades and conduct group discussion. I will NOT post any notes there. 331 W01.3

4 Convention Please check your and the course web page regularly. Every class First minutes, review of last class. Students will be randomly picked to answer questions Class participation will be based on this Discussion-oriented Instructor vs. TA vs. students Instructors are responsible for answering questions related to the lectures to both students and TAs Students should ask TAs about the homework and grades If TAs cannot answer the students, they will contact the instructor directly. 331 W01.4

5 Course Goals and Structure Fundamentals of assembly language programming MIPS assembler programming using the spim system Introduction to the major components of a computer system. To bridge the gap between high level programming and low level digital design. VHDL design simulation using the Synopsys VSS tools Prerequisite (required): 14:332:231 Digital Logic Design 14:332:252 Programming Methodology Corequisites 14:332:333 Computer Architecture Lab 331 W01.5

6 spim Assembler and Simulator spim is a self-contained assembler and simulator for the MIPS R2000/R3000 It provides a simple assembler, debugger and a simple set of operating system services It implements both a simple, terminal-style interface and a visual windowing interface Available as xspim on unix - installed on the Sun machines in EE bldg, /usr/local/spim/bin/xspim PCSpim on Windows - can be downloaded and installed on your own PC from Sorry, there is no Macintosh version of spim 331 W01.6

7 vhdl Analyzer and Simulator VSS is Synopsys s VHDL system simulator It provides a vhdl analyzer that translates vhdl code into the binary required by the vhdl simulator It provides a vhdl simulator and a source code debugger with a graphical user interface for monitoring the simulation It provides a waveform viewer for observing the results of the simulation as signal waveforms Available as vhdlan (text based) or gvan (graphical) vhdlsim (text based) or vhdldbx (graphical) waves - The entire (almost) Synopsys tool set is installed on the Sun machines in the EE bldg 331 W01.7

8 Grading Information Grade determinates Midterm Exam #1 ~21% - Tuesday, Sep 30 th, evening Midterm Exam #2 ~23% - Tuesday, November 11 th, evening Final Exam ~26% - TBD 7 Homework/Programming Assignments ~20% In-class pop quizzes ~ 5% Class Participation ~ 5% Please let me know about exam conflicts ASAP 331 W01.8

9 Grading Policies Assignments will be submitted via (mostly) and must be turned in by 5:00pm on the due date. No late assignments will be accepted. All the assignments should be completed individually. Duplicate assignments will receive duplicate grades of zero. Second offenses will result in a final course grade of F. Grades will be posted on the WebCT See TAs about grading questions on the assignments; see instructor (me) about grading questions on the exams Must submit request for change of grade after discussions with the TAs or instructor 331 W01.9

10 Head s Up This week s material Course introduction Reminders - Reading assignment PH 1.1 through 1.3 and A.9 through A.10 14:332:333 will start from next week HW1 will be handed out on Friday, September 5 th in class. HW1 is due Friday, September 12 th (by 5:00pm) Question/comments about the system go to help@ece.rutgers.edu; questions about the programming assignments go to the course TAs. Next week s material Introduction to MIPS assembler - Reading assignment - PH 3.1 through 3.3, 3.4, and W01.10

11 What You Should Already Know How to write, compile and run programs in a higher level language (C, C++, Java, ) How to create, organize, and edit files and run programs on Unix How to represent and operate on positive and negative numbers in binary form (two s complement, sign magnitude, etc.) Logic design How to design combinational and sequential components (Boolean algebra, logic minimization, technology mapping, decoders and multiplexors, latches and flipflops, registers, mealy/moore finite state machines, state assignment and minimization, etc.) How to use a logic schematic capture and simulation tool (e.g., LogicWorks) 331 W01.11

12 Below the Program High-level language program (in C) swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; ) Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4,$2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Machine (object) code (for MIPS) 331 W

13 Below the Program High-level language program (in C) swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; ) Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4,$2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Machine (object) code (for MIPS) W01.13 C compiler assembler

14 Advantages of Higher-Level Languages Higher-level languages Allow the programmer to think in a more natural language and for their intended use (Fortran for scientific computation, Cobol for business programming, Lisp for symbol manipulation, ) Improve programmer productivity more understandable code that is easier to debug and validate Improve program maintainability Allow programmers to be independent of the computer on which they are developed (compilers and assemblers can translate high-level language programs to the binary instructions of any machine) Emergence of optimizing compilers that produce very efficient assembly code optimized for the target machine As a result, very little programming is done today at the assembler level 331 W01.14

15 Machine Organization Capabilities and performance characteristics of the principal Functional Units (FUs) e.g., register file, ALU, multiplexors, memories,... The ways those FUs are interconnected e.g., buses Logic and means by which information flow between FUs is controlled The machine s Instruction Set Architecture (ISA) Register Transfer Level (RTL) machine description 331 W01.15

16 Major Components of a Computer Processor Devices Control Memory Input Datapath Output 331 W01.16

17 Computer Types Notebook computer Sony Vaio, IBM Thinkpad, etc Mobile users Desktop Dell Dimension, Dell OptiPlex Most widely used in everyday life Workstation Dell Precision, Sun Blade, IBM IntelliStation Same dimensions as desktop computers High-resolution graphics I/O capability, more computational power servers ~ supercomputers HP Integrity Superdome, IBM eserver Computing power and storage 331 W01.17

18 Computer Organization Processor Devices Control Memory Input Datapath Output 331 W01.18

19 Instruction vs. Data void main (){ // instruction int a,b,c; // data c = a + b; // instruction } Instructions (machine instructions) Data Govern the transfer of information within a computer (e.g., load, store) Specify the arithmetic and logic operations to be performed (e.g., add, sub, mul) Operands of the instruction Both instructions and data are in binary format 331 W01.19

20 Input Device Inputs Object Code Processor Devices Control Memory Input Input devices Keyboard Datapath Output Mouse Network Joysticks, trackballs, etc 331 W01.20

21 Object Code Stored in Memory Processor Control Datapath Memory Devices Input Output 331 W01.21

22 Memory Unit: to store the program Primary storage: fast memory that operates at electronic speed Programs must be stored in fast memory when they are being executed The memory contains a large number of semiconductor storage cells, each containing a bit The unit of memory access is a byte or a word, not a bit To provide easy access to any byte/word, a distinct address is associated with each byte location The number of bits in each word is called word length of the computer. That is also the length of instructions. RAM: random access memory. Access time to any location is uniform Memory hierarchy: L-1 cache, L-2 cache, main memory 331 W01.22 Secondary storage Magnetic disks, tapes, optical disks

23 How to execute a program? Sequential execution Fetch Exec Decode 331 W01.23

24 Processor Organization Control needs to have the Ability to input instructions from memory Logic and means to control instruction sequencing Logic and means to issue signals that control the way information flows between datapath components Logic and means to control what operations the datapath s functional units perform Datapath needs to have the Components - functional units (e.g., adder) and storage locations (e.g., register file) - needed to execute instructions Components interconnected so that the instructions can be accomplished Ability to load data from and store data to memory 331 W01.24

25 Instruction Fetch How do you know which instruction next? PC (Program Counter) Where to store PC? (disk, memory, cache, register) How to update PC? (sequential, branch) 331 W01.25

26 Processor Fetches an Instruction Processor fetches an instruction from memory PC Processor Control Datapath Memory Devices Input Output 331 W01.26

27 Control Decodes the Instruction Control decodes the instruction to determine what to execute Processor Control Datapath Memory Devices Input Output 331 W01.27

28 Datapath Executes the Instruction Datapath executes the instruction as directed by control Processor Control Datapath contents Reg #4 ADD contents Reg #2 results put in Reg #2 Memory Devices Input Output 331 W01.28

29 Output Data Stored in Memory At program completion the data to be output resides in memory Processor Memory Devices Control Input Datapath Output 331 W01.29

30 Output Device Outputs Data Processor Devices Control Memory Input Datapath Output W01.30

31 Hardware/Software Interface Application software System software Instruction set architecture includes everything programmers need to know to make a binary program to work Instruction Arithmetic and Logic Unit (ALU), registers, etc hardware Instruction set architecture (architecture) 331 W01.31

32 The Instruction Set Architecture software instruction set architecture hardware The interface description separating the software and hardware. 331 W01.32

33 MIPS R3000 Instruction Set Architecture Instruction Categories Load/Store Computational Jump and Branch Floating Point - coprocessor Memory Management Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP rs rt rd sa funct OP rs rt immediate OP jump target 331 W01.33 Q: How many already familiar with MIPS ISA?

34 How Do the Pieces Fit Together? Application Operating System Memory system Compiler Firmware Instr. Set Proc. Datapath & Control Digital Design Circuit Design I/O system Instruction Set Architecture Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation 331 W01.34

35 How Do the Pieces Fit Together? Application Operating System Memory system Compiler Firmware Instr. Set Proc. Datapath & Control Digital Design Circuit Design I/O system Instruction Set Architecture Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation 331 W01.35