Microcontroller Systems

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1 µcontroller systems 1 / 38 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray david.murray@eng.ox.ac.uk dwm/courses/2co Michaelmas 2014

2 µcontroller systems 2 / 38 Lecture 4 Input/Output, Interfacing, and Applications

3 µcontroller systems 3 / 38 Introduction We have learned how a computer s CPU and memory function and interact, but as yet we have not considered methods of getting information into or out of the computer without which the whole exercise is pointless. Computer I/O can be described at a number of levels. Layers of software protocols build on yet more layers of hardware definition. Our first aim here is to consider I/O the lowest level, which means...

4 µcontroller systems 4 / 38 Register transfers yet again We ve learned that the CPU is able to output to memory input from memory using an address bus and decoder to select a particular register in memory, a data bus to transfer the register s contents in or out of the CPU a control bus to carry control signals (OEmem, Write/Read) MAR Decoder CPU MBR Location Memory

5 µcontroller systems 5 / 38 Exactly the same idea can be exploited for output to a particular device printer, DAC, video display, etc. CPU MAR MBR Serial link Serializer Parallelizer OR Parallel link Decoder IO Register Device Data transfer to memory is performed in parallel high bandwidth option is suited to devices which are physically close to CPU. For longer distances, the output can be serialized. (For many years serial communications were s l o w, but fast serial links are nowadays available over Universal Serial Buses (USB) and Firewire.)

6 µcontroller systems 6 / 38 Buses In a modern desktop PC, the bus typically consists of 50 to 100 separate lines in these three functional groups, and made available on the motherboard A microcontroller will have the same buses, but there is no equivalent motherboard CPU Memory I/O I/O Control Bus Data Bus Address Bus buses, memory and i/o devices tend to be held within a single IC package.

7 µcontroller systems 7 / 38 Bus Designs Bus design made awkward by the intricacies of timing different device speeds plus accumulated transport delay td = gate delay (3-6 ns) + capacitance delay (5 ns) + transit delay (6 ns m 1 ). At the lowest level there are two major design approaches: Synchronous design requires devices to respond within a specified time. No continuous checks of whether the device received the data. Unsuitable when a mix of fast and slow devices sit on the bus. Asynchronous design devices are considered to have their own clocks, and they a treated as separate RTL modules. CPU and IO device negotiates transmission and receipt using two control bus signals that continually monitor readiness to send and receive data. (Hardware handshaking.)

8 µcontroller systems 8 / 38 Strategies for I/O: a comparison

9 µcontroller systems 9 / 38 Strategies for I/O Our main concern is with I/O that directly involves the CPU. We ll discuss Programmed I/O (uses CPU), not Direct Memory Access. Port mapped I/O Programmed I/O Polled I/O Interrupt driven I/O Memory Mapped I/O Direct Memory Access Within programmed I/O we compare... Port-mapped I/O with Memory-mapped I/O How can peripherals avoid wasting CPU time? We compare... Polled I/O with Interrupt-driven I/O

10 µcontroller systems 10 / 38 Register-based I/O towards port-mapped I/O Consider eight I/O registers that sit in a special port address space. We ll need a special 3-bit address bus & decoder to determine which to I/O with, and a special data bus. No need to group them together they can sit separately on the bus. Selection 3 Port address space I/O registers R/W by peripherals Data to and from registers Data to and from registers But we would need a special PortMAR and PortMBR...

11 µcontroller systems 11 / 38 Port-mapped I/O More economical to use the main data and address buses, and just connecting the lowest 3 address lines A0-A2 to the IO Registers. Address 24 Main Memory IO Registers CS Data Data to and from registers USEmem/USEport BUT the addresses of the IO registers overlap those of main memory... so we require a USEmem/USEport control level. This will feed into the memory s ChipSelect, and we need a similar ChipSelect on each set of IO Registers.

12 µcontroller systems 12 / 38 Port-mapped I/O Port-mapping CPUs have IN and OUT instructions. For example: LDA# 0x9A80 ;; shove hex 9A80 into AC OUT 0x007 ;; and send it to the PORT with address 0x07 Address 24 Main Memory IO Registers CS Data Data to and from registers USEmem/USEport Each IO register needs to be readable and writeable both by the cpu and by the external peripheral. Use dual-ported registers.

13 µcontroller systems 13 / 38 Port-mapped I/O Usually a device will not use just one port address, but many most for the transfer of proper data others transfer status info on the device. Status info used to implement hand shaking. E.g. 12 address lines (of our usual 24) are used to address K I/O registers. Address A0 A23 FFFFFF Address A0 A11 FFF Decoder Main Memory Decoder 28F Device IO Registers DP Data IOR IOW Control USEmem USEport

14 µcontroller systems 14 / 38 Memory-mapped I/O Recall that the memory address space may have gaps where there is no physical main memory. We could do away with the need to select between USEmem or USEport if we put the I/O Registers into available gaps in the memory address space. Memory address space I/O registers I/O registers Main Memory R/W by peripherals R/W by peripherals Main Memory I/O registers I/O registers (a) (b)

15 µcontroller systems 15 / 38 Memory-mapped I/O /ctd As earlier, dual Ported registers are required Now, writing and reading to a device can use the standard instruction for loading from and storing into memory. For example LDA# 0x9A80 ;; get 9A80 hex into accumulator STA 0x00CC00 ;; and send to IO reg at address CC00 hex

16 µcontroller systems 16 / 38 The methods compared Both methods have a mix of memory and i/o registers on the same bus and port-mapped requires that extra control wire. Address Main Memory I/O registers I/O registers Data USEmem/USEport Address Main Memory I/O registers I/O registers Data So why is port-mapping used? 1 In µcontrollers, main memory address space often full 2 The hardware cost of decoding (here, 3bits vs 24bits) Remember, each device requires its own decoder.

17 µcontroller systems 17 / 38 Polled versus Interrupt-driven I/O Port mapped I/O Programmed I/O Polled I/O Interrupt driven I/O Memory Mapped I/O Direct Memory Access

18 µcontroller systems 18 / 38 Handshaking When there is a mix of fast and slow devices on a bus one needs a method of handshaking between the CPU and device. Full handshaking involve conversations like... CPU: Are you ready? IOdev: I m ready CPU: Have you got it? IOdev: I ve got it The notes describe how handshaking is implemented at the lowest level on asynchronous buses. But we don t want to rely on nano-second timescale handshaking to cope with communication with devices which are orders of magnitude slower.

19 µcontroller systems 19 / 38 Example: Buffered I/O One approach to bridging the speed gap is to output data in bursts, buffering it in fast memory on the slow device. Peripheral Emptied slowly The FIFO buffer must be bigger than the volume of data that might be output in one burst Filled quickly... FIFO buffer Slow part of device But the arrangement is not wholly robust at very least the IOdevice must have a bit in a device status register indicating READY or NOTREADY. We consider two ways of handling handshaking at this higher level: Polling and Interrupts.

20 µcontroller systems 20 / 38 Polling The CPU periodically checks the status of the device. Code transfers 100 Bytes of data from an array at address 0x200 to an output register at Port 0x500. The status word is at Port 0x501. LDA #200 ; Load base address into AC STA 22 ; Loc22 hold address of array element LOOP: IN 501 ; read device status word <<<<<<<<< AND #1 ; is the lowest bit equal to 1? <<<<<<<<< BZ LOOP ; if not, jump to LOOP <<<<<<<<< LDA (22) ; Load contents of array location OUT 500 ; write them to device LDA 22 ; Load and ADD #1 ; increment the location STA 22 ; and store it back SUB #300 ; Have we gone too far? BNZ LOOP ; If not, carry on looping BIG SNAG: If the processor is fast and the device slow, the polling loop will be executed many times before the status bit changes.

21 µcontroller systems 21 / 38 How wasteful could this be? Er, VERY! Suppose the IO device handles some 1000 Bytes per second. To handle one Byte takes 10 3 s. A 2 GHz CPU taking 4 clock cycles per instruction will take only (3instructions 4cycles)/( ) 10 8 s to handle computation the polling loop. The polling loop executes approx 10 5 times while waiting for the device to be ready again! Could try to be more efficient by completing other tasks before re-polling... No Check device status Ready? Yes Transfer data to device (a) Increment Complete n th n useful task No Check device status Ready? Yes Transfer data to device (b)

22 µcontroller systems 22 / 38 Interrupt-driven i/o Fetch Decode Execute No IRQ=1? Yes Jump to Int Service Rtne Normal instruction cycle Much more efficient to allow the peripheral to signal to the CPU that it is ready to input or output the peripheral interrupts the processor from its usual grind through the programmed instructions. In program memory are a set of interrupt service subroutines each contains the instructions to handle a particular device interrupt. When the interrupt occurs the processor jumps to the subroutine and then returns to carry on with the programmed instructions. Although it is a subroutine... it could appear at any time! The machine must make sure the programmer s data in the CPU registers is saved before the interrupt and restore after the interrupt.

23 µcontroller systems 23 / 38 Interfacing for Real-time Control

24 µcontroller systems 24 / 38 Microcontroller architecture We can now appreciate the architecture of a typical microcontroller which integrates onto a single chip: CPU and Memory (ROM, RAM and (E)EPROM) IO Ports (digital and A/D, pulse, serial/parallel comms, etc) IO control and status registers Timers Internal buses to connect the components Hardware Timers Interrupt Controller Serial Comms I/O Ports External bus Clock CPU Program Memory (EPROM) Data Memory (RAM)

25 µcontroller systems 25 / 38 Connecting the microcontroller to peripherals Now we need to think about devices which might be connected to the I/O ports not printers etc, (most texts will discuss in some detail devices such as keyboards, printers, disks, etc), but devices used as part of a general engineering system for data acquisition and control output.

26 µcontroller systems 26 / 38 Simple Digital I/O: Input Simple means input from switches or similar that produce a few bits to indicate their state. Eg: A safety management system may wish to monitor pairs of switches indicating that a seat is occupied and a a seat-belt buckled. 5 switches are connect to bits D0... D4 of the input register. The device clocks the input register, but the CPU output-enables it for transfer to the AC Plant Sensors Output Decoder Select Digital inputs D D0 Input register CPU Enable Data Address Control

27 µcontroller systems 27 / 38 Simple Digital I/O: Input Output Plant Sensors Decoder Select Digital inputs D D0 Input register CPU Enable Suppose the port has address 0xFA all D[4:0] are meant to be high alarm set off if any of the 5 inputs is low Data Address Control again: IN 0xFA ;; read the register into the AC. ;; If all well, the AC should contain SUB #0x1F ;; subtract 0x1F or BNZ alarm ;; the answer should be 0, if it isn t, panic! JMP again alarm:..

28 µcontroller systems 28 / 38 Simple Digital I/O: Output Output Here a relay for switching a large current is controlled. PLANT Decoder Select Output register Digital outputs CPU WRITE Data Address Control data Select Write 8 Q7 + D type reset Output register Q0 Solid state relay

29 µcontroller systems 29 / 38 Simple Digital I/O: Output Suppose data Select Write the port is at OxFB, 8 Q7 + D type reset Output register Q0 all output lines are used and Solid state relay the current status is stored in memory location 0x0123. We want to send the entire current status to the register, except that we must ensure that the MSB is 1 to turn on the relay. The code is LDA 0x0123 ;; get desired status from memory OR #0x80 ;; OR with binary OUT 0xFB ;; out to port STA 0x0123 ;; store status for future use

30 µcontroller systems 30 / 38 Analogue Input: From an A-to-D Recall the role on the computer as part of a digital compensator Engineered transfer function Compensator Plant s Transfer Function Sensing Well behaved S&H + ADC S&H + ADC Computer DAC then ZOH Plant s Transfer Function Sensing Computer Controlled

31 µcontroller systems 31 / 38 Analogue Input: From an A-to-D Analogue Demand Multiplexer Channel select Sample and Hold Sample ADC Convert EofC IO Interface CPU Plant Analogue Sensor The I/O interface just contains an address decoder, data register, and some timing circuitry. The multiplexer allows the ADC to access several inputs here the analogue demand and the sensor feedback.

32 µcontroller systems 32 / 38 Analogue input: S&H and Flash Converter Vin Vref Vsh Vsh 7 Sample 6 V Vin Vsh priority encoder 3 3 bit binary output 2 Hold Track t gnd 1 0

33 µcontroller systems 33 / 38 Analogue I/O: Output with a D-to-A Provides continuous voltage control... Select Sample DAC ZOH Vin CPU IO Interface Plant Vsh DAC Sample DAC Vref 10V R R R 2R 2R 2R 2R 2R VZOH R 8 MSB LSB

34 µcontroller systems 34 / 38 Digital Control System

35 µcontroller systems 35 / 38 Digital control The continuous output y(t) is sampled and held, then digitized, giving discrete time samples of the input y(kt )... r(t) y(t) S&H + ADC S&H + ADC r(kt) y(kt) Computer c(kt) DAC then ZOH c(t) Plant s G(s) y(t) Sensing 1 But what computations are done in the computer box?

36 µcontroller systems 36 / 38 Controller implementation... eg PID control An important quantity to derive is the error between the output (kt )and the demand r(kt ). Dropping the sampling interval T... e(k) = r(k) y(k). A common method of control is to let the output of the compensator be the sum of three terms which are proportional (i) the error between the output and the demand, (ii) to its integral and (iii) to its derivative ) c(t) = K (e(t) + 1Ti e(t)dt + T d ė(t) ( ċ(t) = K ė(t) + 1 ) e(t) + T d ë(t) T i Now substitute backward differences for the derivatives... and ċ(k) ë(k) c(k) c(k 1) T ė(k) ė(k 1) T and ė(k) e(k) e(k 1) T e(k) 2e(k 1) + e(k 2) T 2

37 µcontroller systems 37 / 38 Controller implementation... eg PID control Plug these into ċ(t) = K ( ė(t) + 1 ) e(t) + T d ë(t) T i and rearrange to obtain c(k) = c(k 1) + [( K 1 + T + T ) d e(k) T i T ( T ) d e(k 1) + T ( ) ] Td e(k 2) T A few LDA s and STA s later...

38 µcontroller systems 38 / 38 What have we learned in this course... Separation of data from control The data section of the CPU contains nothing but a few registers and an ALU Aim is to shovel Bytes around! Pathways set up by Levels, Registers clocked by Pulses CSLs and CSPs come from the control unit. Their sequence determine by the instruction Memory just a bunch of registers I/O just a bunch of registers

Microcontroller Systems

µcontroller systems 1 / 43 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/2co Michaelmas 2014 µcontroller