Optimized Reconfigurable Cell Array (ORCA ) OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays
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1 Optimized Reconfigurable ell Array (ORA ) OR3xxx/OR3Txxx Series Field-Programmable Gate Arrays Features High-performance, cost-effective 0.35 µm, 4-level metal technology, with a migration plan for 0.25 µm technology (four-input look-up table delay less than 1.7 ns with -5 speed grade in 0.35 µm). Up to 125,000 usable gates in 0.35 µm, expanding to 225,000 usable gates in 0.25 µm. Up to 448 user I/Os in 0.35 µm. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Twin-quad PFU architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user flip-flops per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset plus a global set/reset that can be disabled per PFU. New Flexible INput Structure (FINS) of the PFUs provides the routability enhancement of shared input LUTs and the logic flexibility of independent LUT inputs. Internal fast-carry for nibble- or byte-wide arithmetic functions, with option to register carry-out for either. New soft-wired LUTs allow fast cascading of up to three levels of LUT logic in a single PFU without using local PFU routing resources. Synthesis friendly by design. New supplemental logic and interconnect cell (SLI) provides 3-statable buffers, up to 10-bit decoder, and PAL*-like AND-OR-Invert (AOI) in each PL. Abundant hierarchical routing resources, based on routing two data nibbles and two control lines per set, provides for faster place and route implementations and less routing delay. TTL or MOS input levels are programmable per pin for the OR3xxx (5 V) devices. Individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. Built-in boundary scan (IEEE ). Enhanced system clock routing for low-skew, highspeed clocks originating on-chip or at any I/O. Up to four new ExpressLK inputs allow extremely fast clocking of signals on- and off-chip with access to general clock routing. New clock stop circuitry to glitchlessly stop and start the ExpressLKs independently by user command. New programmable I/O cell (PI) input has: Fast-capture latch and input FF/latch for reduced input setup time and zero hold time. apability to demultiplex input signals. Fast access to SLI for decodes and PAL-like functions. New programmable I/O cell output has: Fast-output register with signal multiplexing capability. Two-input function capability. Fast open-drain drive capability. * PAL is a trademark of Advanced Micro Devices, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table 1. Lucent Technologies ORA OR3xxx/OR3Txxx Series FPGAs Device Usable Gates Registers Max. User RAM User I/Os Array Size Process Technology OR3/3T30 19K 44K K x µm/4 LM OR3/3T55 32K 72K K x µm/4 LM OR3/3T80 47K 108K K x µm/4 LM OR3/3T125 76K 174K K x µm/4 LM OR3T K 227K K x µm/4 LM OR3T K 320K K x µm/4 LM The first number in the usable gates column assumes 96 gates per PFU (12 gates per 4-input LUT/FF pair) for logic-only designs. The second number assumes 30% of a design is RAM. PFUs used as RAM are counted at 4 gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
2 ORA OR3xxx/OR3Txxx Series FPGAs System-Level Features System-level features reduce glue logic requirements and make a system on a chip possible. Full PI compliance. New dual-use microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA. Glueless interface to i960 *, PowerP, and M68xxx processors with userconfigurable address space provided. New parallel readback capability with the built-in microprocessor interface. New programmable clock manager (PM) adjusts clock phase and duty cycle for input clock rates from 10 MHz to 80 MHz. The PM may be combined with FPGA logic to create complex functions, such as digital phase-locked loops (DPLL), frequency counters, and frequency synthesizers or clock doublers. True internal 3-state, bidirectional buses with simple control provided by the new SLI. 32 x 4 RAM per PFU, configurable as single- or dualport at >100 MHz. reate large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using new SLI decoders and bank drivers. Support ORA Foundry Development System support. Supported by industry-standard AE tools for design entry, synthesis, simulation, and timing analysis. * i960 is a trademark of Intel orporation. M68xxx is a trademark of Motorola, Inc. Description The ORA OR3xxx/OR3Txxx series is a new generation of AM-based FPGAs built on the successful OR2xxA/OR2TxxA FPGAs from Lucent Technologies Microelectronics Group, with enhancements and innovations geared toward today s high-speed designs and tomorrow s systems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORA 2/2T devices, the OR3xxx/ OR3Txxx series more than doubles the logic available in each PFU and incorporates system-level features that can further reduce logic requirements and increase system speed. OR3xxx/OR3Txxx devices contain many new patented architectural enhancements and are offered in a variety of packages, speed grades, and temperature ranges. The ORA OR3xxx/OR3Txxx Series FPGAs consist of three basic elements: programmable logic cells (PLs), programmable input/output cells (PIs), and system-level features. An array of PLs is surrounded by PIs. Each PL contains a programmable function unit (PFU), a SLI, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU (see Figure 1), whereas decoders, PAL-like functions, and 3-state buffering can be performed in the SLI (see Figure 2). The PIs can be used to register signals, perform input demultiplexing, and perform output multiplexing and other functions on two output signals (Figure 3). Some of the system-level functions include the new microprocessor interface and the programmable clock manager (PM). Each PFU contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop. LUTs may be used individually, be combined to produce 5-input LUTs, or be cascaded in a variety of ways to achieve complex functions of up to 21 inputs using the new soft-wired LUT connections. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs, which can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. 2 Lucent Technologies Inc.
3 ORA OR3xxx/OR3Txxx Series FPGAs AR7 L7[d:a] L7d L7c L7b L7a LUT7 AR6 F7 WD7 D7 REG7 Q7 [9, 8, 7:4] B[9, 8, 7:4] A[9, 8, 7:4] L6[d:a] L5[d:a] L6d L6c L6b L6a L5d L5c L5b L5a LUT6 LUT5 AR5 AR4 F6 F5 WD6 WD5 D6 D5 REG6 REG5 Q6 Q5 O9 O8 O7 O6 O5 L4[d:a] F5, F5D L3[d:a] L4d L4c L4b L4a L3d L3c L3b L3a LUT4 LUT3 AR3 AR2 F4 F3 WD4 WD3 D4 D3 REG4 REG3 Q4 Q3 [9, 8, 3:0] B[9, 8, 3:0] A[9, 8, 3:0] L2[d:a] L1[d:a] L2d L2c L2b L2a L1d L1c L1b L1a LUT2 LUT1 AR1 AR0 F2 F1 WD2 WD1 D2 D1 REG2 REG1 Q2 Q1 O4 O3 O2 O1 O0 ASWE K L0[d:a] WD[7:0] SEL K1 K2 K3 K L G L0d L0c L0b L0a IN F5A, F5B LUT0 WD0 Note: L can be disabled on a per-nibble basis, and G can be disabled per PFU. F0 D0 REG0 Q0 AR7 IN AR3 OUT REGOUT REG (F) Figure 1. Simplified OR3xxx/OR3Txxx PFU Diagram Lucent Technologies Inc. 3
4 ORA OR3xxx/OR3Txxx Series FPGAs PFU OUTPUTS BL9 0 1 BR9 DEODE/ PAL MODE BL8 0 1 BR8 BUF[9:8] DE[9:8] BL7 BR7 BL6 BR6 BUFFER MODE BL5 BR5 BUF[7:4] TRI[7:4] DE[7:4] BL4 BR4 TRI 1 0 BL3 BR3 3-STATE MODE BL2 BR2 BUF[3:0] TRI[3:0] DE[3:0] BL1 BR1 BL0 BR DEOUT DE AOI (F) Figure 2. OR3xxx/OR3Txxx SLI 4 Lucent Technologies Inc.
5 ORA OR3xxx/OR3Txxx Series FPGAs MULTIPLEXER AND OUTPUT LOGI OUT1 OUT2 I/O BUFFER PAD D Q PI SWITHING E KIN IN1 IN2 Q D L G SYN ONTROL E K SLK ELK (F) Figure 3. Simplified 1/4 PI (Single Pin) Diagram The SLI is connected to PL routing resources and the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR-INVERT to perform PALlike functions. The 3-state drivers in the SLI and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPGA, reducing required routing and allowing for real-world system performance. The OR3xxx/OR3Txxx PI addresses the demand for ever-increasing system clock speeds. On the input side, each PI contains a fast capture latch that is clocked by an ExpressLK. This latch is followed by a latch/ff that is clocked by a system clock. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Lucent Technologies Inc. 5
6 ORA OR3xxx/OR3Txxx Series FPGAs Two input signals are available to the PL array from each pad, and the ORA 2/2T capability to use any input as a clock or other global input is maintained. On the output side of each PI, two outputs from the PL array can be routed to each output flip-flop and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output flip-flop in combination with output signal multiplexing is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is very similar to the ORA 2/2T Series buffer with enhanced 24 ma sink/12 ma source capability and a new fast open-drain option for ease of use on system buses. The abundant routing resources of the OR3xxx/ OR3Txxx FPGAs is organized to route signals individually or as buses with related control signals. locks are routed on a low-skew, high-speed distribution network and may be sourced from PL logic, externally from any I/O pad, or from the very fast ExpressLK pins. ExpressLKs may be glitchlessly, and independently, enabled and disabled with a programmable control signal. The OR3xxx/OR3Txxx series also provides systemlevel functionality by means of its dual-use microprocessor interface and its innovative programmable clock manager. Some of the capabilities of these features are noted in the Features section at the beginning of this product brief. These features will be further explained in application notes available from Lucent Technologies. The ORA Foundry Development System is used to process a design from a netlist to a configured FPGA. This system is used to map your design onto the ORA architecture and then place and route it using ORA Foundry s timing-driven tools. The development system also includes interfaces to, and libraries for, other popular AE tools for design entry, synthesis, simulation, and timing analysis. The FPGA s functionality is determined by internal configuration RAM. The FPGA s internal initialization/ configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes. The configuration data resides externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin count method for configuring FPGAs. A new method for configuring the devices is through the microprocessor interface. Additional Information ontact your local Lucent Technologies representative for additional information regarding the ORA OR3xxx/OR3Txxx FPGA devices. For FPGA technical applications support, please call Outside the U.S.A., please call For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103, , FAX (In ANADA: , FAX ), docmaster@micro.lucent.com ASIA PAIFI: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 intech III, Singapore Tel. (65) , FAX (65) JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) , FAX (81) For data requests in Europe: MIROELETRONIS GROUP DATALINE: Tel. (44) , FAX (44) For technical inquiries in Europe: TRAL EUROPE: (49) (Munich), NORTHERN EUROPE: (44) (Bracknell UK), FRANE: (33) (Paris), SOUTHERN EUROPE: (39) (Milan) or (34) (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORA is a trademark of Lucent Technologies. Foundry is a trademark of Xilinx, Inc. opyright 1996 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. PN96-208FPGA Printed On Recycled Paper
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