ORCA Series 3C and 3T Field-Programmable Gate Arrays

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1 Product rief January 22 OR Series 3 and 3T Field-Programmable Gate rrays Features High-performance, cost-effective,.35 µm and.3 µm 4-level metal technology (4- or 5-input look-up table delay of.2 ns with -7 speed grade in.3 µm). Same basic architecture as lower-voltage, advanced process technology Series 3 architecture (see OR Series 3Lxxx FPGs documentation). Up to 86, usable system gates. Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Pin-selectable I/O clamping diodes provide 5 V or 3.3 V PI compliance and 5 V tolerance on OR3Txxx devices. Twin-quad programmable function unit (PFU) architecture with eight 6-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. llows for mixed arithmetic and logic functions in a single PFU. Nine user registers per PFU, one following each LUT, plus one extra. ll have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU. Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs. Fast-carry logic and routing to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the new option to register the PFU carry-out. Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU for up to 4% speed improvement. Supplemental logic and interconnect cell (SLI) provides 3-statable buffers, up to -bit decoder, and PL*- like N-OR-INVERT (OI) in each programmable logic cell (PL), with over 5% speed improvement typical. bundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay. TTL or MOS input levels programmable per pin for the OR3xxx (5. V) devices. Individually programmable drive capability: 2 m sink/ 6 m source or 6 m sink/3 m source. uilt-in boundary scan (IEEE 49. JTG) and TS_LL testability function to 3-state all I/O pins. Enhanced system clock routing for low-skew, high-speed clocks originating on-chip or at any I/O. Up to four ExpressLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. StopLK feature to glitchlessly stop/start the Express- LKs independently by user command. Programmable I/O (PIO) has: Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time. apability to (de)multiplex I/O signals. Fast access to SLI for decodes and PL-like functions. Output FF and two-signal function generator to reduce LK to output propagation delay. Fast open-drain drive capability. apability to register 3-state enable signal. aseline FPG family used in Series 3+ FPSs (fieldprogrammable system chips) which combine FPG logic and standard-cell logic on one device. * PL is a trademark of dvanced Micro evices, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table. OR Series 3 and 3T FPGs evice System Gates LUTs Registers Max User RM User I/Os rray Size Process Technology OR3T2 36K K 96 2 x 2.3 µm/4 LM OR3T3 48K K x 4.3 µm/4 LM OR3/3T55 8K K x 8.3 µm/4 LM OR3/3T8 6K K x 22.3 µm/4 LM OR3T25 86K K x 28.3 µm/4 LM The system gate counts range from a logic-only gate count to a gate count assuming 3% of the PFUs/SLIs being used as RMs. The logic-only gate count includes each PFU/SLI (counted as 8 gates/pfu), including 2 gates per LUT/FF pair (eight per PFU), and 2 gates per SLI/FF pair (one per PFU). Each of the four PIOs per PI is counted as 6 gates (three FFs, fast-capture latch, output logic, LK, and I/O buffers). PFUs used as RM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RM (or 52 gates) per PFU.

2 Preliminary Product rief OR Series 3 FPGs January 22 System-Level Features System-level features reduce glue logic requirements and make a system on a chip possible. These features in the OR OR3/Txxx include: Full PI local bus compliance. ual-use microprocessor interface (MPI) can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPG. Glueless interface to i96 * and PowerP processors with user-configurable address space provided. Parallel readback of configuration data capability with the built-in microprocessor interface. Programmable clock manager (PM) adjusts clock phase and duty cycle for input clock rates from 5 to 2. The PM may be combined with FPG logic to create complex functions, such as digital phase-locked loops (PLL), frequency counters, and frequency synthesizers or clock doublers. Two PMs are provided per device. True, internal, 3-state, bidirectional buses with simple control provided by the SLI. 32 x 4 RM per PFU, configurable as single- or dualport at >64 (-7 speed). reate large, fast RM/ ROM blocks (28 x 8 in only eight PFUs) using the SLI decoders as bank drivers. * i96 is a registered trademark of Intel orporation. PowerP is a registered trademark of International usiness Machines orporation. Table 2. OR OR3/Txxx System Performance Parameter # PFUs Speed Unit 6-bit Loadable Up/own ounter 6-bit ccumulator x 8 Parallel Multiplier: Multiplier Mode, Unpipelined ROM Mode, Unpipelined 2 Multiplier Mode, Pipelined x 6 RM (synchronous): Single-port, 3-state us 4 4 ual-port x 8 RM (synchronous): Single-port, 3-state us 4 8 ual-port bit ddress ecode (internal): Using Softwired LUTs.25 Using SLIs 6 32-bit ddress ecode (internal): Using Softwired LUTs 2 Using SLIs ns ns 36-bit Parity heck (internal) ns. Implemented using 8 x multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 6-bit output. 2. Implemented using two 32 x 4 RMs and one 2-bit adder, one 8-bit input, one fixed operand, one 6-bit output. 3. Implemented using 8 x multiplier mode (fully pipelined), two 8-bit inputs, one 6-bit output (7 of 5 PFUs contain only pipelining registers). 4. Implemented using 32 x 4 RM mode with read data on 3-state buffer to bidirectional read/write bus. 5. Implemented using 32 x 4 dual-port RM mode. 6. Implemented in one partially occupied SLI with decoded output set up to in same PL. 7. Implemented in five partially occupied SLIs. Note: Shaded values apply only to OR3Txxx devices. -4 speed grade applies only to OR3xx devices ns ns 2 Lattice Semiconductor

3 Preliminary Product rief January 22 OR Series 3 FPGs Support OR Foundry evelopment System support. Supported by industry-standard E tools for design entry, synthesis, simulation, and timing analysis. escription FPG Overview The OR Series 3 FPGs are a new generation of SRM-based FPGs built on the successful OR2/ Txx FPG (Series 2), with enhancements and innovations geared toward today s high-speed designs and tomorrow s systems on a single chip. esigned from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the OR Series 2 devices, the Series 3 family more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. OR Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. The OR Series 3 FPGs consist of three basic elements: programmable logic cells (PLs), programmable input/output cells (PIs), and system-level features. n array of PLs is surrounded by PIs. Each PL contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLI), local routing resources, and configuration RM. Most of the FPG logic is performed in the PFU (see Figure ), but decoders, PL-like functions, and 3-state buffering can be performed in the SLI (see Figure 2). The PIs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals (see Figure 3). Some of the system-level functions include the new microprocessor interface (MPI) and the programmable clock manager (PM). PL Logic Each PFU within a PL contains eight 4-input (6-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLI is connected to PL routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a -bit N function for decoding, or an N-OR with optional INVERT to perform PL-like functions. The 3-state drivers in the SLI and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPG, reducing required routing and allowing for realworld system performance. PI Logic The OR3/Txxx PI addresses the demand for everincreasing system clock speeds. Each PI contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fastcapture latch that is clocked by an ExpressLK. This latch is followed by a latch/ff that is clocked by a system clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two input signals are available to the PL array from each PIO, and the OR Series 2 capability to use any input pin as a clock or other global input is maintained. On the output side of each PIO, two outputs from the PL array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is very similar to the OR Series 2 buffer with a new, fast, open-drain option for ease of use on system buses. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered. Lattice Semiconductor 3

4 Preliminary Product rief OR Series 3 FPGs January 22 escription (continued) F5 K7_ K7_ K7_2 K7_3 K6_ K6_ K6_2 K6_3 K7 K6 F5MOE67 IN7 IN6 REG7 SEL REG6 SEL F7 Q7 F6 Q6 F5 K5_ K5_ K5_2 K5_3 K4_ K4_ K4_2 K4_3 F5 LK K5 K4 F5MOE45 IN5 IN4 REG5 SEL REG4 SEL Q5 F4 Q4 SEL IN OUT SWE FF8 REGOUT F5 K3_ K3_ K3_2 K3_3 K2_ K2_ K2_2 K2_3 K3 K2 F5MOE23 IN3 IN2 REG3 SEL REG2 SEL F3 Q3 F2 Q2 F K_ K_ K_2 K_3 K_ K_ K_2 K_3 F5 K K F5MOE IN IN REG SEL REG SEL Q F Q Note: ll multiplexers without select inputs are configuration selector multiplexers Figure. Simplified PFU iagram 4 Lattice Semiconductor

5 Preliminary Product rief January 22 OR Series 3 FPGs escription (continued) RI9 I9 LI9 RI8 I8 LI8 L9 R9 L8 R8 RI7 I7 LI7 L7 R7 RI6 I6 LI6 L6 R6 RI5 I5 LI5 RI4 I4 LI4 L5 R5 L4 R4 E TRI / / E HIGH Z WHEN LOW / RI3 I3 LI3 / L3 R3 RI2 I2 LI2 L2 R2 RI I LI L R RI I LI L R (F) Figure 2. SLI iagram (ll Modes) Lattice Semiconductor 5

6 Preliminary Product rief OR Series 3 FPGs January 22 escription (continued) System Features The Series 3 also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative programmable clock manager (PM). These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today s high-speed systems. The MPI provides a glueless interface between the FPG and PowerP and i96 microprocessors. It can be used for configuration and readback, as well as for monitoring FPG status. The MPI also provides a general-purpose microprocessor interface to the FPG user-defined logic following configuration. Two PMs are provided on each Series 3 device. Each PM can be used to manipulate the frequency, phase, and duty cycle of a clock signal. locks may be input from the dedicated corner ExpressLK input (in the same corner as the PM block) or from general routing. Output clocks from the PM can be sent to the system clock spines and/or to the ExpressLK and fast clock spines on the edges of the device adjacent to the PM. ExpressLK/fast clock and system clock output frequencies can differ by up to a factor of 8 to allow slow I/O clocking with fast internal processing (or vice versa). Each PM is capable of manipulating clocks from 5 to 2. Frequencies can be adjusted from /8x to 64x the input clock frequency, and duty cycles and phase delays can be adjusted from 3.25% to %. Routing The abundant routing resources of the Series 3 FPGs are organized to route signals individually or as buses with related control signals. locks are routed on a lowskew, high-speed distribution network and may be sourced from PL logic, externally from any I/O pad, or from the very fast ExpressLK pins. ExpressLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the new StopLK feature. The improved PI routing resources are now similar to the patented intra-pl routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins. onfiguration The FPG s functionality is determined by internal configuration RM. The FPG s internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RM is loaded by using one of several configuration modes. The configuration data resides externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin count method for configuring FPGs. new, easy method for configuring the devices is through the microprocessor interface. FROM ROUTING OUT OUT2 ELK SLK _OVER OVER_ SYN PIO LOGI N NN OR NOR XOR XNOR PMUX OUTOUTREG OUT2OUTREG OUTOUT2 Q SP TS RESET SET Q PULL-MOE UP OWN NONE P LEVEL MOE TTL UFFER MOS MOE FST SLEW SINK P ELK SLK NORML INVERTE INREGMOE LTHFF LTH FF Q Q SP S RESET SET LKIN IN IN2 TO ROUTING ENLE_GSR ISLE_GSR Figure 3. Series 3 Programmable Input/Output (PIO) Image from OR Foundry 5-585(F).c 6 Lattice Semiconductor

7 Preliminary Product rief January 22 OR Series 3 FPGs escription (continued) OR Foundry evelopment System The OR Foundry evelopment System is used to process a design from a netlist to a configured FPG. This system is used to map a design onto the OR architecture and then place and route it using OR Foundry s timing-driven tools. The development system also includes interfaces to, and libraries for, other popular E tools for design entry, synthesis, simulation, and timing analysis. The OR Foundry evelopment System interfaces to front-end design entry tools and provides the tools to produce a configured FPG. In the design flow, the user defines the functionality of the FPG at two points in the design flow: at design entry and at the bit stream generation stage. Following design entry, the development system s map, place, and route tools translate the netlist into a routed FPG. static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation. Timing and simulation output files from OR Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPG s internal configuration RM. When using the bit stream generator, the user selects options that affect the functionality of the FPG. ombined with the front-end tools, OR Foundry produces configuration data that implements the various logic and routing options discussed in this product brief. dditional Information ontact your local Lattice representative for additional information regarding the OR Series 3 FPG devices, or visit our website at Lattice Semiconductor 7

8 Preliminary Product rief OR Series 3 FPGs January 22 Ordering Information Example: EVI TYPE SPEE GRE OR38-4 PS 24 TEMPERTURE RNGE NUMER OF PINS PGE TYPE OR38, -4 Speed Grade, 24-pin Power Quad Shrink Flat Package (SQFP2), ommercial Temperature. Table 3. Voltage Options evice OR3xx OR3Txxx Voltage 5. V 3.3 V Table 4. Temperature Options Symbol escription Temperature (lank) ommercial to 7 I Industrial 4 to +85 Table 5. Package Options Symbol PS S escription Plastic all Grid rray (PG) Enhanced all Grid rray (EG) Power Quad Shrink Flat Package (SQFP2) Shrink Quad Flat Package (SQFP) Table 6. OR Series 3 Package Matrix Packages 28-Pin EIJ SQFP Note: = commercial, I = industrial. 28-Pin EIJ/SQFP2 24-Pin EIJ SQFP 24-Pin EIJ/SQFP2 256-Pin PG 352-Pin PG 432-Pin EG 6-Pin EG S28 PS28 S24 PS OR3T2 l I I I OR3T3 I I I I OR3/T55 I I I I OR3/T8 I I I I OR3T25 I I I I I opyright 22 Lattice Semiconductor ll Rights Reserved Printed in U.S.. January 22 PN99-58FPG (Replaces PN98-2FPG)

Optimized Reconfigurable Cell Array (ORCA ) OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays

Optimized Reconfigurable Cell Array (ORCA ) OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays Preliminary Product rief November 997 Optimized Reconfigurable ell rray (OR ) OR3xxx/OR3Txxx Series Field-Programmable Gate rrays Features High-performance, cost-effective,.35 µm 4-level metal technology,