ECE 448 Lecture 5. FPGA Devices

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1 E 448 Lecture 5 FPGA evices E 448 FPGA and ASIC esign with VHL George Mason University

2 Required reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional etails 2

3 What is an FPGA? Configurable Logic Blocks Block RAMs Block RAMs I/O Blocks Block RAMs E 448 FPGA and ASIC esign with VHL 3

4 Modern FPGA RAM blocks Multipliers Multipliers/SP units Logic Logic resources blocks (#Logic resources, #Multipliers/SP units, #RAM_blocks) Graphics based on The esign Warrior s Guide to FPGAs evices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 4

5 Major FPGA Vendors AM-based FPGAs Xilinx, Inc. ~ 51% of the market ~ 85% Intel ~ 34% of the market (until 2015, Altera Corp.) Lattice Semiconductor Atmel (since 2016, subsidiary of Microchip Technology) Achronix Semiconductor Tabula (went out of business in 2015) Flash & antifuse FPGAs Microsemi SoC Products Group (until 2010 Actel) uick Logic Corp. E 448 FPGA and ASIC esign with VHL 5

6 Xilinx u Primary products: FPGAs and the associated CA software Programmable Logic evices CA Software u u Main headquarters in San Jose, CA Fabless* Semiconductor and Software Company u TSMC (Taiwan) u UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} u Seiko Epson (Japan) u Samsung (Korea) E 448 FPGA and ASIC esign with VHL 6

7 Technology Low-cost Mid-range High-performance 220 nm Virtex 180 nm Spartan-II, Spartan-IIE 120/150 nm Virtex-II, Virtex-II Pro 90 nm Spartan-3 Virtex-4 65 nm Virtex-5 45 nm Spartan-6 Xilinx FPGA Families 40 nm Virtex-6 28 nm Artix-7 Kintex-7 Virtex-7 20 nm Kintex UltraSCALE 16 nm Kintex UltraSCALE+ Virtex UltraSCALE Virtex UltraSCALE+

8 FPGA Family 8

9 Artix-7 FPGA Family E 448 FPGA and ASIC esign with VHL 9

10 CLB Structure E 448 FPGA and ASIC esign with VHL George Mason University

11 General structure of an FPGA Programmable interconnect Programmable logic blocks The esign Warrior s Guide to FPGAs evices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( E 448 FPGA and ASIC esign with VHL 11

12 Xilinx Artix-7 CLB E 448 FPGA and ASIC esign with VHL 12

13 Row & Column Relationship Between CLBs & Slices E 448 FPGA and ASIC esign with VHL 13

14 14 A6:A1 COUT X C CX B BX A AX O6 O5 X MUX C C CMUX B B BMUX A A AMUX Reset Type FF/LAT HI LO FF/LAT HI LO FF/LAT HI LO FF/LAT HI LO CIN 0/1 Sync/Async FF/LAT A6:A1 O6 O5 C6:1 CX 6:1 A6:A1 O6 O5 B6:1 BX A6:A1 O6 O5 A6:1 AX CLK HI LO HI LO HI LO HI LO Basic Components of the Slice LUTs Storage Elements

15 Example of a 4-input LUT (Look-Up Table) (used in earlier families of FPGAs) x 1 x 2 x 3 x y x 1 x 2 x 3 x 4 LUT y x 1 x 2 x 3 x 4 x 1 x 2 x 3 x y Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs x 1 x 2 y y E 448 FPGA and ASIC esign with VHL 15

16 LUT of Artix-7 E 448 FPGA and ASIC esign with VHL 16

17 X LUT O5 Output FF HIGH LOW X LUT Output FF/LATCH FF LATCH HIGH LOW CX LUT C O5 Output CFF HIGH LOW C CX LUT C Output CFF/LATCH FF LATCH HIGH LOW C LUT B O5 Output BFF Reset Type Sync Async LUT B Output BFF/LATCH Reset Type Sync Async BX CLK HIGH LOW B BX CLK FF LATCH HIGH LOW B AX LUT A O5 Output AFF HIGH LOW A AX LUT A Output AFF/LATCH FF LATCH HIGH LOW A UG474_c2_04_

18 Reset and Set Configurations No set or reset Synchronous set Synchronous reset Asynchronous set (preset) Asynchronous reset (clear) E 448 FPGA and ASIC esign with VHL 18

19 Two ifferent Types of Slices in Artix-7 E 448 FPGA and ASIC esign with VHL 19

20 20 SLIL A6:A1 COUT X C CX B BX A AX O6 O5 UG474_c2_03_ X MUX C C CMUX B B BMUX A A AMUX Reset Type FF/LAT HI LO FF/LAT HI LO FF/LAT HI LO FF/LAT HI LO CIN 0/1 Sync/Async FF/LAT A6:A1 O6 O5 C6:1 CX 6:1 A6:A1 O6 O5 B6:1 BX A6:A1 O6 O5 A6:1 AX CLK HI LO HI LO HI LO HI LO

21 Fast Carry Logic u u Each SliceL and SliceM contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Carry logic is independent of normal logic and routing resources MSB LSB Carry Logic Routing 21

22 Accessing Carry Logic u All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (IFF <= A - B) Comparators (if A < B then ) Counters (count <= count +1) 22

23 COUT (To Next Slice) Carry Chain Block (CARRY4) O6 From LUT S3 MUXCY CO3 MUX/* O5 From LUT X I3 O3 MUX (Optional) O6 From LUTC S2 MUXCY CO2 CMUX/C* O5 From LUTC CX I2 O2 CMUX C (Optional) O6 From LUTB S1 MUXCY CO1 BMUX/B* O5 From LUTB BX I1 O1 BMUX B (Optional) O6 From LUTA S0 MUXCY CO0 AMUX/A* O5 From LUTA AX I0 O0 AMUX A CYINIT CIN (Optional) 0 1 CIN (From Previous Slice) *Can be used if unregistered/registered outputs are free. UG474_c2_23_

24 24 SLIM X-Ref Target - Figure 2-3 A6:A1 COUT X C CX B BX A AX O6 I2 O5 I1 MC31 WEN I1 MC31 WEN I1 MC31 WEN I1 MC31 WEN UG474_c2_02_ X MUX C C CMUX B B BMUX A A AMUX Reset Type FF/LAT HI LO FF/LAT HI LO FF/LAT HI LO FF/LAT HI LO CIN 0/1 WEN WE Sync/Async FF/LAT A6:A1 O6 O5 C6:1 CX 6:1 I A6:A1 O6 O5 B6:1 BX A6:A1 W6:W1 W6:W1 W6:W1 W6:W1 O6 O5 A6:1 AX CLK HI LO HI LO HI LO HI LO I2 I2 I2 CI BI AI

26 Single-port 64 x 1-bit RAM 26

27 Single-port 64 x 1-bit RAM 27

28 Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: Single-port 128 x 1-bit RAM: RAM128x1S ual-port 64 x 1-bit RAM : RAM64x1 Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S ual-port 128 x 1-bit RAM: RAM128x1 uad-port 64 x 1-bit RAM: RAM64x1 Simple-dual-port 64 x 3-bit RAM: RAM64x3SP (one address for read, one address for write) 28

29 ual-port 64 x 1 RAM ual-port 64 x 1-bit RAM : 64x1 Single-port 128 x 1-bit RAM: 128x1S 29

30 ual-port 64 x 1 RAM ual-port 64 x 1-bit RAM : 64x1 Single-port 128 x 1-bit RAM: 128x1S E 448 FPGA and ASIC esign with VHL 30

31 Total Size of istributed RAM in Artix-7 31

32 MLUT as a 32-bit Shift Register (L32) E 448 FPGA and ASIC esign with VHL 32

33 Input/Output Blocks (IOBs) E 448 FPGA and ASIC esign with VHL George Mason University

34 Basic I/O Block Structure Three-State FF Enable Clock Set/Reset Output FF Enable EC EC Three-State Control Output Path irect Input FF Enable Registered Input EC Input Path E 448 FPGA and ASIC esign with VHL 34

35 IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed E 448 FPGA and ASIC esign with VHL 35

36 Family Attributes E 448 FPGA and ASIC esign with VHL George Mason University

37 Artix-7 FPGA Family E 448 FPGA and ASIC esign with VHL 37

38 FPGA device present on the igilent Nexys 4 R board XC7A35T- 1CPG236C Artix-7 family Size Speed Grade Package type 236 pins Commercial temperature range 0 C 85 C E 448 FPGA and ASIC esign with VHL 38

39 FPGA esign Process 39

40 FPGA esign process (1) esign and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds.. Specification / Pseudocode On-paper hardware design (Block diagram & ASM chart) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; VHL description (Your Source Files) Functional simulation Synthesis Post-synthesis simulation

41 FPGA esign process (2) Implementation Timing simulation Results Configuration On chip testing

42 Synthesis George Mason University

43 Logic Synthesis VHL description Circuit netlist architecture MLU_ATAFLOW of MLU is signal A1:ST_LOGIC; signal B1:ST_LOGIC; signal Y1:ST_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: ST_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; end MLU_ATAFLOW; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; 43

44 Circuit netlist (RTL view) 44

45 Implementation George Mason University

46 Mapping LUT0 FF1 LUT1 LUT2 FF2 46

47 Placing FPGA CLB SLIS 47

48 Routing FPGA Programmable Connections 48

49 Synthesis Two main stages of the FPGA esign Flow Implementation Technology independent Technology dependent RTL Synthesis Map Place & Route Configure - Code analysis - erivation of main logic constructions - Technology independent optimization - Creation of RTL View - Mapping of extracted logic structures to device primitives - Technology dependent optimization - Application of synthesis constraints -Netlist generation - Creation of Technology View - Placement of generated netlist onto the device -Choosing best interconnect structure for the placed design -Application of physical constraints - Bitstream generation - Burning device

ECE 545 Lecture 12. FPGA Resources. George Mason University

ECE 545 Lecture 12. FPGA Resources. George Mason University ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks