FYSE420 DIGITAL ELECTRONICS. Lecture 7

Transcription

1 FYSE420 DIGITAL ELECTRONICS Lecture 7 1 [1] [2] [3] DIGITAL LOGIC CIRCUIT ANALYSIS & DESIGN Nelson, Nagle, Irvin, Carrol ISBN DIGITAL DESIGN Morris Mano Fourth edition ISBN Digital Design Principles and Practices Fourth edition Wakerly John F. ISBN

2 A high complexity of integrated circuits poses an enormous design challenge. Computer aided design Well-established design methodologies The rate of technology advancement depends on the absorption bandwidth of the design community The rate of the IC-manufacturing development The correct operation of the designed circuit. The productivity of the design teams The IC-complexity is growing faster than the productivity Design gap 3 Complexity Logic transistors per chip Productivity Trans./Staff-month µ Complexity µ Productivity µ Design productivity gap 4

3 Digital Circuit Implementation Approaches Custom Semicustom Cell based Array based Standard cells Compiled cells Macro cells Pre-wired (FPGA s,..) Prediffused (Gate arrays) The preferred approach to mapping a function onto silicon depends largely upon the function itself. Pre-wired arrays 5 By using the prewired arrays the IC manufacturing time can be reduced to zero in desk to market time. The prewired array of cells is called a field-programmable gate array, FPGA The implementation can be performed at the user site with negligible turnaround time. The time from desk to market The logical design of digital system Cell based The manufacturing of IC Pre-diffused Semicustom Unprogrammed FPGAs from IC vendor Pre-wired FPGA 6

4 (OTP) Fuse-based FPGA The nonvolatile FPGA The volatile FPGA Antifuse based Fuse based Short-circuited by default EEPROM (Electrically Erasable Programmable Read-Only Memory) Flash memory RAM-based FPGA FPGA do not have special manufacturing process requirements (regular CMOS process). Open-circuited by default 7 Fuse-based FPGA Advantage Fuse based Memory cell is very small Resistance of the short-circuited fuse is low Disadvantage One-time programmable Reliable simulation A new component is required for every design change 8

5 Fuse-based FPGA Antifuse based A thin layer (<10nm) of ONO (oxide-nitride-oxide) dielectric is deposited between conducting polysilicon and diffusion layers. The circuit is open by default. Large programming current through it. ONO dielectric The current causes the dielectric to melt Antifuse polysilicon A permanent connection with fixed resistance (about 300Ω). n + antifuse diffusion 9 Fuse-based FPGA Antifuse based In an amorphous-silicon based FPGA, the two layers of metal are separated by amorphous silicon, which provides electrical insulation. A programming pulse of 10V to 12V across the via Metal Via SiO 2 Conductive link with a resistance of about 50Ω. Link Amorphous-silicon antifuse element 10

6 The nonvolatile FPGA Advantage Once programmed, the logic remains functional and fixed until new programming round. Memory retains its value even when the supply voltage is turned off. Disadvantage Disadvantage of this approach is that nonvolatile memories require special steps in the manufacturing process. High programming/erasure voltage (>10V) 11 The volatile FPGA Advantage Ram-Based FPGA FPGA do not have special manufacturing process requirements (regular CMOS process). Logic can be modified on the fly. Disadvantage The reloading of the configuration from an external permanent memory is necessary every time the part is turned on. The size of the memory cells with pass transistors is large. The resistance of the interconnection switch is high (about 1000Ω). 12

7 The volatile FPGA Ram-Based FPGA Select Programming bit Interconnect switch SRAM cell 13 The volatile FPGA Ram-Based FPGA The six SRAM controlled pass transistors N SRAM cell W E S 14

8 A complex circuit implementation Programmable Logic * Array-Based Programmable Logic * Cell-Based Programmable Logic Programmable Interconnection * Array-Based Programmable Wiring * Switch-Box-Based Programmable Wiring 15 Array-Based Programmable Logic Programmable logic array (PLA) I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array AND and OR planes can be programmed by selectively enabling connections. AND plane Sum-of-product format (SOP). Required minterms OR plane The set of selected minterms Programmable AND array O 3 O 2 O 1 O 0 16

9 Array-Based Programmable Logic PROM architecture I 3 I 2 I 1 I 0 Programmable OR array In PROM architecture the AND plane is fixed and enumerates all possible minterms. Spend die area Fixed AND array O 3 O 2 O 1 O 0 17 Array-Based Programmable Logic Programmable array logic (PAL) I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array OR plane is fixed and the AND plane is programmable. Note! To realize the complete, sequential subdesigns, the presence of registers and/or flip-flops is an absolute requirement. Programmable logic devices PLDs : PLA, PROM, PAL Programmable AND array O 3 O 2 O 1 O 0 18

10 Array-Based Programmable Logic programmable AND array 2i (2x i 3jk jk) k macrocells 1 product terms j -wide OR array j D Q OUT j A B C i i inputs CLK macrocell PAL A single register in macrocell can be programmed also : D, T, JK, or clocked SR flip-flop Partition the array into a number of smaller sections : macrocells introduce flip-flops and provide a potential feedback from output to the inputs. 19 Array-Based Programmable Logic The PLA approach has two distinct advantages: Structure is very regular. Estimation of the parasitics is quite easy. Accurate predictions of area, speed, and power dissipation. Efficient implementation of two-level logic description (functions with large fan-in). For example finite-state machines used in controllers and sequencers. Disadvantages: High overhead. Every intermediate node has sizable capacitance (lower performance and higher power dissipation). These are true especially when parts of array are underutilized (only some of the minterms are only used). 20

11 Cell-Based Programmable Logic Small logic block that can be configured to perform a wide range of logic functions. Array-based programmable logic Fits better in the multilevel logic. Fits poorly in the multilevel logic. Logic functions with large fan-out. Multilevel logic implementation such as addition and multiplication. 21 Cell-Based Programmable Logic A 0 F = AS + BS Configuration A B S F= F 0 X 1 X 0 Y 1 Y B 1 0 Y X XY X 0 Y XY S Y 0 X XY Y 1 X X + Y The multiplexer as a function generator 1 0 X X 1 0 Y Y

12 Cell-Based Programmable Logic The logic cell of Actel ACT family of FPGAs consists of three two-input multiplexers and two-input NOR gate. A B 1 Any two- or three input logic function, some four-input Boolean functions, and a latch. SA C 1 Y D 1 SB S0 S1 Logic Cell of Actel Fuse-Based FPGA 23 Cell-Based Programmable Logic Lookup table method In Out Out Memory ln1 ln2 Lookup table LUT 24

13 Cell-Based Programmable Logic C 1...C 4 4 H 1 xxxx xxxx xxxx Xilinx 4000 Series G 4 G 3 G 2 G 1 F 4 F 3 F 2 F 1 K (clock) Logic function of F1-F4 Logic function of F1-F4 Logic function x of xxx Multiplexer Controlled by Configuration Program xx xx xx xx x H P xx xx xx xx 1 1 S/R control S/R control D SD Q EC RD D SD Q EC RD LUT-based logic cell of the XILINX XC4000 series. xxxx YQ Y xxxx XQ x 25 Programmable Interconnect Requirements The interconnect network must be flexible and routing bottlenecks must be avoided. Short interconnection delays. High performance Good question! Low power consumption. How to get these features? One-time programmable Fuse and antifuse Reprogrammable SRAM, EEPROM 26

14 Programmable Interconnect Array-Based Programmable Wiring Programmed interconnection Input/output pin Cell M tracks Pass transistor Vertical tracks 27 Programmable Interconnect Switch-Box-Based Programmable Wiring Programmable meshbased interconnect network. Switch Box Connect Box Interconnect Point 28

15 Programmable Interconnect Switch-Box-Based Programmable Wiring Transistor-level schematic diagram. Mesh-based interconnection network is quite efficient for local connections, but unefficient for global interconnections. * Delay * Large capacitive load 29 Programmable Interconnect Switch-Box-Based Programmable Wiring Wire with doubled pitch We can include long wires that connect every second, 4 th, 8 th, or 16 th switch matrix (S-box). * Decreased interconnection resistance. * Shorter delay. 30

16 Altera Actel Xilinx Quicklogic FPGA: *Stratix *Cyclone *Stratix GX *APEX II *APEX 20K *Mercury *FLEX 10K *ACEX 1K *FLEX 6000 CPLD: *MAX 3000A *MAX 7000 Reprogrammable Flash FPGAs: *ProASICplus *ProASIC Antifuse Devices: *Axcelerator *SX-A / SX *ex *MX FPGA: *VirtexIIIPro *VirtexII *VirtexE *Virtex *Spartan 3 *SpartanIIE *SpartanII *SpartanXL *Spartan CPLD: *CoolRunner *XC9500 family FPGA: *Eclipse *Eclipse-II *pasic *pasic 1 *pasic 2 *pasic 3 *QuickRAM 31 The End 32