ELE432. ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Introduction and FPGA issues

Transcription

1 ELE432 ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Introduction and FPGA issues

2 Organization of the course Course Basics Group Project and Labs Course Contents 1. Embedded World and FPGA Introduction (NOW) 2. FPGA Design Flow and VHDL 3. Review of Sequential and Combinational Logic 4. Lab Introduction VHDL and FPGA A simple combinational implementation 5. FSM Design and ALU Design 6. Lab FSM Design and ALU Design a sequential experiment / A control unit implementation 7. Memory Implementations 8. Implementation of a small microprocessor Design 9. Lab Small Processor design 10. Pipelining for advanced microprocessor design 11. Using the HPC on the FPGA 12. Lab interfacing a peripheral (accelerometer, vs. ) 13. Soft IP core implementation NIOS II Softcore processor 14. Project

3 Syllabus Details are at the web page: for updated slides etc. Must be enrolled in the student information HU EE ASSOC. PROF. DR. ALI ZIYA ALKAR DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING BEYTEPE ANKARA TURKEY PHONE: You can take the course if -> you are a Senior EE students who have performed well (C1 and above) in ELE237 Digital Design, ELE336 Microprocessor Programming and Architecture courses. you can spend extra hours (not necessarily during course times) for Labs and Term Project. Why you need to take the course if -> you would like to expertise yourself in computer architecture and digital design field. you would like to learn about cutting edge state-of-the-art technology in the digital design. Grading you are a Senior EE students who have performed well (C1 and above) in ELE237 Digital Design, ELE336 Microprocessor Programming and Arch Final exam %35, Project %35, Laboratories (1+3) graded %30

4 Some useful resources The Design Warrior s Guide to FPGAs, Clive Maxfield Digital Design with CPLD Applications and VHDL, 2E Robert Dueck Digital Design, Principles & Practices, J.F. Wakerly, 4th Edition (Sept 05) Prentice Hall "High-Speed Digital Design - A handbook of black magic", Johnson, Graham. Practical guide to designing and building very high speed digital circuits. "Contemporary Logic Design" Gaetano Boriello, Randy H. Katz, Prentice Hall,

5 DE1-SOC board DE1-SoC Board Information The DE1-SoC box includes: The 6.5 x 5 inch DE1-SoC board with a Cyclone V 5CSEMA5 (896-pin package) FPGA 12V AC/DC adaptor USB cable Micro-USB cable Plexiglas cover for the DE1-SoC board Quick start guide Feature Description FPGA Cyclone V SoC 5CSEMA5F31 with EPCQ Mbit serial configuration device I/O Interfaces Memory Displays Switches and LEDs Clocks Built-in USB-Blaster for FPGA configuration Line In/Out, Microphone In (24-bit Audio CODEC) Video Out (VGA 24-bit DAC) Video In (NTSC/PAL/Multi-format) Infrared port 10/100/1000 Ethernet Two Port USB 2.0 Host (Type A) PS/2 dual mouse and keyboard port Expansion headers (two 40-pin headers) 1GB DDR3 SDRAM (HPS), 64 MB SDRAM (FPGA) Micro SD memory card slot Six 7-segment displays 10 toggle switches 10 LEDs Four debounced pushbutton switches 50 MHz clock (x4)

6 The Booming of Semiconductor Industry $300 billion industry Electronics is everywhere in our lives Cell phones, cars, buildings Medical, social, e-commerce Military, security, aerospace

7 Billions of transistors

8 Technology Timeline

9 PLD

10 UNPROGRAMMED PROM

11 Simple Combinational Logic Programming

12 Programmed PROM

13 PLA

14 PAL/GAL

15 SPLD -> CPLD

16 ASIC

17 Full Custom In the case of full-custom devices, design engineers have complete control over every mask layer used to fabricate the silicon chip. By means of appropriate tools, the engineers can handcraft the dimensions of individual transistors and then create higher-level functions based on these elements The design of full-custom devices is highly complex and timeconsuming, but the resulting chips contain the maximum amount of logic with minimal waste of silicon real estate.

18 ASIC Gate Arrays Components (Basic Cells) pre fabricated on chip.

19 Gate Array Technology (IBM s) Simple logic gates combine transistors to implement combinational and sequential logic Interconnect wires to connect inputs and outputs to logic blocks I/O blocks special blocks at periphery for external connections Add wires to make connections done when chip is fabbed mask-programmable construct any circuit Xilinx FPGAs - 19

20 ASIC Standard Cells Nothing pre-fabricated Libraries are provided by the factory Reuse of reuse previously designed functions or to purchase blocks of intellectual property (IP). Dynamic Routing while designing

21 ASIC Structured ASIC Tiles of gates/mux s/flops Overhead in silicon, performance and power compared to Standard Cell

22 ASIC Structured ASIC The idea is that the device can be customized using only the meta lization layers (just like a standard gate array). The difference is that, due to the greater sophistication of the structured ASIC tile, most of the metallization layers are also predefined. Many structured ASIC architectures require the customization of only two or three metallization layers This dramatically reduces the time and costs associated with creating the remaining photo-masks used to complete the device

23 ASIC vs FPGA 1. cost of development, sometimes called non-recurring engineering (NRE) 2. cost of manufacture total costs A B NRE number of units manufactured (volume) performance NREs Unit cost TTM ASIC ASIC FPGA ASIC FPGA MICRO FPGA MICRO MICRO ASIC FPGA MICRO

24 The Gap = FPGA Cheap & fast but not too complex expensive and slow but complex

25 FPGA Variations Families of FPGA s differ in: physical means of implementing user programmability, arrangement of interconnection wires, and the basic functionality of the logic blocks. Anti-fuse based (ex: Actel) Latch-based (Xilinx, Altera, ) latch + Non-volatile, relatively small fixed (non-reprogrammable) +reconfigurable volatile relatively large.

26 FPGA Variations

27 FPGA

28 A simple Logic Block in FPGA Each CLB (or programmable logic block) can be programmed to perform a certain function MUX can be used to select either d or output of the LUT Flip flop can be triggered either for L-H or H-L transition

29 Configuring a LUT

30 An Implementation of a LUT

31 Top-down view of FPGA

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33 FPGA Architecture simplified

34 Features and Specifications of the FPGA MUX based approaches

35 Features and Specifications of the FPGA LUT based approach and implementation

36 LUT vs. MUX If you take a group of logic gates several layers deep, then a LUT approach can be very efficient in terms of resource utilization and input-to-output delays. (In this context, deep refers to the number of logic gates between the inputs and the outputs. However, one downside to a LUT-based architecture is that if you only want to implement a small function such as a 2-input AND gate somewhere in your design, you ll end up using an entire LUT to do so. In addition to being wasteful in terms of resources, the resulting delays are high for such a simple function.

37 Features and Specifications of the FPGA Slices formed of Logic Cells. LC->Slice (with two LCs)->CLB (with four slices) is that it is complemented by an equivalent hierarchy in the interconnect. Thus, there is fast interconnect between the LCs in a slice, then slightly slower interconnect between slices in a CLB, followed by the interconnect between CLBs. The idea is to achieve the optimum trade-off between making it easy to connect things together without incurring excessive interconnect-related delays.

38 Distributed RAM s Assuming a 4-input LUT we can have a 16x1 RAM 4 slices (with each slices having two logic cells) per CLB corresponds to:

39 Fast Carry Chains Each LC is connected within each slice. Slices are connected with each other in CLB s. CLB s are also connected with carry chains. With the addition of embedded multipliers in FPGA fabric Makes it suitable for DSP applications

40 RAM Implementation A lot of apps now need RAM built into the FPGA. Depending on the device, such a RAM might be able to hold anywhere from a few thousand to tens of thousands of bits. Furthermore, a device might contain anywhere from tens to hundreds of these RAM blocks, thereby providing a total storage capacity of a few hundred thousand bits all the way up to several million bits. These may be scattered around or mostly in blocks.

41 Embedded multipliers, adders, MACs, etc. Some functions, like multipliers, are inherently slow if they are implemented by connecting a large number of programmable logic blocks together. Since these functions are required by a lot of applications, many FPGAs incorporate special hardwired multiplier blocks. These are typically located in close proximity to the embedded RAM blocks introduced in the previous point because these functions are often used in conjunction with each other

42 MAC block implementation Some FPGAs offer dedicated adder blocks. One operation that is very common in DSP-type applications is called a multiply-andaccumulate (MAC)

43 IP? An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation ( EDA ) industry trend towards repeated use of previously designed components. Universal Asynchronous Receiver/Transmitter (UARTs), central processing units (CPUs), Ethernet controllers, and PCI interfaces are all examples of IP cores. IP cores fall into one of three categories: hard cores, firm cores, or soft cores. Hard cores are physical manifestations of the IP design. These are best for plug-and play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement data but are configurable to various applications. Firm-cores are encrypted black boxes that are integrated into design flow in the same way as library elements The most flexible of the three, soft cores exist either as a netlist (a list of the logic gate s and associated interconnections making up an integrated circuit ) or hardware description language ( HDL ) code.

44 Embedded processor cores (hard and soft) an electronic design can be realized in hardware (using logic gates and registers, etc.) or software (as instructions to be executed on a microprocessor). Picosecond and nanosecond logic: This has to run insanely fast, which mandates that it be implemented in hardware (in the FPGA fabric). Microsecond logic: This is reasonably fast and can be implemented either in hardware or software (this type of logic is where you spend the bulk of your time deciding which way to go). Millisecond logic: This is the logic used to implement interfaces such as reading switch positions and flashing light-emitting diodes (LEDs). It s a pain slowing the hardware down to implement this sort of function (using huge counters to generate delays, for example). Thus, it s often better to implement these tasks as microprocessor code (because processors give you lousy speed compared to dedicated hardware but fantastic complexity).

45 Embedded processor cores (hard) high-end FPGAs have become available that contain one or more embedded microprocessors, which are typically referred to as microprocessor cores. A hard microprocessor core is implemented as a dedicated, predefined block. There are two main approaches for integrating such a core into the FPGA. The first is to locate it in a strip (actually called The Stripe ) to the side of the main FPGA fabric

46 Embedded processor cores (hard) Hard IP cores ROM, RAM, FIFO RISC CPU DSP Multiplier Flash memory (boot, user) PCI, PCIe JTAG

47 Embedded processor cores (hard)

48 Embedded processor cores (soft) As opposed to embedding a microprocessor physically into the fabric of the chip, it is possible to configure a group of programmable logic blocks to act as a microprocessor. Soft cores are simpler (more primitive) and slower than their hard-core counterparts.2 However, they have the advantage that you only need to implement a core if you need it and also that you can instantiate as many cores as you require until you run out of resources in the form of programmable logic blocks.

49 Embedded processor cores (soft) PCI master-target, 32/64 bit, PCIe Ethernet, UART μp, μc (incl. old ones), RISC CPUs Interface to DRAM, SSRAM DSP: CORDIC, DDS, FFT, Filters VME, USB, CAN, I2C, SPI, SD card encryption / decryption

50 Sources of IP 1. Internally created blocks from previous designs, 2. FPGA vendors, 3. Third-party IP providers.

51 Handcrafted IP One scenario is that the IP provider has handcrafted an IP block starting with an RTL description also have used an IP block/core generator application In this case, there are several ways in which the end user might purchase and use such a block

52 IP at the unencrypted RTL level In certain cases, FPGA designers can purchase IP at the RTL level as blocks of unencrypted source code. These blocks can then be integrated into the RTL code for the body of the design (a). These are already simulated, synthesized, and verified the IP blocks before handing over the RTL source code). This is an expensive option because IP providers typically don t want anyone to see their RTL source code. The IP provider may charge you an arm and a leg, and you ll end up signing all sorts of licensing and nondisclosure agreements (NDAs)

53 IP at the unplaced-and-unrouted netlist level Perhaps the most common scenario is for FPGA designers to purchase IP at the unplaced-and-unrouted LUT/CLB netlist level (b) Such netlists are typically provided in encrypted form, either as encrypted EDIF or using some FPGA vendor-specific format One disadvantage is that the FPGA designer doesn t have any ability to remove unwanted functionality. Another disadvantage is that the IP block is tied to a particular FPGA vendor and device family.

54 IP at the placed-and-routed netlist level In certain cases, the FPGA designer may purchase IP at the placed-and-routed LUT/CLB netlist level Such netlists are typically provided in encrypted form, either as encrypted EDIF or using some FPGA vendor-specific format The reason for having placed-and-routed representations is to obtain the highest levels of performance. In some cases the placements will be relative, which means that the locations of all of the LUT, CLB, and other elements forming the block are fixed with respect to each other, but the block as a whole may be positioned anywhere (suitable) within the FPGA.

55 IP core generators Another very common practice is for FPGA vendors (sometimes EDA vendors, IP providers, and even small, independent design houses) to provide special tools that act as IP block/core generators. These generator applications are parameterized, thereby allows to specify the widths and depths, or both of buses and functional elements. First, you get to select from a list of different blocks/cores, and then you get to specify the parameters to be associated with each. In the case of some blocks/cores, the generator application may allow you to select from a list of functional elements that you wish to be included or excluded from the final representation. In the case of a communications block, for example, it might be possible to include or exclude certain error-checking logic. Or in the case of a CPU core, it might be possible to omit certain instructions or addressing modes. This allows the generator application to create the most efficient IP block/core in terms of its resource requirements and performance.

56 IP core generators Depending on the origin of the generator application (or sometimes the licensing option you ve signed up for), its output may be in the form of encrypted or unencrypted RTL source code, an unplaced-and-unrouted netlist, or a placedand- routed netlist.

57 Clock trees and clock managers All of the synchronous elements inside an FPGA for example, the registers configured to act as flipflops inside the programmable logic blocks need to be driven by a clock signal. Such a clock signal typically originates in the outside world, comes into the FPGA via a special clock input pin, and is then routed through the device and connected to the appropriate registers. This is called a clock tree because the main clock signal branches again and again (the flip-flops can be consider, to be the leaves on the end of the branches). This structure is used to ensure that all of the flip-flops see their versions of the clock signal as close together as possible. If the clock were distributed as a single long track driving all of the flip-flops one after another, then the flip-flop closest to the clock pin would see the clock signal much sooner than the one at the end of the chain. This is referred to as skew, and it can cause all sorts of problems

58 Clock managers Phase shifting Auto-skew correction: Jitter removal Freq. Synthesis

59 General-purpose I/O Each bank can be configured individually to support a particular I/O standard. In addition to allowing the FPGA to work with devices using multiple I/O standards, this allows the FPGA to actually be used to interface between different I/O standards today s FPGAs allow the use of internal terminating resistors whose values can be configured by the user to accommodate different circuit board environments and I/O standards. different I/O standards may use signals with voltage levels significantly different from the core voltage, so each bank of generalpurpose I/Os can have its own additional supply pins.

60 Communication with the FPGA

61 Gigabit transceivers

62 Programming an FPGA configuration file (sometimes called a bit file), which contains the information that will be uploaded into the FPGA in order to program it to perform a specific fun In the case of SRAM-based FPGAs, the configuration file contains a mixture of configuration data (bits that are used to define the state of programmable logic elements directly) and configuration commands (instructions that tell the device what to do with the configuration data). When the configuration file is in the process of being loaded into the device, the information being transferred is referred to as the configuration bitstream.

63 Programming an FPGA The underlying concept associated with programming an FPGA is relatively simple (i.e., load the configuration file into the device).

64 Programming an FPGA these devices are volatile, which means that they have to be programmed in-system (on the circuit board), and they always need to be reprogrammed when power is first applied to the system.

65 Programming an FPGA From the outside world, we can visualize all of the SRAM configuration cells as comprising a single (long) shift register. Consider a simple bird s-eye view of the surface of the chip showing only the I/O pins/pads and the SRAM configuration cells

66 Programming an FPGA The problem is that an FPGA can contain a humongous number of configuration cells. By 2003, for example, a reasonably high-end device could easily contain 25 million such cells! The core of a flip-flop requires eight transistors, while the core of a latch requires only four transistors. For this reason, the configuration cells in an SRAM-based FPGA are formed from latches.

67 Programming an FPGA

68 Programming an FPGA

69 Programming an FPGA

70 Programming an FPGA

71 Programming an FPGA

72 Programming an FPGA

73 Who are the players?

74

75 Age of an FPGA 1 human year = 15 years in FPGA years