Computer Structure. Unit 2: Memory and programmable devices

Transcription

1 Computer Structure Unit 2: Memory and programmable devices Translated from Francisco Pérez García (fperez at us.es) by Mª Carmen Romero (mcromerot at us.es, Office G1.51, ) Electronic Technology Department University of Seville (February 2012)

2 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. Bibliography: Floyd. Digital Fundamentals. 10th Ed. (Ch.10, Ch.11) 2

3 1. Basic concepts Computer requires to store a huge amount of binary data permanently. Systems based on microprocessor needs memory devices to store programs and data (generated during processing). In Computer Science, memory usually refers to RAM and ROM memories and storage usually refers to disks and other external devices. 3

4 PROCESSOR Basic organization of a computer ADDRESS BUS ROM RAM I/O DATA BUS 4

5 Example of using memory in a computer 5

6 Memory Hierarchy Reg. Speed and Cost Cache Main Memory (RAM and ROM) Secondary Memory (HDD) Capacity External storage 6

7 Basic memory array Each element of storage in a memory can store 1 bit and it is called cell. Memory is made up of cells matrices. Each row of that memory array is called word and represents the information that is able to be read or written in each access.

8 Bidimensional organization of a memory

9 Memory address and capacity (Address Bus) A n M 2 n xk k D (Data Bus) Memory capacity is the amount of bits that it can store: A (Address Bus) n xk. Position of a word is called address. (Data Bus) k

10 Basic operations of memory Because they are storage devices, memory has two basic operations: Write: it allows to store a word in a particular memory address. Read: it allows to retrieve a word stored in a particular memory address. To implement these operations two buses are needed: Address bus (A n-1 : A 0 ): to indicate the read/write address. Data bus (D k-1 : D 0 ): to read/write the word. R W M A n-1 : A 0 D k-1 : D 0 10

11 Writing in memory

12 Reading from memory

13 Reading from memory Memory

14 Tridimensional organization of a memory

15 Tridimensional organization of a memory

16 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. 16

17 Classification semiconductor memory Random access Only read (ROM) Read/Write (RAM) FIFO (queue) Sequential access LIFO (stack) 17

18 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. 18

19 RAM and ROM memory The two main random access semiconductor memory categories are: ROM (Read-Only Memory): they can only be read and they are nonvolatile. RAM (Random-Access Memory): they can be read and written and they are volatile. 19

20 Family of ROM memory ROM Read Only Memory Mask ROM PROM Programmable ROM EPROM Erasable PROM UV EPROM Ultraviolet EPROM EEPROM Electrically EPROM 20

21 ROM Memory One is able to store 2 m data of n bits Non volatile It is recorded during manufacturing (ROM) or in laboratory (EPROM, EEPROM ) AB: Address BUS [A m-1 :A 0 ] DB: Data BUS [Dn-1:D0] 21

22 Example: ROM 2 3 x4 (8 positions of 4 bits) CS x y z CS: Chip Selection A 2 A 1 A 0 ROM 2 3 x 4 D 3 D 2 D 1 D 0 CS A2 A1 A0 D3 D2 D1 D HI HI HI HI In each column a function is carried out (when CS=1). E.g. D 0 = S (m 0, m 3, m 4, m 5 ) = P (M 1, M 2, M 6, M 7 ) When CS disable, outputs are in HIGH IMPEDANCE (HI) 22

23 Internal organization of a ROM. E.g.: ROM 16x8 23

24 Example of use of ROM: Natural binary code to Gray converter Address Content B3 B2 B1 B0 G3 G2 G1 G0 Natural binary code 3 bits GRAY code 24

25 Example of tridimensional organization: ROM 256x4 Array (32x8)x4 bits 25

26 Example of tridimensional organization: ROM 256x4 array (32x8)x4 bits 26

27 Example of a commercial EPROM NMC27C16B 2048x8 Bit EPROM (Fairchild s) Chip Enable/ ProGramming Mode 27

28 Access time for the commercial EPROM NMC27C16B 2048x8 Bit EPROM (Fairchild s) 28

29 Access time for the commercial EPROM NMC27C16B 2048x8 Bit EPROM (Fairchild s) 29

30 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. 30

31 RAM memory ROM (Read Only Memory): Only read, non-volatile RAM (Random Access Memory): Read/write, volatile Random access 2 main types: Static (SRAM): they keep the stored data while there is power (with flip-flops) (faster). Dynamic (DRAM): they need to refresh the information periodically ( reload condensers) (cheaper).

32 RAM cells SRAM cell DRAM cell

33 Description of RAM memory It can have unidirectional data lines (separated inputs and oputputs) or bidirectional. Description of RAM 2 n x m with bidirectional data lines: Address Bus Data Bus RW M DB = 00 M M HI 01 M(AB) DB [DB in] 10 M M DB = M(AB) 11 Forbidden Read Write

34 Internal organization of RAM (32kx8) /CS /OE /WE Mode Data Bus?

35

36 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion (association) 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. 36

37 Word length expansion in ROM memory 37

38 Word length expansion in ROM memory Get a ROM 2 3 x 8 with two ROM 2 3 x 4 CS A2 A1 A ROM 8x ROM 8x4 ROM 8x D7D6D5D4 D3D2D1D0 38

39 Word length expansion in ROM memory E.g. Get a ROM 64kx8 with two ROM 64kx4 39

40 Word length expansion in RAM memory CS WE OE A2 A1 A RAM 8x RAM 8x4 RAM 8x D7D6D5D4 D3D2D1D0 40

41 Word length expansion in RAM memory E.g. Get a RAM 1Mx8 with two RAM 1Mx4 41

42 Word amount expansion in memory 42

43 Word amount expansion in ROM memory Get a ROM 2 4 x 4 with two ROM 2 3 x 4 CS A3 A2 A1 A ROM 8x ROM 8x ROM 16x4 D3D2D1D0 43

44 Example: word amount expansion in RAM memory CS WE OE A3 A2 A1 A RAM 8x RAM 8x RAM 16x4 D3D2D1D0 44

45 Example: word amount expansion in RAM memory E.g.: Get a RAM 1Mx4 with two RAM 512K x4 45

46 FLASH memory Read/write, high capacity and non-volatile memory TYPE Non-volatile High density Cell of 1 transistor Write insystem Flash Yes Yes Yes Yes SRAM No No No Yes DRAM No Yes Yes Yes ROM Yes Yes Yes No EPROM Yes Yes Yes No EEPROM Yes No No Yes 46

47 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion (association) 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. 47

48 FIFO (First In-First Out) memory (queue; cola) Incoming data last 1st Outgoing data 48

49 LIFO (Last In-First Out) memory (stack; pila) PUSH Write new data Bottom (D) Last data TOP (R0) PULL / POP Read/Extract last data First data EMPTY STACK: When none data has been written yet FULL STACK: IDLE STACK: When D elements have been written When there isn t Pull neither Push 49

50 Writing on Stack (Pila) 50

51 Reading from Stack (Pila) 51

52 Content 1. Memory 1.1 Basic concepts 1.2 Semiconductor memory classification 1.3 Random Access Memory - Read Only Memory (ROM) - Read and Write Memory (RAM) - Memory expansion (association) 1.4 Sequential access memory 2. Programable devices: Basic architecture for a FPGA. 52

53 Programmable Logic Devices Designing functions with many inputs and outputs using flip-flops and gates (from K-map and state diagrams) is non-viable. PLDs: They are devices that are programmable by user to implement many functions with many variables. Large variety: SPLD (Simplex PLD): PAL/GAL, FPLA, CPLD (Complex PLD) Currently, the most used are FPGAs (Xilinx and Altera) PLD: Programmable Logic Device PAL: Programmable Array Logic GAL: Generic Array Logic FPGA: Field-Programmable Gate Array

54 Lifecycle of design with PLD PLD: Programmable Logic Device HDL: Hardware Description Language

55 Design environment with PLD

56 Basic structure of a PAL (SPLD) (fussel logic NON-reprogrammable) PAL: Programmable Array Logic SPLD: Simple Programmable Logic Device

57 Product addition accomplished with a PAL (SPLD) (fussel logic NON-reprogrammable) PAL: Programmable Array Logic SPLD: Simple Programmable Logic Device

58 Basic structure of a GAL (SPLD) (It IS reprogrammable) GAL: Generic Array Logic SPLD: Simple Programmable Logic Device

59 Simplified notation for PAL/GAL (SPLDs)

60 PAL/GAL (SPLDs) architecture

61 Output logic of macrocells in PAL/GAL (SPLDs) devices

62 CPLDs (Complex PLDs) Generic architecture PLD: Programmable Logic Device SPLD: Simple Programmable Logic Device PIA: Programmable Interconnect Array

63 Example: Architecture CPLD MAX 7000 (Altera)

64 FPGA (Field-Programmable Gate Array) A FPGA allows to implement any digital circuit. The only limitation is the amount of gates for the circuit. Develop is carried out using a prototype board.

65 Main manufacturers and models of FPGA Otros Others Actel Lattice Altera Market share Xilinx Xilinx: Spartan Virtex Altera: Arria Cyclone Stratix Actel: Igloo ProASIC SmartFusion

66 FPGA concept LTU: Look-Up Table

67 Basic architecture of a FPGA CLB: Configurable Logic Block

68 Structure of Configurable Logic Blocks (CLB) of a FPGA

69 Structure of a logic module (included in CLBs) of a FPGA

70 Examples of configurations of volatile FPGAs (LUT SRAM)

71 Advanced architectures of FPGAs DSP: Digital Signal Processor LAB: Logic Array Block

72 Advanced architectures of FPGAs Column interconnects Rows interconnects Embedded memory DSP cores I/Os CLBs (a) FPGA with fully configurable logic (b) Same size FPGA with embedded memory and DSP cores results in fewer CLBs and is limited by the perimeter I/Os. Processor core (c) FPGA with more embedded memory, additional DSP cores, and processor core will require a larger physical size at some point.

73 First projects with FPGAs