SoC FPGAs. Your User-Customizable System on Chip Altera Corporation Public

Transcription

1 SoC FPGAs Your User-Customizable System on Chip

2 Embedded Developers Needs Low High Increase system performance Reduce system power Reduce board size Reduce system cost 2

3 Providing the Best of Both Worlds ARM Processor System Dual Core ARM Cortex-A9 MPCore Processor 28-nm FPGA Hard Memory Controller Peripherals SoC FPGA ARM + Altera = SoC FPGAs 3

4 SoC FPGA Family Highlights Dual-core ARM Cortex-A9 MPCore processor Hard memory controller, peripherals and high-bandwidth interconnect Altera s 28-nm FPGA fabric Cyclone V FPGA and Arria V FPGA ARM s ecosystem and Altera s hardware development flow Quartus II software and Qsys system integration tool Proven virtual prototyping methodology SoC FPGA Virtual Target for device-specific software development 4

5 ARM Processor Combined with Hard IP NEON Peripherals ARM Cortex-A9 L1 Cache FPU L2 Cache Memory Controller with ECC FPU ARM Cortex-A9 L1 Cache Hard Processor System NEON Dual-core ARM Cortex-A9 MPCore processor Hard IP 800 MHz per core (industrial grade) NEON media processing engine Single/double precision floating point unit (FPU) 32-KB/32-KB L1 caches per core ECC-protected 512-KB shared L2 cache Multi-port memory controller with ECC DDR2/3, Mobile DDR and LPDDR2 Flash memory controllers with ECC QSPI (NOR), NAND and SD/SDIO/MMC Wide range of common peripherals 5

6 Advanced 28-nm FPGA Technology 200-MHz to 10-Gbps Transceivers Variable Precision DSP Block 28-nm FPGA Memory Controller with ECC PCIe PCIe 28-nm low-power (28LP) FPGA fabric Hard IP The optimal choice for addressing today s power- and cost-constrained applications Lowest absolute power Up to three memory controllers with ECC Variable precision DSP technology Up to two hard PCIe Gen 2 x4 High-speed transceivers operating up to 10 Gbps 6

7 Superior System Bandwidth with Data Integrity 2x 10/100/1000 Ethernet 2x USB 2.0 OTG Memory bandwidth >170 Gbps Gen2 x4 (hard) Gen2 x8 (soft) Peripherals 161 to 216 I/O Memory Controller with ECC Memory Controller with ECC 66 to 528 I/O PCIe PCIe Hard Processor System 28-nm FPGA >125-Gbps Interconnect NEON ARM Cortex-A9 L1 Cache FPU FPU L2 Cache ARM Cortex-A9 L1 Cache NEON Variable Precision DSP Block Up to 6 x 10 Gbps Up to 30 x 6 Gbps Processor/FPGA boot flexibility 0 to 30 transceivers 200-MHz to 10-Gbps 7

8 System-Level Benefits of SoC FPGA Low High Increased system performance 4,000 DMIPS for under 1.8W Up to 1,600 GMACS, 300 GFLOPS DSP >125 Gbps processor to FPGA interconnect Cache coherent hardware accelerators Devices Before FPGA Memory Reduced power consumption Up to 30% power savings vs. 2-chip solution Devices CPU Memory Reduced board size Up to 55% form factor reduction As few as two power rails Reduced system costs Lower component cost Reduction in PCB complexity and cost Less routing with fewer layers Devices After FPGA + CPU Memory 8

9 SoC FPGA Device Portfolio Tailored to Address Diverse Application Requirements 9

10 SoC FPGA Key Features Key Features Process Processor Cache/co processors FPGA/Processor System Interface Memory controllers 28nm Low Power (28LP) process Dual-core ARM Cortex-A9MPCore processor L1, L2 Cache, NEON, DP FPU, ACP >100 Gbps bandwidth >125 Gbps bandwidth Up to 2 Hard memory controllers with ECC Up to 4 Hard memory controllers with ECC Memory bandwidth >51 Gbps >170 Gbps Logic Density 25, 40, 85,110KLE 350, 460KLE Transceivers Up to 5 Gbps Up to 10 Gbps Total Power Consumption 2W to 5W (Single 300 MHz commercial temp to dual 800 MHz industrial temp ) 10W to 15W (Single 300 MHz commercial temp to dual 800 MHz industrial temp ) 10

11 Technical Details 11

12 ARM Cortex-A9 MPCore Processor Dual-issue superscalar pipeline 2.5 MIPS per MHz Single- and double-precision floating-point unit (FPU) NEON media processing engine for media and signal processing acceleration Coherent L1 caches Memory coherency maintained between processors and FPGA 12

13 13

14 System Architecture Processor Dual-core ARM Cortex -A9 MPCore processor 4,000 MIPS (up to 800 MHz per core) NEON coprocessor with double-precision FPU 32-KB/32-KB L1 caches per core 512-KB shared L2 cache Multiport SDRAM controller Up to 533-MHz DDR3 and LPDDR2 Up to 400-MHz DDR2 Up to 200-MHz Mobile DDR Integrated ECC support High-bandwidth on-chip interfaces > 125-Gbps HPS-to-FPGA interface > 125-Gbps FPGA-to-SDRAM interface Cost- and power-optimized FPGA fabric Lowest power transceivers Up to 1,600 GMACS, 300 GFLOPS Up to 25Mb on-chip RAM More hard intellectual property (IP): PCIe and memory controllers Hard Processor System (HPS) ARM Cortex-A9 NEON / FPU L1 Cache QSPI Flash Control NAND Flash (1) (2) L2 Cache 64-KB RAM SD / SDIO/ MMC (1) Shared Multiport DDR SDRAM Controller (2) ARM Cortex-A9 NEON / FPU L1 Cache FPGA JTAG Debug / Trace (1) Timers (x11) HPS to FPGA USB OTG (x2) (1) GPIO SPI (x2) DMA (8 Channels) FPGA to HPS 28LP process 8-input ALMs Variable-precision DSP M10K memory and 640-bit MLABs fplls Ethernet (x2) (1) I 2 C (x2) CAN (x2) UART (x2) FPGA Configu ration Multiport Hard Multiport Multiport DDR DDR SDRAM DDR Hard 3-, 5-, 6-, SDRAM SDRAM Controller Controller (2) PCIe and 10-Gbps Controller Transceivers HPS I/Os FPGA General Purpose I/Os 14 Notes: (1) Integrated direct memory access (DMA) (2) Integrated ECC

15 Save Cost with an Efficient Core Architecture Adaptive LUT Full Adder Full Adder Reg Reg Reg Reg Enhanced ALM architecture Up to 30% increase in logic packing efficiency v 4-LUT 2x registers in each ALM for easier timing closure Variety of memory structures 10K blocks optimized for highest port count 640-bit MLABs for efficient data buffers Variable precision DSP block One block equals either : One 27x27 multiplication Two 18x19 multiplications Three 9x9 multiplications Up to 1,600 GMACS, 300 GFLOPS in Arria V SoC Up to 150 GMACS, 100 GFLOPS in Cyclone V SoC Efficient core lets you fit into a smaller device

16 Save BOM Cost Power distribution networks Cyclone V designs with only 2 power rails and only two switchers Arria V designs with only 3 power rails using 2 switchers and 1 linear Cyclone V Arria V Oscillators Synthesize ANY frequency with high precision Nine independent outputs from each fpll Reduce clock pins 16

17 Ultimate Configuration Flexibility Independent FPGA configuration and processor boot SOC Device Sources Configuration PCIe (1) QSPI /SPI Passive Serial Passive Parallel FPGA Config Controller (2) (3) CPU HPS QSPI /SPI MMC /SD NAND Flash Boot Sources Boot ROM Scratch RAM (1) Meets the PCIe 100 ms power-up-active time requirement (2) Supports AES encryption for design security (3) Supports partial re-configuration 17

18 Ultimate Configuration Flexibility Processor boots first, then configures the FPGA FPGA Config Controller SOC Device CPU HPS QSPI /SPI MMC /SD NAND Flash Boot Sources Configuratio on Sources Boot ROM Scratch RAM 18

19 Ultimate Configuration Flexibility FPGA configures first, CPU boots through FPGA logic (e.g. secure boot, custom backplane I/F) SOC Device Sources Configuration PCIe QSPI /SPI Passive Serial Passive Parallel FPGA Config Controller CPU HPS Boot Source User Specified I/F AXI Boot ROM Scratch RAM 19

20 HPS Multi-Port Hard Memory Controller Key Features DDR2, DDR3, LPDDR1, LPDDR2 support MHz ( Mbps) speed x8, x16 or x32 interfaces with optional ECC x8, x16 components with 2 chip selects High Performance HPS FPGA Fabric User Design Multiport Front End x8 / x16 / x32 Memory Controller Low latency full rate operation Deficit Round Robin arbitration with aging Per port & per burst priority & weighting High priority bypass for latency sensitive traffic High efficiency with command and data reordering PHY Interface PHY I/O Interface Low Cost Hard logic in HPS (HPS dedicated I/O) Up to six ports shared with FPGA fabric CMD/ADDR DQS ECC HPS Hard Memory Controller 20

21 FPGA Multi-Port Hard Memory Controller Similarities to HPS hard memory controller Same device support Same performance Same operation Differences No direct connection to HPS Up to 3 hard memory controllers in FPGA Available for user design PHY can be used by soft logic (bypass) I/O can be used by soft logic (bypass) FPGA Fabric User Design Multiport Front End x8 / x16 / x32 Memory Controller PHY Interface PHY I/O Interface CMD/ADDR DQS ECC FPGA Hard Memory Controller 21

22 PCIe Support Arria V - Gen2 x4, Gen1 x8 Cyclone V - Gen2 x2, Gen1 x4 Live link within 100 ms Root port and endpoint support Configuration via Protocol (CvP) using PCIe Hard PCIe block Reduces costs and power Provides built-in timing closure Shortens design time New: multifunction support PCS PMA Non-PCIe Applications User Design Core Fabric Transceivers PIPE 2.0 PHY/MAC Data Link Layer Transaction Layer PCIe Hard IP 22

23 First PCIe Multi-Function Support in FPGAs Simplifies sharing of PCIe link bandwidth between multiple peripherals Shortens development time by enabling use of standard software drivers Memory Controller Processor Root Complex Local Periph1 Local Periph 2 Each peripheral gets its own function with individual control status registers (CSR) and address space Reduces costs Integrates multiple single-function endpoints into single multifunction endpoint Supports up to eight functions Saves approximately 20 KLEs PCIe Root Port PCIe Link PCIe Endpoint CAN GbE ATA Bridge to PCI Multifunction USB SPI GPIO I2C Customize Industry-Standard Processors for Your Application 23

24 CPU & FPGA I/O A portion of device I/O are allocated to the HPS peripherals HPS Local I/O LVTTL 1.8V I/O Bank LVTTL 2.5V I/O Bank LVTTL 3.3V I/O Bank FPGA I/O HPS peripherals assigned to HPS I/O HPS peripherals can be routed to FPGA FPGA logic can be routed to HPS I/O SSTL V I/O Bank HPS Core (Processors & Peripherals) HPS / FP PGA Interface FPGA I/O HPS / FPGA Interface 24

25 Power 25

26 Process Choice for 28-nm Portfolio Power Power Cost TSMCs 28LP process and design 28-nm LP optimizations Speed Cost TSMCs 28HP process and 28-nm design HP optimizations Speed Lowest static and absolute power Lowest power transceivers Sufficient performance Maximum hardened IP High performance IO interfaces Highest bandwidth 28G transceivers at 200 mw Lowest power in high-performance systems 26

27 40% Power Reduction with Arria V FPGAs 1.2 l Power Arria II FPGA Power) Total (Normalized to A Up to 15% Up to 40% Up to 30% IO s Transceiver Core Dynamic Core Static 0 Arria II FPGAs Up to 70% Arria V FPGAs 27

28 Cyclone V FPGAs Reduce Total Power Up to 40% ~150K Gates 60 nm ~150K Gates 28 nm 28-nm LP benefits: Lower capacitance Multi-threshold transistors Variable channel lengths reduce leakage Reduced core voltage 28 Source: Excel based power estimation tools Q1 2011

29 Lowest Transceiver Power per Channel Gbps 6 Gbps 10 Gbps Power per Channel (m mw) Competing 28nm FPGAs Altera's 28-nm LP FPGAs Conditions: 85C Junction Typical Case Source: Xilinx XPE 13.1 ~30% the power at any data rate 29 Source: Excel based power estimation tools Q1 2011

30 Development Flow & Tools 30

31 System Development Flow Standard FPGA Flow Hardware Development Standard Software Flow Software Development Quartus II design software Qsys system integration tool Standard RTL flow Altera and partner IP Design Design ARM Development Studio 5 GNU toolchain OS/BSP: Linux, VxWorks Etc ModelSim, VCS, NCSim, etc. AMBA-AXI and Avalon bus functional models (BFMs) Simulate Simulate Virtual Target SignalTap II logic analyzer System Console Quartus II Programmer In-system Update Debug Release FPGA in the Loop Debug Release GNU, Lauterbach, DS5 and ARM ecosystem Flash Programmer

32 FPGA Industry s First Virtual Target Immediate device-specific software development Binary- and register-compatible Uses proven virtual prototyping technology Linux and VxWorks enabled, compatible with ARM tools FPGA-in-the-loop extension option Real I/O Connectivity on Host PC PC-Based Simulation of SoC FPGA Development Board Optional FPGA-in-the-loop Extension FPGA for user IP Ethernet DDR USB Flash Peripherals Hardened CPU Interface IP User IP User IP 32

33 FiL Over PCIe AIIGX Dev Board Laptop ExpressCard to PCIe Adapter Card/Cable 33

34 Leveraging the ARM Ecosystem Source: ARM 34

35 Leveraging the ARM Ecosystem Software Development Tools GNU ARM Design Studio 5 (DS-5) Lauterbach TRACE32 Wind River Workbench Available on the Virtual Target Today! OS Support Available on the Virtual Target Vendor Altera Wind River Systems Micrium OS/RTOS Linux VxWorks uc/os-ii All major OS support in planning. Contact Altera for availability. 35

36 Qsys: Altera s System Integration Tool High-Performance Interconnect Based on Network-on-a-Chip (NoC) Architecture Design Reuse Hierarchy Package as IP Design System Add to Library 36 Qsys Improves Your Productivity Where You Need It

37 Family plan 37

38 SoC FPGA Device Family Plan Family KLE Block Memory Bits (Mb) Var. Prec. Multiplier Blocks Max. FPGA User I/Os Max HPS I/Os Max. XCVRs (GP) Per - XCVR Max. Data Rate (Gbps) HPS Hard Memory Controller FPGA Hard Memory Controllers Hard PCIe Cyclone V SoC FPGA Arria V SoC FPGA / 16 6 / , / 16 6 / ea, Gen1 2 ea, Gen1 2 ea, Gen2 2 ea, Gen2 2 ea, Gen2 2 ea, Gen2 38

39 SoC FPGA Device Package Plan Non-XCVR Devices (FPGA User I/Os) XCVR Devices (FPGA User I/Os,XCVRs) Family KLE U484-WB 19x19 U672-WB 23x23 F896-WB 31x31 U672-WB 23x23 (IO,3G) F896-WB 31x31 (IO,3G/5G) F896-FC 31x31 (IO, 6G, 10G) F1152-FC 35x35 (IO, 6G, 10G) F1517-FC 40x40 (IO, 6G, 10G) ,6 Cyclone V SoC FPGA , ,6 288, ,6 288,9 Arria V SoC FPGA ,12,4 350,18,8 528,30, ,12,4 350,18,8 528,30,16 HPS I/O

40 Thank You