Chapter 1: The General Purpose Machine

Transcription

1 Chapter 1: The General Purpose Machine Computer ystems esign and rchitecture

2 User s View of a Computer The user sees software, speed, storage capacity, and peripheral device functionality. Computer ystems esign and rchitecture

3 Machine/assembly Language Programmer s View Machine language: et of fundamental instructions the machine can execute Expressed as a pattern of 1 s and 0 s ssembly language: lphanumeric equivalent of machine language Mnemonics more human oriented than 1 s and 0 s ssembler: Computer program that transliterates (one-to-one mapping) assembly to machine language Computer s native language is assembly/machine language Programmer, as used in this course, means assembly/machine language programmer Computer ystems esign and rchitecture

4 Machine and ssembly Language The assembler converts assembly language to machine language. Op code ata reg. #5 ata reg. #4 MC68000 ssembly Language MOVE.W 4, 5 Machine Language I.W #9, Table 1.2 Two Motorola MC68000 instructions Computer ystems esign and rchitecture

5 The tored Program Concept The stored program concept says that the program is stored with data in the computer s memory. The computer is able to manipulate it as data for example, to load it from disk, move it in memory, and store it back on disk. Invented by Eckert & Mauchley Computer ystems esign and rchitecture

6 ENIC (1946) Electronic Numerical Integrator nd Calculator The first electronic computer esigned by Mauchly and Eckert Built with 18,000 vacuum tubes and 6,000 switches Used for trajectory calculation in the U army Computer ystems esign and rchitecture

7 EVC (1951) Electronic iscrete Variable utomatic Computer The first internally stored program computer Binary number system Computer ystems esign and rchitecture

8 EVC uccessor of the ENIC Made by the same designers: Mauchly and Eckert tored program Computing Invented by Mauchly and Eckert This concept was subsequently documented by Johann (John) von Neumann in his paper which is now known as the First raft. John Presper Eckert and John Mauchly Computer ystems esign and rchitecture

9 The first microprocessor Intel 4004 (in 1971) esigned by Federico Faggin, Ted Hoff, and tan Mazor Computer ystems esign and rchitecture

10 Intel bit 4004 ran at 108 khz and contained 2300 transistors (0.06 MIP) Motivation: In 1971, Busicom, a Japanese company, wanted a chip for a new calculator Computer ystems esign and rchitecture

11 PECInt95 Performance C dvances in Intel processors 81.3 (projected) Pentium IV 2.8GHz (superscalar, out-of-order) (projected) Pentium IV 1.7GHz (superscalar, out-of-order) Pentium III 600MHz (superscalar, out-of-order) 8.09 PPro 200MHz Pentium 100MHz (superscalar, out-of-order) 1 (superscalar, in-order) X2 66MHz (pipelined) 10 Pentium II 300MHz (superscalar, out-of-order) Computer ystems esign and rchitecture 2002

12 Fetch-Execute Cycle Computer ystems esign and rchitecture

13 Programmer s Model: Instruction et rchitecture (I) Instruction set: the collection of all machine operations. Programmer sees set of instructions, along with the machine resources manipulated by them. I includes instruction set, memory, and programmer accessible registers of the system. There may be temporary or scratch-pad memory used to implement some function is not part of I. Non Programmer ccessible. Computer ystems esign and rchitecture

14 Programmer s Models of 4 commercial machines Computer ystems esign and rchitecture

15 Machine, Processor and Memory tate The Machine tate: contents of all registers in system, accessible to programmer or not The Processor tate: registers internal to the CPU The Memory tate: contents of registers in the memory system tate is used in the formal finite state machine sense Maintaining or restoring the machine and processor state is important to many operations, especially procedure calls and interrupts Computer ystems esign and rchitecture

16 Examples of HLL to ssembly Language Mapping I n s t r u c t i o n C l a s s C V X s s e m b l y L a n g u a g e a t a M o v e m e n t r i t h m e t i c / l o g i c C o n t r o l f l o w a = b b = c + d * e g o t o L B L MOV b, c MPY d, e, b c, b, b BR LBL This compiler: Maps C integers to 32 bit VX integers Maps C assign, *, and + to VX MOV, MPY, and Maps C goto to VX BR instruction The compiler writer must develop this mapping for each language-machine pair Computer ystems esign and rchitecture

17 Tools of the ssembly Language Programmer s Trade The assembler The linker The debugger or monitor The development system Computer ystems esign and rchitecture

18 Who Uses ssembly Language The machine designer must implement and trade-off instruction functionality The compiler writer must generate machine language from a HLL The writer of time or space critical code Performance goals may force program specific optimizations of the assembly language pecial purpose or embedded processor programmers pecial functions and heavy dependence on unique I/O devices can make HLL s useless Computer ystems esign and rchitecture

19 Computer rchitect s View rchitect is concerned with design & performance esigns the I for optimum programming utility and optimum performance of implementation esigns the hardware for best implementation of the instructions Uses performance measurement tools, such as benchmark programs, to see that goals are met Balances performance of building blocks such as CPU, memory, I/O devices, and interconnections Meets performance goals at the lowest cost Computer ystems esign and rchitecture

20 Buses as Multiplexers Interconnections are very important to computer systems Most connections are shared bus is a time-shared connection or multiplexer bus provides a data path and control Buses may be serial, parallel, or a combination erial buses transmit one bit at a time Parallel buses transmit many bits simultaneously on many wires Computer ystems esign and rchitecture

21 One and Two Bus rchitecture Examples Computer ystems esign and rchitecture

22 Getting pecific: The pple PowerMac G4 Bus (simplified) Computer ystems esign and rchitecture

23 Memory Hierarchy Modern computers have a hierarchy of memories llows tradeoffs of speed/cost/volatility/size, etc. CPU sees common view of levels of the hierarchy. CPU Cache Memory Main Memory isk Memory Tape Memory Computer ystems esign and rchitecture

24 Tools of the rchitect s Trade oftware models, simulators and emulators Performance benchmark programs pecialized measurement programs ata flow and bottleneck analysis ubsystem balance analysis Parts, manufacturing, and testing cost analysis Computer ystems esign and rchitecture

25 istinction between Classical Logic esign and Computer Logic esign The entire computer is too complex for traditional FM design techniques FM techniques can be used in the small There is a natural separation between data and control ata path: storage cells, arithmetic, and their connections Control path: logic that manages data path information flow Well defined logic blocks are used repeatedly Multiplexers, decoders, adders, etc. Computer ystems esign and rchitecture

26 Two Views of the CPU PC Register Programmer: 31 0 PC B Bus 32 Q 32 Bus Logic esigner (Fig 1.8): PC PC out CK PC in Computer ystems esign and rchitecture

27 Historical Generations 1st Generation: vacuum tubes, relays, mercury delay lines 2nd generation: discrete transistors and magnetic cores 3rd generation: small and medium scale integrated circuits 4th generation: 1975-present, single chip microcomputer Integration scale: components per chip mall: Medium: 100-1,000 Large: ,000 Very large: greater than 10,000 Computer ystems esign and rchitecture

28 Tube Pictures Computer ystems esign and rchitecture