FTF-AUT-F0561. Continental Virtual Platform for a Chassis and Safety Application. Dr. D. Baumeister Continental Manfred Thanner - Freescale

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1 June 23, 2010 Continental Virtual Platform for a Chassis and Safety Application FTF-AUT-F0561 Dr. D. Baumeister Continental Manfred Thanner - Freescale Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. TM

2 Abstract This joint Continental and Freescale presentation will give an overview about the development and deployment on a virtual platform used in electronic stability control application for pre-silicon software development, design exploration and performance analysis. The presentation will give an overview on the used simulation technologies, example model implementations and coupling technologies. The deployed software use cases will be shown and how it accelerated the development process due to pre-silicon availability. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 2 TM

3 Agenda Overview Model Approach Electronic Control Unit Simulation Setup Use Cases Error Injection Summary Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 3 TM

4 Overview Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 4 TM

Background on Continental and Freescale Virtual Platforms Continental & Freescale are working in a long-term development partnership over 5 ucontroller Generations Enabled continuous development of

5 Background on Continental and Freescale Virtual Platforms Continental & Freescale are working in a long-term development partnership over 5 ucontroller Generations Enabled continuous development of virtual platforms Two generations of virtual platforms frameworks delivered since 2001 Covering several devices with virtual platforms Enabled infrastructure and workflows for seamless model exchange Extending use cases Validation Software driver development and test Full applications Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 5 TM

6 Improving the Schedule Goal: All hardware related software implemented and tested when first silicon arrives Prerequisite: Virtual Model Availability pre-silicon Started when specification is mostly finished Runs in parallel with hardware design Simulator must be made available at least 6 months ahead of silicon Low level driver development started with early simulator releases Decouples SW development from the HW design schedule Design Spec Spec First Silicon Design Virtual Model Software Integration HW Design Virtual model Releases HW Related SW Development HW / SW Integration, Bring up Parallel HW/SW Development Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 6 TM

Virtualization Merits Early System Trade-Off Analysis Manage the complexity Analysis beyond CPU MIPs and memory footprint System evaluation of new IP ahead of first Silicon.

Potential for FMEA case scenario analysis Etc.

7 Virtualization Merits Early System Trade-Off Analysis Manage the complexity Analysis beyond CPU MIPs and memory footprint System evaluation of new IP ahead of first Silicon. Prepare system/user oriented test cases Early software development start MCU / system operation insight (perhaps not available in hardware) Potential for fault injection scenario analysis Potential for FMEA case scenario analysis Etc. Increase new product introduction efficiency by using tools in the concept/definition phase then leveraging the tools to launch verification/validation ahead of silicon availability. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 7 TM

8 Virtualization has been used by many years in the industries Initial company proprietary solutions Future is in standardized, inter operable models in an ecosystem TLM, model to tool APIs, model to model standard definitions Automotive modeling standards and best practices evolving Virtualization History Company internal solutions Semi s, Tier1, OEMs Proprietary by nature Target to few use cases Commercial Solutions become available Often based on outplaced company solutions First standardization efforts visible Standards evolve Model reuse Wider number of use cases addressed Commercial ecosystems become available Wider use cases addressed Standardization on TLM Model to tool Model exchange Model guide lines Standards & automations 1980s 1990s 2000s 2010s Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 8 TM

9 Model Type Scope Use Case Model Completeness Overview Core model ISS only Core only, Instruction set covered (no exceptions), e.g., Lauterbach build in ISS Running cross compiled code without interaction to peripherals Core ISS With exceptions Core model takes any exception into account; used often in high end speed models without timing Code running with exceptions, e.g., software interrupts Core model cycle count accurate Platform model Used for profiling requires accurate memory models Core, memory, IRQ, xbar Can be used for memory profiling Used for profiling, cycle count accuracy; periphery stub as memory For OS porting/development, minimal peripheral features covered (max IRQ, timer) Full chip model Used all models Covering all peripherals, EVB equivalent Full chip model with plant model Application development Additional models are connected or co-simulated Target for Continental and Freescale Virtual Platform Development Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 9 TM

10 Model Approach Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 10 TM

11 Power Architecture Core & Peripheral Models Core Models Available today e200z4, e200z6, e200z3, e200z0, e200z7 ADL/uADL Core models Based on FSL open source architectural description language Integrated today into CoWare s SystemC simulation platform ADL Focus Functional ISS models validated vs. FSL testbench uadl focus on micro architecture implementation pipeline, architecture, Timing Focus on cycle counts accuracy Validation against RTL Integration in any simulator framework possible Peripheral Models Available today Large set of automotive peripherals FlexCAN, FlexRay, Timer, esci, SPI Interrupt controller, xbar, SIU Peripheral models Model kernel is C/C++ Base Class used for mapping to SystemC simulation platform Target to migrate to TLM2.0 Vendor agnostic Transaction based Event driven bus access, CAN and FlexRay communication transaction based Mapped to SCML for CoWare VPA visibility & functionality support Cycle count accurate Timer, memories, xbars cycle time validation vs. silicon on-going Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 11 TM

12 Power Architecture : e200 Automotive Platform same instruction set / memory map / interrupt map / software Single Issue Dual Issue z0 64MHz MHz z1 z3 80MHz MHz 120MHz MHz z4 150MHz MHz z6 200MHz MHz z7 300MHz MHz e200 Core models are available or in progress FSL models can be integrated in commercial tools e.g., CoWare, OSCI Tool vendor core models available e.g., VaST Source level integrations possible Freescale open source ADL model framework Active used frameworks CoWare VaST OSCI SystemC kernel Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 12 TM

13 General High Level Timeline for Virtual Platform Creation Milestones Phase 0 Prototype Platform Phase 1 Initial Platform Phase 2 Extended Platform Phase 3 Full Platform Phase 4 Full Platform Error Injection Time line to be adapted on detailed requirements Timeline based on previous simulator developments Releases 6-9 months ahead of silicon 20xx 20xx 20xx J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D Key Development Efforts Core Model Peripheral Models Top Level Integration Incremental Core Model drops Interface development First Silicon Incremental Peripheral Model drops Incremental levels of SoC integration Tool Integration Phases Maintenance Release Maintenance and Support Phase (silicon validation) Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 13 TM

Continental Multi Core Setup in Platform Architect Core 1 xbar FMPLL RAM Bridge Sample graphical representation of virtual model Block based Scriptable Full view of model implementations Basis for

14 Continental Multi Core Setup in Platform Architect Core 1 xbar FMPLL RAM Bridge Sample graphical representation of virtual model Block based Scriptable Full view of model implementations Basis for Virtual Platform export and generation Parameterization accessibility Core 2 Flash Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 14 TM

15 Overview Simulator Structure config.xml config.xml Configuration Core selection logging on/off VCD tracing model parameters Sim.log Lauterbach source debugging run time control break points HW View simulator control HW view watch points Config TCL Scripting Log errors, trace log All runs on WXP similar look and feel than EVBs ECU level models included for ABS/ESP Debugger integrations e.g., Lauterbach Log files and Traces deeper insight than HW Configurability selectable cores accuracies sim.vcd Signal Tracing Virtual scope logic analyzer selectable on module basis Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 15 TM

Infrastructure and Features Overview Full Device model developed PowerPC Multi Core simulation (e200z650 and e200z0) Switchable Cores between functional and cycle count accurate Xbars, Memories

Debug interface for source level debugging Lauterbach debugger integration Multicore debug capable Tracing capabilities Signal traces with VCD files (Virtual Logic Analyzer) Error Injection

16 Infrastructure and Features Overview Full Device model developed PowerPC Multi Core simulation (e200z650 and e200z0) Switchable Cores between functional and cycle count accurate Xbars, Memories (Flash, RAM), Interrupt controllers Automotive peripherals (CAN, FlexRay, LIN) Timers, PLL, etc. Debug interface for source level debugging Lauterbach debugger integration Multicore debug capable Tracing capabilities Signal traces with VCD files (Virtual Logic Analyzer) Error Injection capability Scripts for error injection Connectivity reconnect to provide loops pin to pin, CAN to CAN, FlexRay stimulus node, SPI to SPI Scriptability Fully scriptable to run and exit simulation Log files for regression result tracking Currently used for pre-silicon SW development Virtual Platform shipped months ahead of Silicon Driver development Basis for SW development Source Level Lauterbach Debugger Multicore Debugging Debugger connection Virtual Platform Analyzer OS Aware Hardware and Software parallel view Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 16 TM

17 Electronic Control Unit Simulation Setup Chassis & Safety EBS Development Electronics 17 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

18 Continental Corporation: Strong Divisions and Business Units Continental Corporation Automotive Group Rubber Group Chassis & Safety Powertrain Interior Passenger and Light Truck Tires Commercial Vehicle Tires ContiTech Electronic Brake Systems Hydraulic Brake Systems Sensorics Passive Safety & ADAS Chassis Components Engine Systems Transmissions Hybrid & Electric Vehicle Sensors & Actuators Fuel Supply Instrumentation & Driver HMI Infotainment & Connectivity Body & Security Commercial Vehicles & Aftermarket Original Equipment Replacement Business EMEA Replacement Business The Americas Replacement Business Asia Pacific Two-Wheel Tires Truck Tires Europe Truck Tires The Americas Truck Tires Asia Pacific Industrial Tires Air Spring Systems Benecke-Kaliko Group Conveyor Belt Group Elastomer Coatings Fluid Technology Power Transmission Group Vibration Control Other Operations 18 Continental AG

Chassis & Safety Division Business Units Electronic Brake

ADAS Chassis Components Electronic brake systems, e.g.

for motorcycle brakes ABS for motorcycles Regenerative brake

assistance systems Hydraulic valves Brake disks Drum brakes

boosters Tandem master cylinders Mechanical, electronic and

pressure regulators Inertial sensors for stability and ESC

and torque sensors Speed sensors for wheels, engines and

position Passive safety Driver assistance systems Occupant

systems Air suspension systems Chassis electronics Electronic

19 Chassis & Safety Division Business Units Electronic Brake Systems Hydraulic Brake Systems Sensorics Passive Safety & ADAS Chassis Components Electronic brake systems, e.g. ABS and ESC Electric-hydraulic combi brake (EHC) Control units for motorcycle brakes ABS for motorcycles Regenerative brake systems Software for extended brake control functions and assistance systems Hydraulic valves Brake disks Drum brakes Brake calipers Parking brakes Electric parking brakes Brake boosters Tandem master cylinders Mechanical, electronic and hydraulic brake assist devices Brake actuation modules Brake pressure regulators Inertial sensors for stability and ESC applications Sensors for active chassis control Steering angle and torque sensors Speed sensors for wheels, engines and transmission Sensors and switches for seat belt locks and seat position Passive safety Driver assistance systems Occupant classification Product integration and validation Steering systems Air suspension systems Chassis electronics Electronic components Windshield and headlamp cleaning systems Brake hoses Duo-servo parking brake systems 19 Continental AG

20 Contintental s Motivation for C-based IC Modeling: Benefits Reduction of developing time / time-to-market - Evaluation of hardware components to be developed in complex hardware/software environment - Parallelizing development of hardware and software 3 months 3 months Cycle-approximate MCU Model Cost Reduction Cycle-accurate MCU Model - Simple PC setup instead of physical test equipment (setups of various devices can be easily distributed, installed and maintained) - Reduction of Silicon Redesign (e.g. ROM masks) Quality improvement by verification enhancement - Verification of software components 1 st Silicon MCU - Verification of complex analog/mixed signal systems - Verification of complex hardware/software systems Enhanced System Visibility and Fault Coverage - Error Injection: Setup of fault conditions which are difficult to provoke in silicon device - Higher System Visibility: ECU-level actuators being modeled; Input of sensor data streams supported Chassis & Safety EBS Development Electronics 20 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

Simulation Target System: EBS ECU with Focus on Integrated Circuits Target System: Electro-hydraulic Control Unit for Electronic Stability Control (ESC) Car Sensors required to execute software on

21 Simulation Target System: EBS ECU with Focus on Integrated Circuits Target System: Electro-hydraulic Control Unit for Electronic Stability Control (ESC) Car Sensors required to execute software on virtual platform Components: Safety Integrity Level 3 (SIL3) certified Chip-Set: Full-Custom leading edge automotive safety MCU Full-Custom leading edge mixed-signal IC Actuators: Valves, Motor Sensors: Acceleration-, Pressure-, Wheel-speed-Sensors Chassis & Safety EBS Development Electronics 21 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

IC-Level Simulation Environment Microcontroller Models Instruction- and cycle-accurate at MCU pin-border: 100% S/W-compatible to silicon target Fast simulation execution compared to RTLsimulation

22 IC-Level Simulation Environment Microcontroller Models Instruction- and cycle-accurate at MCU pin-border: 100% S/W-compatible to silicon target Fast simulation execution compared to RTLsimulation (slow compared to IS emulator) Monolithic IP blocks delivered by Freescale MCU-Family Simulator covering portfolio of target configurations Mixed-Signal IC Models Complete modeling by Continental (no IC supplier contribution) Model implementation depending on use case: Fast simulation execution (behavioral models) Allows fast ECU-level simulations (not feasible on RTL level) Accurate (linear/non-linear analog solvers based on SystemC-AMS) thourough investigations of complex mixedsignal system functionalities Flash PGM ECC CPU RAM COM Redundancy Checker CPU RAM Sensor Signal Cond. ADC COM Bus I/F Watchdog PWM Valve Control Valve Drivers uc Power Supply Failsafe Chassis & Safety EBS Development Electronics 22 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

Continental EBS ECU-Level Simulation Environment Heterogeneous Simulation Environment representing target ECU Various domains Digital circuit modeling Analog circuit modeling - Behavioral models

23 Continental EBS ECU-Level Simulation Environment Heterogeneous Simulation Environment representing target ECU Various domains Digital circuit modeling Analog circuit modeling - Behavioral models (SDF: signal data flow) - Conservative models (linear/non-linear solvers) Various implementation languages C++ (with proprietary C++ class library extension) SystemC (v2.2 with TLM2.0 1) library extension) SystemC-AMS 2) (v0.15) Proprietary IP and IP blocks by IC vendor Digital Mixed Signal 1) TLM: Transaction Level Modeling 2) AMS: Analog Mixed-signal Chassis & Safety EBS Development Electronics 23 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

24 IC Simulation: Technology Leap from Proprietary to Standard Simulation Platform Proprietary Simulation Platform Development of new Simulation Technology SystemC/ SystemC-AMS Platform uc Generation 2 uc Generation 3 uc Generation 4 uc Generation 5 Technology Status: Full XML based tool flow within Cadence IDE, including automated net list generation >> required for efficient modeling of complex systems with distributed development teams worldwide Leading simulator coupling technology >> allowing coupling of different SystemC Kernels >> supporting coupling of different model IP blocks Chassis & Safety EBS Development Electronics 24 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

25 Simulator of First Triple-Core Automotive MCU Model Features Cores: Redundant main core, I/O processor Full memory system: Flash, SRAM, Cache Failsafe system emulation (100% S/W compliant to silicon) Peripheral set: Timer, QSPI, FlexCAN, FlexRay, SIU, esci Implementation Language: SystemC SystemC Simulation kernel: CoWare Virtual Platform Lauterbach Debugger By Freescale TCP /IP MCU (S)PACE SystemC CoWare SystemC Kernel (Master) By Continental C dll C PCU/ECU Digital/Analog Comp. SystemC/ SystemC-AMS OSCI 1) SystemC(-AMS) Kernel (Slave) 1) OSCI: Open SystemC Initiative Model Accuracy Cycle Approximate Cycle Accurate MCU Family Approach Configurable Umbrella Simulator Target Config. 1 MCU-1 (ADL) MCU-1 (uadl) Target Config. 2 MCU-2 (ADL) MCU-2 (uadl) Target Config. 3 MCU-3 (ADL) MCU-3 (uadl) Selection of MCU target configuration and accuracy level done by configuration file at simulation start-up Chassis & Safety EBS Development Electronics 25 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

26 Analog/Mixed-signal Modeling: Technical Goals Continental Conservative modeling of analog components with SystemC-AMS Behavioral modeling of analog components (with SystemC-AMS) Goals: Enhancement of analog model fidelity Performance Enhancement: double t=sc_time_stamp().to_seco if (en.event()) { t0=t; } double rel_t=t-t0; if (en) { o=factor1 * (a-e1)*exp(-rel_t/t); } else { o=factor1 * (a-e2)*(1-exp(-rel_t/t)); } Speed-up the system simulation platform for analog and digital ICs by at least one order of magnitude by using behavioral analog modeling (SystemC-AMS) Cancellation of proprietary technology solutions Move away from proprietary modeling techniques (AVSL) to industry-standard techniques (SystemC- AMS) in order to benefit from tool availability and model reuse Chassis & Safety EBS Development Electronics 26 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

27 XML-based Design Flow Cadence ICMS-based tool flow featuring: Script automation Dedicated user interface for nonmodeling experts Flow enabling: Robust, distributed model development at different sites world wide Reduced model development time Modeling of large and complex systems Cadence ICMS Non-OSCI SystemC Kernel (Master) SystemC ICMS Netlister Plugin C Heterogeneous Simulation Target dll C SystemC-AMS SystemC AVSL OSCI SystemC/SystemC-AMS Kernel (Slave) SystemC -AMS SystemC C++/AVSL Wrapper SystemC/AVSL Libraries incl. SystemC -AMS Simulation Data Scope AVSL: Continental Proprietary Modeling Standard Chassis & Safety EBS Development Electronics 27 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

28 Use Cases Chassis & Safety EBS Development Electronics 28

29 IC Simulation Use Cases Software-related use cases (Pre-silicon) Software Development of hardware-dependant software parts low-level drivers, AUTOSAR drivers, hardware-dependant S/W-functions (Post-silicon) Software Verification - MCU connections on ECU Level (MCU I/O Test) - Failsafe concepts Microcontroller / Mixed-signal ASIC - Hardware/Software Interface (mutual failsafe requirements, Flash/ROM compatibility) Cross-correlation to silicon; silicon performance evaluation Hardware-related use cases ASIC circuit development/design exploration Functional Partitioning Microcontroller/Mixed-Signal IC Functional Partitioning Hardware/Software Top-level Mixed-Signal IC Design Verification Certification of automotive safety chip-set (enabling verification diversity) Chassis & Safety EBS Development Electronics 29 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

30 Pre-silicon Benchmarking/Design-Exploration on a Virtual Platform Target: Design-Exploration on a Virtual Platform to define MCU Roadmap Benchmarking of CPU Core Options within Continental s target architecture Evaluation of peripheral enhancements Evaluation of architectural options Virtual Platform enabling Design Space Exploration Performance/Functionality MCU_A MCU_B MCU_C MCU_D MCU_E MCU_F MCU_G 120MHz 150MHz z3 z4 200MHz 300MHz z6 z7 in series under development Under definition Typical MCU Roadmap Time Chassis & Safety EBS Development Electronics 30 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

31 Pre-silicon software development S/W driver development at supplier S/W driver verification at Conti Silicon validation code development (6 months ahead of 1 st silicon) (3 months ahead of 1 st silicon) (6 months ahead of 1 st silicon) - 100% complete verification database when silicon samples are available S/W development of new application functions H/W-S/W integration (3 months ahead of 1 st silicon) (3 months ahead of 1 st silicon) RTL Freeze Tape Out 1 st Silicon Samples S/W driver development Validation Code Development S/W driver verification Development of new appl. functions H/W-S/W Integration Chassis & Safety EBS Development Electronics 31 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

supported traces: - Instruction trace - OS task trace - Memory access Chassis & Safety

32 S/W Analysis on Virtual Platform MCU/PCU Co-Simulation Result: Signal Trace ~2 s real-time vcd-trace of an application software run PCU MCU PCU MCU Function Trace: Other supported traces: - Instruction trace - OS task trace - Memory access Chassis & Safety EBS Development Electronics 32 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

33 Fault Fault Error Injection Chassis & Safety EBS Development Electronics 33

Error Injection Target: Functional safety software verification: exception handling in case of system fail state Benefit of simulator approach: Access to failure modes, which are hard to provoke with

34 Error Injection Target: Functional safety software verification: exception handling in case of system fail state Benefit of simulator approach: Access to failure modes, which are hard to provoke with silicon setup Method: Injection of errors into IC models by simulation backplane during program execution Examples: MCU errors: Memory System: Flash data/ecc error, ECC correction error, RWW Error Bus Systems: Data/Address/Control Bus error Clock System: Loss-of lock reset, Loss-of clock reset Failsafe System: Watchdog timer reset, Checkstop reset Reset/Interrupt System Mixed-signal IC errors: Watchdog Failures: Initialization/Command/Redundancy Errors ADC Failures: Data Corruption Errors, Shutdown Errors Actuator Failures: Leakage Errors, Load Driver Failures Chassis & Safety EBS Development Electronics 34 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

35 Summary Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 35 TM

36 Summary: Continental s Chassis and Safety Virtual Platform Continental EBS IC Development is committed to virtual prototype development Based on Freescale s MCU model portfolio, Continental established ECU-level mixed-signal, mixed-level Virtual Platform ECU-level Virtual Platform enables pre- and postsilicon use cases for software development, verification and analysis as well as hardware design exploration Coupling technology for IP model integration being developed by Continental Scripted Tool Flow for model generation mandatory to manage complex system modeling Chassis & Safety EBS Development Electronics 36 / Dr. D. Baumeister / IC Development CETE-IA / Date Continental AG

37 Simulation Summary Partnership enabled Eco system setup for Inter company model exchange Organizational support for effective virtual platform deployment High level model quality to achieve productivity based on Virtual platforms Reuse of existing models on-going Full device models available 6-9 months ahead of silicon Challenges Inter-company model exchange Standards don t support dynamic model plug- in Emerging virtualizations needs and requirements Few customers today, many more tomorrow in varying stages of virtualization Support and maintenance infrastructure Long model life cycle in automotive Change of EDA infrastructure and standards Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 37 TM

Summary Pre-silicon SW development is possible today Driver development OS porting Validation code development Simulator technology is not the bottle neck anymore Standard Need and Solutions, For

38 Summary Pre-silicon SW development is possible today Driver development OS porting Validation code development Simulator technology is not the bottle neck anymore Standard Need and Solutions, For inter-company model exchange Standardized model interfaces on ECU level Communication interface abstraction (), FlexRay, CAN, Signal interface MCU virtual prototypes aim to address key SW development challenges Integration with Tool ECO systems Collaboration between tools developers, model developers and services providers plus our collective customers is essential to realize the full potential of virtualization from which all can benefit. Virtual prototype simulation can be seen in the Tech Lab Virtual Multicore Power Architecture Platform for Automotive Running AUTOSAR OS Aware Debugging Pedestal A12 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobilegt, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 38 TM

39 TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

Dr. Stephen Rober Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks