Intel s s Memory Strategy for the Wireless Phone

Transcription

1 Intel s s Memory Strategy for the Wireless Phone Stefan Lai VP and Co-Director, CTM Intel Corporation Nikkei Microdevices Memory Symposium January 26 th, 2005

2 Agenda Evolution of Memory Requirements Evolution of the Memory Subsystem Evolving Role of Storage Future Role of Emerging Memory 2

3 Evolution of Memory Requirements Evolution of the Memory Subsystem Evolving Role of Storage Future Role of Emerging Memory 3

4 WW Adoption of New Handset Features 100% 75% 50% Packet Data: +18 Mb Color: +46 Mb Camera: +202 Mb 3G: +402 Mb 25% 0% Source: NPD/GfK, Intel January 2005 Mainstream Adoption Differs Worldwide - Handset needs diverge as segmentation increases - Features driving RAM, code & data density increase - Data needs highly variable, driving growth of card sockets Solution Must Scale Across Wide Range of Needs 4

5 Today s s Memory Subsystem Needs Memory Function 05 Requirements Technologies RAM Code Data User System Execution Working Static Low cost 0.5 to 2 MB/s write 10 5 erase cycles 104 MHz random read Very low retention power read cycles <100 ns bit alterations <500 µa A retention power 10 8 write cycles Small Form Factor HDD NAND MLC NOR MLC NOR SBC NOR LPS/DDR DRAM + storage SRAM PSRAM LPS/DDR DRAM 5

6 Needs Vary Greatly by Handset Segments Hardware BOM High 68 mu handsets Mid 281 mu handsets Low 312 mu handsets Functionality System & User Data 256 to 512+ Mb Execution Memory 256 to 512 Mb Working Memory 128 to 512 Mb System & User Data 64 to 128 Mb Execution Memory 64 to 256 Mb Working Memory 64 to 128 Mb System & User Data 2 to 32 Mb Execution Memory 16 to 64 Mb High End Needs Advance Rapidly as Consumer Segments Fragment Mainstream Handsets Dominate Unit Volumes 2005 Source: Intel, Gartner 9/2004 Working Memory 2 to 32 Mb 6

7 Evolution of Memory Requirements Evolution of the Memory Subsystem Evolving Role of Storage Future Role of Emerging Memory 7

8 Memory Hierarchy & Trends: Evolution of the Subsystem Increasing Latency, Decreasing Cost/Bit Main Memory BB/App CPU Rotating Storage Removable Storage Embedded Data Buffers NVM Code 2 nd Level Cache 1 st Level Cache Integrated memory for Cache & Buffers on the rise Emergence of 2nd Level Cache in Wireless CPUs Large integrated memory appears in mainstream chipsets Size of embedded volatile memory remains limiting factor System in Package use growing New technologies enable size, power, & performance gains Flexibility & scalability are key 8

9 Memory Architecture Approaches Execute in Place (XIP) Memory Store and Download (SnD) Memory R F Baseband DSP Peripherals DSP ARM* ARM* Peripherals NVM RAM RAM I$ I$ D$ Memory/Bus Controller Code Data Working Working Static Flash RAM R F Baseband DSP Peripherals DSP ARM* NVM RAM RAM I$ I$ D$ ARM* Peripherals Memory/Bus Controller Data & Files Shadow Working Static NV Storage RAM Code copied and fixed in place at boot Data flow in a I cache miss Data flow in a I cache miss Lowest RAM density required Lowest standby power Minimum chip count, weight, space Extra RAM density required or reduced performance with demand paging Higher standby power Higher software complexity Single bus bottleneck XIP Memory Shipping in 95% of Handsets 9

10 Subsystem Architecture Comparison Values Low Cost Bill of Materials, Max User Available RAM Fast Code Performance Multimedia, Java, Paging Impacts, Boot Fast File System Performance File Write, Database, Multimedia file Low Power (Energy) Code Execution Power in System Standby Low System Complexity Code and Data Integrity, Simple Software XIP over SnD = + -/=

11 Next Steps: Extending the Benefits of an XIP- based Memory Subsystem Deliver the best XIP performance & data storage performance Higher performance XIP Increased bus frequency, Flash DDR Pipelined interface Increased write speeds > 4 Megabits/sec Optimized total subsystem solutions Developing an array of solutions to make mobile systems more secure 11

12 XIP SnD Enables Unauthorized Entry Points Code executed directly from NOR Flash R F Baseband DSP Peripherals DSP ARM* ARM* Peripherals NVM RAM RAM I$ I$ D$ Memory/Bus Controller Most viruses overwrite RAM in an unauthorized manner ADWARE DIALERS SPYWARE Code Data Working Working Static Flash LP SDRAM (Optional) Code Storage Memory = Execution Memory TROJAN HORSE HOAX WORM SnD R F Code executed from RAM Baseband DSP Peripherals DSP ARM* NVM RAM RAM I$ I$ D$ ARM* Peripherals Memory/Bus Controller Boot/ Comm Data & Files Shadow Working XIP foundation eliminates opportunity of intercept while writing to RAM Static NOR DISK LP SDRAM REMOTE ACCESS JOKE PROGRAMS HACK TOOLS Shadowed/paged code in vulnerable to modifications 12

13 Optimal Wireless Memory System LPSDRAM PSRAM SRAM Data Flash Code NOR Data Flash Intel StrataFlash Wireless Memory LPSDRAM Intel StrataFlash Wireless Memory PSRAM/LPSDRAM Intel StrataFlash Wireless Memory Card Slot Card Slot Scalable from Low to High SRAM/PSRAM Flexibility to Meet Different Phone Price Points 13

14 Evolution of Memory Requirements Evolution of the Memory Subsystem Evolving Role of Storage Future Role of Emerging Memory 14

15 08 Consumer Mobile Mass Storage Target Density Notebook PC 100 GB 10 GB Floor Cost of HDD Digital Camcorder High End MP3 1.8 HDD 1.0 HDD MLC NOR/NAND 1 GB Cards HH Video Game 0.1 GB Volume Handset $1 $10 $100 Storage Price Point 15

16 Usage of SFF HDD in Handheld Systems Power, vibration & environment inherent issues with rotating media Successful implementations focus on media storage Large media files (MP3, MPEG4) are buffered into RAM and HDD shut down XIP code & system data in MLC NOR complements large media storage in SFF HDDs SFF HDD Performs Best When Data can be Buffered into RAM 16

17 HDD in Handset Implementation Solutions Scale High to Low Data Flash MLC NOR LP DRAM MLC NOR 1T RAM MLC NOR SFF HDD MLC NOR LP DRAM Card Slot Card Slot Media Data: Large file data such as MPEG4 video, MP3 songs Code + Key Data: OS, Driver, Applications plus Key System Data and Databases RAM: Working system memory & media data buffered from HDD 1T/6T RAM HDD and MLC NOR Complementary Solutions in Media-Heavy Handsets 17

18 CE-ATA Industry Workgroup Consortium focused on defining a standard interface for storage devices optimized for handheld and consumer electronics applications Led by major industry-leading consumer electronics, storage and semiconductor companies Promoter Companies include Hitachi, Intel, Marvell, Nokia, Seagate and Toshiba Workgroup open to additional Contributor company participation 18

19 Evolution of Memory Requirements Evolution of the Memory Subsystem Evolving Role of Storage Future Role of Emerging Memory 19

20 Moore s s Law Continues with FG NVM 1986/1.5µm 1988/1.0µm 1991/0.8µm 1993/0.6µm Visibility for scaling of floating gate clear to 32 nm Forms high hurdle for new technologies to leap 1996/0.4µm 1998/0.25µm 2000/0.18µm 2002/0.13µm 90 nm cell is 1/476 th of 1.5 µm m cell 2004/90nm 2006/65nm 2008/45nm Source: Intel 20

21 Near-term Candidates for Alternative Memory Three leading alternative memories Potential for mainstream adoption within 3 to 5 years All are nonvolatile execution memories But, no credible technology challenger to Flash through

22 Attribute Fit to Requirements Key Attributes Application Fit Applied Electric Field Moves Center Atom FeRAM Cell F² F Fast read/write <10 9 read cycles Low density storage & execution Embedded MRAM Cell F² F Fastest read/write Unlimited R/W cycles High performance working memory Execution & RAM Data Storage Region Chalcogenide Amorphous Phase Change Material Poly Crystalline Hea ter Resistive Electrode OUM Cell 1.5 to 20 F² F Fast read / medium write Unlimited read, write cycles Execution System storage Embedded 22

23 Evolution of Future Handset Storage Floating Gate and SFF HDDs have clear scaling path Other new alternatives are longer term for mainstream adoption (>3 to 5 years) Promise new new price points Cost of 1 st MB FG Memory Multi-Layer Memory Seek and Scan MEMS SFF HDD * Images from Seagate, IBM website GB / $ 23

24 Vision for Future Wireless Subsystems

25 Memory Subsystem Evolution Solutions Scale High to Low Data Flash MLC NOR LP DRAM MLC NOR 1T RAM MLC NOR Card Slot Card Slot Data Flash MLC NOR LP DRAM MLC NOR 1T RAM MLC NOR SFF HDD High performance XIP DDR Flash MLC NOR LP DRAM Enhanced security solutions Card Slot Faster 4+ Mb/sec write Card Slot 1T/6T RAM 1T/6T RAM 2005 Next 25

26 Future Technology Vision Solutions Must Scale High to Low Data Flash MLC NOR LP DRAM MLC NOR 1T RAM MLC NOR 1T/6T RAM SFF HDD MLC NOR LP DRAM Card Slot Card Slot MEMS? MLM? OUM xram OUM xram OUM Integrated Card Slot Card Slot Next 2010+? 26

27 Summary & Conclusions XIP MLC NOR is at the core of the best wireless memory subsystems Best solution scales across the wide range of needs Intel extending memory solution with higher performance, increased security SFF HDD complements XIP NOR in media-intensive intensive applications Phase change memory best candidate for near-term alternative 27

28 Thank You