5. Delta-Sigma Modulators for ADC
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1 Basics Architectures SC Modeling Assisted Low-Power 1/46 5. Delta-Sigma Modulators for ADC Francesc Serra Graells Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated Circuits and Systems IMB-CNM(CSIC)
2 Basics Architectures SC Modeling Assisted Low-Power 2/46 1 Oversampling and Noise Shaping Principles 2 3 Architecture Selection Based on Quantization Error Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
3 Basics Architectures SC Modeling Assisted Low-Power 3/46 1 Oversampling and Noise Shaping Principles 2 3 Architecture Selection Based on Quantization Error Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
4 Basics Architectures SC Modeling Assisted Low-Power 4/46 Oversampling e.g. 5-level quantization Constant (white) error spectrum profile signal amplitude error amplitude signal amplitude error amplitude 2-times sampling rate
5 Basics Architectures SC Modeling Assisted Low-Power 5/46 Oversampling Constant (white) error spectrum profile Power spectral density (PSD) Same power (total area) Nyquist rate Spread across spectrum (fs/2) dependent from sampling frequency Oversampling rate Oversampling ratio Lower in-band noise Higher clock frequencies Dynamic Range Power
6 Basics Architectures SC Modeling Assisted Low-Power 6/46 Quantization Noise Shaping Basic single-loop Delta-Sigma modulator (DSM) for discrete time (DT) ADCs: shaping filter (e.g. integrator) quantizer (e.g. 1-bit) all-pass S/H high-pass shaping Equivalent linear model: signal quantization noise output log(power) signal out-band noise shaping 20dB/dec log(frequency)
7 Basics Architectures SC Modeling Assisted Low-Power 7/46 Quantization Noise Shaping N-order B-bit single loop architecture: S/H multi-bit (B) quantization Multi-bit quantization: Resolution added to overall DR Internal full-scale reduction Feedback DAC not intrinsically linear High-order filtering: Sharper noise shaping Stability issues Ideal dynamic range: shaping order oversampling only log(power) signal (N+0.5)-bit/oct(OSR) 20N db/dec 6N db/oct direct improvement log(frequency)
8 Basics Architectures SC Modeling Assisted Low-Power 8/46 1 Oversampling and Noise Shaping Principles 2 3 Architecture Selection Based on Quantization Error Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
9 Basics Architectures SC Modeling Assisted Low-Power 9/46 Single-Loop vs MASH High-order feedback or feedforward DSM architectures: S/H DAC Unstability issues S/H DAC Cancellation Filter Mismatching sensitivity DAC
10 Basics Architectures SC Modeling Assisted Low-Power 10/46 Single-Loop vs MASH High-order feedback or feedforward DSM architectures: S/H DAC Unstability issues S/H DAC Cancellation Filter Mismatching sensitivity More suitable for DSM DACs! DAC
11 Basics Architectures SC Modeling Assisted Low-Power 11/46 Order Selection Simplest DSM architecture: first-order S/H Intrinsically stable Large OSR needed DAC Tonal spectrum caused by signal to quantization noise correlation! log(power) signal in-band harmonics log(frequency)
12 Basics Architectures SC Modeling Assisted Low-Power 12/46 Order Selection Next architecture step: second-order S/H Intrinsically stable for limited input range Signal to quantization noise uncorrelation (continuous spectrum) DAC Moderate OSR requirements log(power) signal second-order high-pass 40 db/dec 12 db/oct log(frequency)
13 Basics Architectures SC Modeling Assisted Low-Power 13/46 Delta-Sigma Noise Shaping Higher-order general architecture: S/H gain coefficients DAC safe region Sharper noise shaping Possibility of loop instability for N>2 Coefficients optimization against mismatching SNDR maps
14 Basics Architectures SC Modeling Assisted Low-Power 14/46 Commonly Used Architectures Feedfoward cancellation: Internal full scale low occupancy Additional adder stage in front of quantizer S/H Resonator attenuation: DAC Extra noise shaping at band edge Zero sensitivity to coefficient matching log(power) S/H zero DAC log(frequency)
15 Basics Architectures SC Modeling Assisted Low-Power 15/46 1 Oversampling and Noise Shaping Principles 2 3 Architecture Selection Based on Quantization Error Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
16 Basics Architectures SC Modeling Assisted Low-Power 16/46 SC Integrator Shaping filter basic building block: SC-OpAmp compact implementation: gain function integration function for initialization purposes single-ended circuit version Analog circuit realization (ADC) Digital circuit realization (DAC) non-overlapping phases clock S I
17 Basics Architectures SC Modeling Assisted Low-Power 17/46 SC Integrator SC-OpAmp compact implementation: clock S I
18 Basics Architectures SC Modeling Assisted Low-Power 18/46 SC Integrator SC-OpAmp compact implementation: clock S I
19 Basics Architectures SC Modeling Assisted Low-Power 19/46 SC Integrator SC-OpAmp compact implementation:
20 Basics Architectures SC Modeling Assisted Low-Power 20/46 SC Noise Shaper Fully-differential 2nd-order single-bit DSM example: feedforward signal cancellation S/H differential signal domain
21 Basics Architectures SC Modeling Assisted Low-Power 21/46 SC Noise Shaper S/H Fully-differential 2nd-order single-bit DSM example: common mode input sampler reused for DAC feedback
22 Basics Architectures SC Modeling Assisted Low-Power 22/46 SC Noise Shaper S/H Fully-differential 2nd-order single-bit DSM example: integrator initialization
23 Basics Architectures SC Modeling Assisted Low-Power 23/46 SC Noise Shaper S/H Fully-differential 2nd-order single-bit DSM example: passive adder -6dB attenuation negligible thanks to 1-bit quantization
24 Basics Architectures SC Modeling Assisted Low-Power 24/46 1 Oversampling and Noise Shaping Principles 2 3 Architecture Selection Based on Quantization Error Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
25 Basics Architectures SC Modeling Assisted Low-Power 25/46 Switch Thermal Noise Added to signal at input sampler: oversampling extension switch on-resistance
26 Basics Architectures SC Modeling Assisted Low-Power 26/46 Switch Thermal Noise Added to signal at input sampler: Dynamic range Power & area oversampling extension switch on-resistance Fully differential contributions: Large capacitor area and low input impedance values!
27 Basics Architectures SC Modeling Assisted Low-Power 27/46 Clock Jitter Critical at input sampler due to its continuous (CT) to discrete time (DT) conversion: Dynamic range External references jitter error S H already in DT! jitter probability estimated power under harmonic stimulus:
28 Basics Architectures SC Modeling Assisted Low-Power 28/46 OpAmp Finite Gain SC integrator transfer function when OpAmp open loop gain is limited: equivalent single ended half circuit more relevant in first stages
29 Basics Architectures SC Modeling Assisted Low-Power 29/46 OpAmp Finite Gain SC integrator transfer function when OpAmp open loop gain is limited: integration leakage gain mismatch
30 Basics Architectures SC Modeling Assisted Low-Power 30/46 OpAmp Finite Gain SC integrator transfer function when OpAmp open loop gain is limited: integration leakage gain mismatch Signal dependent gain generates output distortion
31 Basics Architectures SC Modeling Assisted Low-Power 31/46 OpAmp Slew-Rate and GBW Qualitative case studies: OpAmp works as a charge pump during integration phase current limitation!
32 Basics Architectures SC Modeling Assisted Low-Power 32/46 OpAmp Slew-Rate and GBW Qualitative case studies: frequency transfer function!
33 Basics Architectures SC Modeling Assisted Low-Power 33/46 OpAmp Slew-Rate and GBW Qualitative case studies: Non-linear errors = signal distortion mixed limitation!
34 Basics Architectures SC Modeling Assisted Low-Power 34/46 Feedback DAC Non-Linearity Only for multi-bit DSM architectures: INL/DNL directly added to signal input! quantizer non-linearity shaped as error How to get rid of feedback flash DAC non-linearity effects?
35 Basics Architectures SC Modeling Assisted Low-Power 35/46 1 Oversampling and Noise Shaping Principles 2 3 Architecture Selection Based on Quantization Error Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
36 Basics Architectures SC Modeling Assisted Low-Power 36/46 Feedback DAC Mismatching Single-stage multi-bit SC flash architecture example: reset single-ended version
37 Basics Architectures SC Modeling Assisted Low-Power 37/46 Feedback DAC Mismatching Single-stage multi-bit SC flash architecture example: hardwired binary weighted Simple digital control
38 Basics Architectures SC Modeling Assisted Low-Power 38/46 Feedback DAC Mismatching Single-stage multi-bit SC flash architecture example: technology mismatching hardwired binary weighted Pelgrom's Law in-band harmonics Simple digital control Distortion caused by static mismatching
39 Basics Architectures SC Modeling Assisted Low-Power 39/46 Feedback DAC Mismatching Single-stage multi-bit SC flash architecture example: thermometric dynamic selection technology mismatching bin to therm rand om izer Pelgrom's Law Complex digital control in-band white noise Low in-band noise by thermometric scrambling
40 Basics Architectures SC Modeling Assisted Low-Power 40/46 Feedback DAC Mismatching Single-stage multi-bit SC flash architecture example: dynamic element matching (DEM) technology mismatching bin to therm DWA data-wieghted averaging dB/dec first-order shaping Complex digital control barrel shifting Mismatch shaping by equalizing long-term element selection
41 Basics Architectures SC Modeling Assisted Low-Power 41/46 1 Oversampling and Noise Shaping Principles 2 Architecture Selection Based on Quantization Error 3 Switched-Capacitor CMOS Implementations 4 Modeling Circuit Second Order Effects 5 Digitally Assisted Techniques 6 Low-Power Circuit Topologies
42 Basics Architectures SC Modeling Assisted Low-Power 42/46 Switched OpAmp (SOA) Distortion caused by signal-dependent switch on-resistance: INL/DNL directly added to signal input! quantizer non-linearity shaped as error How to make on-resistance independent from signal for these particular switches?
43 Basics Architectures SC Modeling Assisted Low-Power 43/46 Switched OpAmp (SOA) Moving output switches into OpAmp blocks: single-ended circuit version clock S I Constant on-resistance for all switches Power savings due to 50% OpAmp duty cycle Each integrator stage operates in alternative phases
44 Basics Architectures SC Modeling Assisted Low-Power 44/46 Switched OpAmp (SOA) Moving output switches into OpAmp blocks: M4 M3 M5 M6 M1 M2 M7 M8 Example: single-ended single-stage folded OpAmp Constant on-resistance for all switches Power savings due to 50% OpAmp duty cycle Each integrator stage operates in alternative phases
45 Basics Architectures SC Modeling Assisted Low-Power 45/46 OpAmp Dynamic Biasing Discrete time dynamic biasing: M4 M3 M5 M6 M1 M2 M7 M8 M9 M10 clock S I time
46 Basics Architectures SC Modeling Assisted Low-Power 46/46 OpAmp Dynamic Biasing Discrete time dynamic biasing: M4 M3 M5 M6 Synchronous Class-AB operation Static power savings M7 M1 M2 M8 OpAmp fast on/off recovery time required M9 M10 Biasing peak value is technology dependent Ripple induced in the power rails (digital-like) time
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