SPECIAL TOPICS IN COMPUTER ARCHITECTURE AND VLSI DESIGN: Prof. Youngcheol Chae Office: Room B712, Office Hours: Fri.

Transcription

1 SPECIAL TOPICS IN COMPUTER ARCHITECTURE AND VLSI DESIGN: Overview of Data Converters Prof. Youngcheol Chae Office: Room B712, Office Hours: Fri. 4~6PM

2 Related Course Mixed SignalVLSI (EEE 6632) : Graduate Course Covers Data Converters (ADCs and DACs) Prerequisites Microelectronics II, CMOS VLSI Analog VLSI or equivalent (e.g. transistor level circuit design including opamp) Prior exposure to Spectre or Hspice EEE Spring 2013 Slide 2

3 Outline of EEE 6632 Sampling and quantization DAC architecture Sample andhold Switched capacitor circuits Comparators Nyquist rate conversion Oversampled conversion Limits in accuracy Calibration, DEM, and DWA Test andspecification EEE Spring 2013 Slide 3

4 Motivation All electronic systems rely on data converters EEE Spring 2013 Slide 4

5 Motivation ADC / DAC : Interface Between Analog Media and DSP System Higher Performance of Data Converters Required Trends of SoC Implementation Main Bottleneck ofdesigntime andresources EEE Spring 2013 Slide 5

6 System Design Trend VLSI Design & Tech Improvement More Signal Processing Performed in Digital Signal Domain Implementation Trend : A B Partition Criteria Determined Mainly By Available Design Resources of Analog Front End Such as ADC/DAC & ASP (Analog Signal Processing) Required Performance Specifications : (B) > (A) Applications & System Requirements EEE Spring 2013 Slide 6

7 A/D Converter Application Space EEE Spring 2013 Slide 7

8 Analog IC Market EEE Spring 2013 Slide 8

9 Example 1 Source: EEE Spring 2013 Slide 9 9

10 Example 1 EEE Spring 2013 Slide 10 10

11 Example 2 EEE Spring 2013 Slide 11

12 Example 3 EEE Spring 2013 Slide 12

13 The Data Conversion Problem EEE Spring 2013 Slide 13

14 Overview EEE Spring 2013 Slide 14

15 Performance metric of Data Converter Number of Bits Data Conversion Rate Power Dissipation / Hardware Area Static Parameters Gain & Offset Errors Non Linearity : DNL (Differential), INL (Integral) Non Monotonicity, Missing Codes Dynamic Parameters SNR (Signal to Noise Ratio) THD (Total Harmonic Distortion) SNDR (Signal to {Noise+Distortion} Ratio) ENOB (Effective Number of Bits) Signal Bandwidth EEE Spring 2013 Slide 15

16 Let s look at Data Sheet EEE Spring 2013 Slide 16

17 Input/Output p Relation DAC ADC EEE Spring 2013 Slide 17

18 Static Errors Linear Errors: Offset, Gain errors Non-monotonicity, Missing Codes Non Linear Errors EEE Spring 2013 Slide 18

19 Static Errors Differential Non-Linearity it (DNL) Integral Non-Linearity it (INL) EEE Spring 2013 Slide 19

20 Quantization Error (Noise) Digital-Out q 1 /2 2 2 /2 2 x dx 12 V FS N 2 2 Signal Power: SNR P ( f ) S P S (f) P (f) P N N N Error SNR(dB) P S (db) 6.02 N 1.76 P N EEE Spring 2013 Slide 20

21 Dynamic Errors SNR Peak SNR 0dB Dynamic range Amplitude EEE Spring 2013 Slide 21

22 Anti Alias Filtering Brick Wall Attenuation f s 2f s f f s 2f s f 0.5 f/f s 0.5 f/f s Ideal AAF Real AAF EEE Spring 2013 Slide 22

23 Sampling & AAF In order to prevent aliasing, we need f sig,max < f s /2 The sampling rate f s=2f sig,max is called Nyquist rate Can tradeoff sampling speed against filter order In high speed converters, making f s /f sigmax > 10 is usually impossible, therefore we need fairly high order filters EEE Spring 2013 Slide 23

24 Classes of Sampling EEE Spring 2013 Slide 24

25 Classification of ADCs ADC Nyquist-rate Oversampled Flash Two-step Pipeline e Successive approximation Algorithmic Dual Slope... SC (Switched-Capacitor) Sigma-delta implementations CT (Continuous-Time) implementations EEE Spring 2013 Slide 25

26 Example: Flash ADC EEE Spring 2013 Slide 26

27 Performance Limits [pj] P/f snyq 1.E+07 1.E+06 1E+05 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 ISSCC 2013 VLSI 2012 ISSCC VLSI FOMW=10fJ/conv-step FOMS=170dB Nyquist [db] EEE Spring 2013 Slide 27

28 Results from Yonsei ISSCC 13 High precision SAR+ hybrid ADC 20bit resolution, 6ppm INL, 1uV offset, and 6.3uW power EEE Spring 2013 Slide 28

29 Performance Limits z] BW [H 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 ISSCC 2013 VLSI 2012 ISSCC VLSI Jitter=1psrms Jitter=0.1psrms SNDR [db] EEE Spring 2013 Slide 29

30 Ideal DAC EEE Spring 2013 Slide 30

31 The Reconstruction Problem EEE Spring 2013 Slide 31

32 Zero-Order Hold Reconstruction EEE Spring 2013 Slide 32

33 Dirac Pulses EEE Spring 2013 Slide 33

34 Spectrum EEE Spring 2013 Slide 34

35 Finite Hold Pulse EEE Spring 2013 Slide 35

36 Envelope with Hold Pulse Tp=Ts EEE Spring 2013 Slide 36

37 Example EEE Spring 2013 Slide 37

38 Reconstruction Filter EEE Spring 2013 Slide 38

39 Example: Resistor String DAC Resistors : Current Division Capacitors : Charge Division Transistors : Current Division iii EEE Spring 2013 Slide 39

40 Overview EEE Spring 2013 Slide 40

41 Thank you for your attention! Prof. Youngcheol Chae Office: Room B712, Office Hours: Fri. 4~6PM 41