Cypress Semiconductor Process Qualification Report

Transcription

1 Cypress Semiconductor rocess Qualification Report QT# VERSION 1.0 March 2005 TSMC 0.5um Logic3 Device Family, Fab2 CYW305B CY28323B CY28349B CY28325B-3 Frequency Controller with System Recovery for Intel Integrated Core Logic FTG for Intel entium 4 CU and Chipsets FTG for Intel entium 4 CU and Chipsets FTG for Via entium 4 CU and Chipsets CYRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Rene Rodger Sabbas Daniel rincipal Reliability Engineer Quality Engineering Director (408) (408)

2 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 2 of 8 RODUCT QUALIFICATION HISTORY Qual Report Description of Qualification urpose Date Comp TSMC Logic 3 (0.5um) Technology transfer to Fab2 Feb 03

3 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 3 of 8 RODUCT DESCRITION (for qualification) Qualification urpose: Qualify TT105 - W305B device family 0.5um Technology in Fab 2B Marketing art #: CYW305B, CY28323B, CY28349B, CY28325B-3 Device Description: 3.3V, Commercial available in 48/56-pin SSO package Cypress Division: Cypress Semiconductor Corporation - Timing Technology Division (SJ) Overall Die (or Mask) REV Level (pre-requisite for qualification): Rev. A What ID markings on Die: 7C8305A, 7C8323A, 7C8349A, 7C8325A TECHNOLOGY/FAB ROCESS DESCRITION Number of Metal Layers: 2 Metal Composition: Metal 1: Al/Cu/Si/TiN = 4,000Å/1,400Å Metal 2: Al/Cu/Si/TiN = 8,000Å/250Å assivation Type and Materials: EOX / ESIN Free hosphorus contents in top glass layer (%): 0% Number of Transistors in Device: 38,431 Number of Gates in Device: N/A Generic rocess Technology/Design Rule (µ-drawn): CMOS, Single oly, Double Metal, TSMC 0.50 µm Logic Gate Oxide Material/Thickness (MOS): SiO 2 / 85Å Name/Location of Die Fab (prime) Facility: Fab 2B Hsinchu - Taiwan Die Fab Line ID/Wafer rocess ID: Fab 2B ACKAGE AVAILABILITY 48/56-Lead SSO ACKAGE TYE CSI-R, ASE/OSE Taiwan, Anam Korea ASSEMBLY SITE FACILITY

4 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 4 of 8 MAJOR ACKAGE INFORMATION USED IN THIS QUALIFICATION ackage Designation: 056 ackage Outline, Type, or Name: 56-lead Shrunk Small Outline ackage (SSO) Mold Compound Name/Manufacturer: EME 6600HR/Sumitomo Mold Compound Flammability Rating: V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Copper Lead Finish, Composition / Thickness: Snb (300~800 uinch) Die Backside reparation Method/Metallization: Grinding Die Separation Method: Wafer Saw Die Attach Method: Dispensing Die Attach Supplier: Dexter Die Attach Material: QMI509 Bond Diagram Designation Wire Bond Method: Thermosonic Wire Material/Size: 1.0mil Thermal Resistance Theta JA C/W: C/W ackage Cross Section Yes/No: N/A Assembly rocess Flow: Name/Location of Assembly (prime) facility: CML ELECTRICAL TEST / FINISH DESCRITION Test Location: CML Fault Coverage: 100%

5 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 5 of 8 RELIABILITY TESTS ERFORMED ER SECIFICATION REQUIREMENTS Stress/Test Test Condition (Temp/Bias) Result /F High Temperature Operating Life Early Failure Rate High Temperature Operating Life Latent Failure Rate Dynamic Operating Condition, Vcc = 3.8V, 150 C Dynamic Operating Condition, Vcc = 3.8V, 150 C Long Life Verification Dynamic Operating Condition, Vcc = 3.8V, 150 C High Temperature Steady State Life Static Operating Condition, Vcc = 3.6V, 150 C Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65ºC to 150ºC recondition: JESD22 Moisture Sensitivity MSL hrs, 85ºC, 85%RH+3IR-Reflow, 235 C+5, -0 C High Accelerated Saturation Test (HAST) ressure Cooker 130ºC, 85%RH, 3.63V recondition: JESD22 Moisture Sensitivity MSL hrs, 85ºC, 85%RH +3IR-Reflow, 235 C+5, -0 C 121C, 100%RH recondition: JESD22 Moisture Sensitivity MSL hrs, 85ºC, 85%RH +3IR-Reflow, 235 C+5, -0 C High Temp Storage 165 C, no bias Dynamic Latch up Sensitivity In accordance with JEDEC 17. Cypress Spec Acoustic Microscopy MSL1 Cypress Spec Aged Bond Strength MIL-STD-883, Method 2011 Latch up Sensitivity 125ºC, 10V, ± 300mA In accordance with JEDEC 17. Cypress Spec

6 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 6 of 8 RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Device Hours # Fails Activation Energy Thermal 3 A.F Failure Rate High Temperature Operating Life Early Failure Rate High Temperature Operating Life 1, 2 Long Term Failure Rate 3,044 Devices 0 N/A N/A 0 M 179,000 DHRs FIT 1 Assuming an ambient temperature of 55 C and a junction temperature rise of 15 C. 2 Chi-squared 60% estimations used to calculate the failure rate. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation AF = exp E k A 1 T T1 where: E A =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 ev/kelvin. T 1 is the junction temperature of the device under stress and T 2 is the junction temperature of the device at use conditions.

7 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 7 of 8 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism STRESS: ACOUSTIC-MSL1 W305B-OC (W305B) TAIWN-OS COM 15 0 W305B-OC (W305B) A TAIWN-OS COM 15 0 W305B-OC (W305B) TAIWN-OS COM 15 0 STRESS: AGE BOND W305B-OC (W305B) TAIWN-OS COM 15 0 W305B-OC (W305B) A TAIWN-OS COM 15 0 W305B-OC (W305B) TAIWN-OS COM 15 0 STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (150C, 3.8V, Vcc Max) W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) TAIWN-OS STRESS: HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE (150C, 3.8V, Vcc Max) W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) TAIWN-OS STRESS: LONG LIFE VERIFICATION (150C, 3.8V) W305B-OC (W305B) TAIWN-OS STRESS: HIGH TEM STEADY STATE LIFE, (150C, 3.6V, Vcc Max) W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) A TAIWN-OS STRESS: STATIC LATCH-U TESTING (125C, 10V, +/300mA) W305B-OC (W305B) TAIWN-OS COM 3 0 W305B-OC (W305B) A TAIWN-OS COM 3 0 W305B-OC (W305B) TAIWN-OS COM 3 0 STRESS: DYNAMIC LATCH-U TESTING CY28349BOC (7C8349A) CML-R COM 3 0 STRESS: HIGH TEMERATURE STORAGE, no bias W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) A TAIWN-OS STRESS: RESSURE COOKER TEST (121C, 100%RH), RE COND 168 HR 85C/85%RH, MSL1) W305B-OC (W305B) TAIWN-OS Cut Wedge on Identified Failing in W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) TAIWN-OS

8 Cypress Semiconductor QT# , V. 1.0 Logic-3 Device Family, 0.5um, TSMC Fab 2 age 8 of 8 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Ass Loc Duration Samp Rej Failure Mechanism STRESS: HI-ACCEL SATURATION TEST (130C, 85%RH, 3.6V, RE COND 168 HR 85C/85%RH, MSL1) W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) TAIWN-OS STRESS: TC COND. C -65C TO 150C, RECONDITION 168 HRS 85C/85%RH (MSL1) W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) A TAIWN-OS W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) TAIWN-OS W305B-OC (W305B) TAIWN-OS