Qualification Report. January, 1995 QTP# Version 1.3. FAB µm FCT-T PRODUCTS

Size: px

Start display at page:

Download "Qualification Report. January, 1995 QTP# Version 1.3. FAB µm FCT-T PRODUCTS"

Leo Waters
5 years ago
Views:

1 Qualification Rept January, 1995 QTP# Version 1.3 FB µm FT-T PRODUTS

3 PGE 3 YPRESS SEMIONDUTOR PRODUT DESRIPTION (f qualification) Infmation provided in this document is intended f generic qualification and technically describes the ypress part supplied: Marketing Part #: Device Description: ypress Division: Y54/74T573T FT-T LOGI PRODUTS ypress Semiconduct pation Overall Die ( Mask) REV Level (pre-requisite f qualification): Die Size (stepping): 65 mils x 67 mils What markings on Die: FT573 ypress Qualification completion/marketing vailability Dates (urrent REV): Feb/1994 Now TEHNOLOGY/FB PROESS DESRIPTION - LOGI2.7 Number of Metal Layers: 2 Metal omposition: Metal 1: 500 Ti/1,200 TiW/6,000 l/1,200 TiW Metal 2: 1,500 TiW/10,000 l/150 Ti Passivation and Materials: Free Phosphus contents in top glass layer(%): Die oating(s), if used: N/ 7,000 TEOS 6,000 Generic Process Technology/Design Rule (µ-drawn): MOS, Single Poly, Double Metal /0.65 µm Gate Oxide Material/Thickness (MOS): Name/Location of Die Fab (prime) Facility: Die Fab Line /Wafer Process : None SiO2 / 145 ypress Semiconduct, Bloomington, MN Fab 3 / LG27

4 PGE 4 YPRESS SEMIONDUTOR PLSTI PKGE/SSEMBLY DESRIPTION Package Outline,, Name: 20-pin,300-mil Plastic DIP Die to Package edge clearance: 92 mils per side Mold ompound Name/Manufacturer: EME-6300H(R) Lead Frame material: opper Lead Finish, composition: Solder Dipped, 63%Sn, 37%Pb Die ttach rea Plating: Silver Die ttach Pad Dim: 110 mils x 140 mils Die ttach Method: Epoxy Die ttach Material: Silver Epoxy Wire Bond Method: Thermocompression Wire Material/Size: Gold / 1.3 mil Name/Location of ssembly (prime) facility: ssembly Line and Process : INDNS-O / P27 HERMETI PKGE/SSEMBLY DESRIPTION Package Outline,, Name: 20-pin, 300-mil erdip Die to Package edge clearance: 114 mils per side Mold ompound Name/Manufacturer: N/ Lead Frame material: lloy 42 Lead Finish, composition: Solder Dipped, 63%Sn, 37%Pb Die ttach rea Plating: None Die ttach Pad Dim: 130 mils x 200 mils Die ttach Method: Silver Glass Die ttach Material: OMI 2419 Wire Bond Method: Ultrasonic Wire Material/Size: luminum / 1.25 mil Name/Location of ssembly (prime) facility: ssembly Line and Process : LPH- / D2

5 PGE 5 YPRESS SEMIONDUTOR OTHER INFORMTION F approval by similarity, identify other devices using the same basic die with bonding metal mask options test selections and explain: "7114" mask set, "7112" mask set If ypress is planning any changes in the near future, identify change (Qtr/Yr) in: Die Design Rev./Shrink: Fab/ssembly site change: Die Process hange: ross Licensee/Licens: Other Devices to be qualified in this technology: LOGI2.7: ll 16/20/24 pin FT-T family (Y54/74FT***T) YBUS3384 Other Packages to be qualified f this device: SOI, QSOP, L ESD Voltage Rating (per MIL STD-008, Method 3018): Flammability lassification (UL-94V): 1/8 None lternate Fab/ssembly Locations: ssembly: stra, Indonesia Please attach the following Qualification / Reliability data f the die revision and Package type, f the fab and assembly sites identified above (mark [] if included): 1 HST (5.5V, 130, 85%RH, 15psig) 7 Operating Life at (temp): Temperature ycles (-65 to 150 ) 8 Steady State Life (HTSSL, 5.75V, 150 ) 3 Temperature ycles (-40 to 165 ) 9 Temperature Humidity Bias (5.5V, 85, 85%RH) 4 Data Retention Bake, Plastic (165 ) 10 Latchup Testing 5 Data Retention Bake, Hermetic (250 ) 11 ESD Tests (MIL-STD 883, method 3015) 6 utoclave (PT, 121, 100%RH) 12 Other: urrent Density Input apacitance Read & Recd Life Test Internal Water Vap ged Bond Strength Long Life Verification

6 PGE 6 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 16/20 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. (mm/yy) Y54/74FT573/*TP Y54/74FT573/*TQ Y54/74FT573/*TSO Y54/74FT573/*TDMB Y54/74FT573/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT138/*TP Y54/74FT138/*TQ Y54/74FT138/*TSO Y54/74FT138/*TDMB Y54/74FT138/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT157/*TP Y54/74FT157/*TQ Y54/74FT157/*TSO Y54/74FT157/*TDMB Y54/74FT157/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT158/*TP Y54/74FT158/*TQ Y54/74FT158/*TSO Y54/74FT158/*TDMB Y54/74FT158/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia * an be replaced by speed.

7 PGE 7 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 16/20 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT163/*TP Y54/74FT163/*TQ Y54/74FT163/*TSO Y54/74FT163/*TDMB Y54/74FT163/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO Omedata,Indonesia Dynesem,Philippine stra,indonesia Y54/74FT191/*TP Y54/74FT191/*TQ Y54/74FT191/*TSO Y54/74FT191/*TDMB Y54/74FT191/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO Omedata,Indonesia Dynesem,Philippine stra,indonesia Y54/74FT240/*TP Y54/74FT240/*TQ Y54/74FT240/*TSO Y54/74FT240/*TDMB Y54/74FT240/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO Omedata,Indonesia Dynesem,Philippine stra,indonesia Y54/74FT244/*TP Y54/74FT244/*TQ Y54/74FT244/*TSO Y54/74FT244/*TDMB Y54/74FT244/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO Omedata,Indonesia Dynesem,Philippine stra,indonesia * an be replaced by speed.

8 PGE 8 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 16/20 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT245/*TP Y54/74FT245/*TQ Y54/74FT245/*TSO Y54/74FT245/*TDMB Y54/74FT245/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO Dynesem, Phillipine stra, Indonesia >2,00 0V Y54/74FT257/*TP Y54/74FT257/*TQ Y54/74FT257/*TSO Y54/74FT257/*TDMB Y54/74FT257/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO Dynesem, Phillipine stra, Indonesia >2,00 0V Y54/74FT273/*TP Y54/74FT273/*TQ Y54/74FT273/*TSO Y54/74FT273/*TDMB Y54/74FT273/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO Dynesem, Phillipine stra, Indonesia >2,00 0V Y54/74FT373/*TP Y54/74FT373/*TQ Y54/74FT373/*TSO Y54/74FT373/*TDMB Y54/74FT373/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO Dynesem, Phillipine stra, Indonesia >2,00 0V * an be replaced by speed.

9 PGE 9 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 16/20 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT374/*TP Y54/74FT374/*TQ Y54/74FT374/*TSO Y54/74FT374/*TDMB Y54/74FT374/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT377/*TP Y54/74FT377/*TQ Y54/74FT377/*TSO Y54/74FT377/*TDMB Y54/74FT377/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT399/*TP Y54/74FT399/*TQ Y54/74FT399/*TSO Y54/74FT399/*TDMB Y54/74FT399/*TLMB () pins PDIP 16 pins QSOP 16 pins SOI 16 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT540/*TP Y54/74FT540/*TQ Y54/74FT540/*TSO Y54/74FT540/*TDMB Y54/74FT540/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia * an be replaced by speed.

10 PGE 10 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 16/20 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT541/*TP Y54/74FT541/*TQ Y54/74FT541/*TSO Y54/74FT541/*TDMB Y54/74FT541/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia Y54/74FT574/*TP Y54/74FT574/*TQ Y54/74FT574/*TSO Y54/74FT574/*TDMB Y54/74FT574/*TLMB () pins SOI 20 pins DIP 20 pins L 65 x µ MOS 3 LTO stra, Indonesia * an be replaced by speed.

11 PGE 11 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 24 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y29FT52/*TP Y29FT52/*TQ Y29FT52/*TSO Y29FT52/*TDMB Y29FT52/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y29FT520/*TP Y29FT520/*TQ Y29FT520/*TSO Y29FT520/*TDMB Y29FT520/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y29FT818/*TP Y29FT818/*TQ Y29FT818/*TSO Y29FT818/*TDMB Y29FT818/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT480/*TP Y54/74FT480/*TQ Y54/74FT480/*TSO Y54/74FT480/*TDMB Y54/74FT480/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia * an be replaced by, B speed.

12 PGE 12 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 24 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT543/*TP Y54/74FT543/*TQ Y54/74FT543/*TSO Y54/74FT543/*TDMB Y54/74FT543/*TLMB () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT646/*TP Y54/74FT646/*TQ Y54/74FT646/*TSO Y54/74FT646/*TDMB Y54/74FT646/*TLMB () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT648/*TP Y54/74FT648/*TQ Y54/74FT648/*TSO Y54/74FT648/*TDMB Y54/74FT648/*TLMB () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT652/*TP Y54/74FT652/*TQ Y54/74FT652/*TSO Y54/74FT652/*TDMB Y54/74FT652/*TLMB () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia * an be replaced by, B speed.

13 PGE 13 YPRESS SEMIONDUTOR Product Family: Mfg Division: PRODUT INFORMTION FOR QULIFITION BY SIMILRITY 24 pins FT-T 0.65µm Technology ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT821/*TP Y54/74FT821/*TQ Y54/74FT821/*TSO Y54/74FT821/*TDMB Y54/74FT821/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT823/*TP Y54/74FT823/*TQ Y54/74FT823/*TSO Y54/74FT823/*TDMB Y54/74FT823/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT825/*TP Y54/74FT825/*TQ Y54/74FT825/*TSO Y54/74FT825/*TDMB Y54/74FT825/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia Y54/74FT827/*TP Y54/74FT827/*TQ Y54/74FT827/*TSO Y54/74FT827/*TDMB Y54/74FT827/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia

14 PGE 14 YPRESS SEMIONDUTOR * an be replaced by, B speed. PRODUT INFORMTION FOR QULIFITION BY SIMILRITY Product Family: 24 pins FT-T 0.65µm Technology Mfg Division: ypress Semiconduct Supplier's Part Number Rated (ns) Pkg Size/ Die Rev. Die Size mil x mil (stepping) Design Rule (µ) Fabrication Process Line Passivation Mold ompound ssembly Line Location ESD Volt Rating vail. mm/yy Y54/74FT841/*TP Y54/74FT841/*TQ Y54/74FT841/*TSO Y54/74FT841/*TDMB Y54/74FT841/*TLMB B () pins SOI 24 pins DIP 28 pins L 72 x µ MOS 3 LTO stra, Indonesia YBUS3384P YBUS3384Q YBUS3384SO 0 to 0.25 ns 24 pins SOI 72 x µ MOS 3 LTO stra, Indonesia * an be replaced by, B speed.

15 PGE 15 YPRESS SEMIONDUTOR DEVIE RELIBILITY SUMMRY Marketing Part: Y74FT573 Wafer Fab: Fab3 - Bloomington, MN Pkg Description: 20-pin,300-mil PDIP 20-pin,300-mil DIP 24-pin QSOP ssembly: High Temperature Dynamic Operating Life (HTOL, 5.75V, 150 ) - Early Failure Rate Device ssy Lot# Fab Lot # 48 Hours umulative FT573-D /340 0/1089 FT573-P /409 1 FT573-P /340 High Temperature Dynamic Operating Life (HTOL, 5.75V, 150 ) - Latent Failure Rate Device ssy Lot# Fab Lot# 80 Hours 500 Hours umulative FT573-P / /105 0/465 FT573-P /120 FT573-D /120 0/120 High Temperature Steady State Life Test (HTSSL, 5.75V, 150 ) Device ssy Lot# Fab Lot# 80 Hours 168 Hours umulative FT573-P /80 0/80 0/240 FT573-P /80 0/80 FT573-D /80 0/80 Temperature ycle (ondition, -65 to 150 ) Device ssy Lot# Fab Lot# 100 ycles 300 ycles 1000 ycles umulative FT573-P /45 0/45 0/145 FT573-P /50 0/50 FT573-D /50 0/50 FT827Z-QSOP P /45 0/45 FT727Z-QSOP P /45 0/ Destroyed during test EOS.

16 PGE 16 YPRESS SEMIONDUTOR utoclave (PT, No bias, 121, 100%RH, 15psig) Device ssy Lot# Fab Lot# 168 Hours umulative FT573-P /45 0/95 FT573-P /50 High ccelerated Saturation Test (HST, 5.5V, 140, 85%RH, 15psig) Device ssy Lot# Fab Lot# 128 Hours umulative FT573-P /45 0/95 FT573-P /50 Read & Recd (5.75V, 150 ) Device ssy Lot# Fab Lot# 48 Hours 80 Hours 500 Hours umulative FT573-P /10 0/10 0/20 FT573-P /10 0/10 0/10 old Life (LTOL, 6.5V, -45 ) Device ssy Lot# Fab Lot# 500 Hours umulative FT573-P /45 0/45 Long Life Verification (LLV, 5.75V, 150 ) Device ssy Lot# Fab Lot# 1000 Hours umulative FT573-P /105 0/105

17 PGE 17 YPRESS SEMIONDUTOR Device Reliability Summary FB µm FT-T TEHNOLOGY Y74FT573/*T Electrostatic Discharge Human Body Model ircuit per Mil 883, Method 3015 Unit 1 >-2,000V Unit 2 >-2,000V Unit 3 >-2,000V (Highest passing voltage, 10% Guard banded) Latchup Testing to ypress Internal Latch-up Procedure 3 Tests: urrent Injection = 200m Trigger Hot Socket = V 0-7V V Oscillation V = V at 1MHz Temp = 150 Other miscellaneous tests urrent Density Input apacitance Internal Water Vap ged Bond Strength Pass Pass Pass Pass

18 PGE 18 YPRESS SEMIONDUTOR YPRESS QULIFITION REPORT Marketing Part: Y719*/Y7627 Prod. Family: SRM ompletion Date: October, 1993 Process : R25 Technology: MOS 0.65µm Technology Process Location: Fab 3 - Bloomington, MN ypress Test No. Stress/Test Reference Method ctual onditions Status * Qualification Data Reference Test Result Temp/Bias Hrs/yc SS/Fail Pass Fail 22 HTOL - EFR HTOL - LFR /5.75V 80 Hrs 500 Hrs 0/410 2/ /494 0/ High Temp. Bake/DRET 23 HST /5.5V 128 Hrs 0/99 0/ Steam Test/utoclave/PT ,100%RH 15 psig 168 Hrs 0/100 1/ Temperature ycle JEDE22, ond. B --40 to ycs 1000 ycs 0/99 0/46 0/99 0/ Temperature ycle ond. -65 to ycs 1000 ycs 0/50 0/50 37 HTSSL , 5.75V 80 Hrs 168 Hrs 0/245 3/ /243 0/ Mechanical Sequence 26 -Ray 6 ESD- ner Pins Internal Pins ---- / ESD-DM ner Pins Internal Pins ---- / Latch-up / Flammability & Oxygen Index 14 Moisture Resistance 9 Internal Water Vap 2 Solvent Resistance 4 Internal Visual 1 Physical Dimensions 7 Lead Integrity 5 Bond Strength Die Shear Strength

19 PGE 19 YPRESS SEMIONDUTOR 11 Lid Tque bake reversible, both non-visual Marginal fail/uv reversible (trapped charge) Non-visual

Qualification Report 64K RAM 2.1, 7% SHRINK CY7C161/A * CY7C162/A * CY7C164/A * CY7C166/A * CY7C185/A* CY7C187/A *

Qualification Report 64K RAM 2.1, 7% SHRINK CY7C161/A * CY7C162/A * CY7C164/A * CY7C166/A * CY7C185/A* CY7C187/A * Qualification Report November, 1994, QTP# 94012/94133 Version 1.1 64K RAM 2.1, 7% SHRINK MARKETING PART NUMBER Y7161/A * Y7162/A * Y7164/A * Y7166/A * Y7185/A* Y7187/A * DEVIE DESRIPTION 16K x 4 Static