Cypress Semiconductor Product Qualification Report

Transcription

1 Cypress Semiconductor roduct Qualification Report QT# VERSION 1.0 November, 2000 Low Cost VMEbus Interface Controller Family L28ED Technology Fab 2 CY7C960A/CY7C961A CYRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Rene Rodgers Reliability Director Staff Reliability Engineer (408) (408)

2 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 2 of 12 Qual Report Description of Qualification urpose Date New roduct and ackage Qualifcation Feb Military and ackage Qualification Feb Fab Transfer Commercial Mar Fab Transfer (Military) Mar Multilayer Change Commercial (except Metal and Via) Jul Military, Multilayer Change (except Metal and Via) Jul 00

3 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 3 of 12 RODUCT DESCRITION (for qualification) urpose: To qualify multilayer mask change (excluding metal and via) for CY7C960A/CY7C961A, in qualified L28ED Technology, Fab2. Marketing art #: CY7C960A/CY7C961A Device Description: 5V, Military and Commercial available in 64-pin TQF and 64-pin CQF package. Cypress Division: Cypress Semiconductor Corporation Data Com Division (DCD) Overall Die (or Mask) REV Level (pre-requisite for qualification): Rev. B Die Size (stepping): 190 mils x 190 mils What ID markings on Die: 7C960A TECHNOLOGY/FAB ROCESS DESCRITION Number of Metal Layers: 2 Metal Composition: Metal 1: 500A Ti/1,200A TiW/6,000A Al/1,200A TiW Metal 2: 1,500A TiW/10,000A Al/150A Ti assivation Type and Materials: 3,000A TEOS + 15,000A Si 2 N 4 Free hosphorus contents in top glass layer(%): n/a Die Coating(s), if used: n/a Generic rocess Technology/Design Rule (µ-drawn): CMOS, Single oly, Double Metal /0.65 µm Gate Oxide Material/Thickness (MOS): Name/Location of Die Fab (prime) Facility: Die Fab Line ID/Wafer rocess ID: SiO 2 / 145 Å Cypress Semiconductor Round Rock, Texas Fab2/L28ED ACKAGE AVAILABILITY 64-pin TQF 64-pin CQF ACKAGE ASAT Hong Kong (ASAT-B) VLSI USA (USA-V) ASSEMBLY FACILITY SITE Note: ackage Qualification details upon request

4 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 4 of 12 MAJOR ACKAGE INFORMATION USED IN THIS QUALIFICATION ackage Designation: U64A ackage Outline, Type, or Name: 64-pin Ceramic Quad Flatpack ackage (CQF) Lead Frame Material: Alloy 42 Lead Finish, Composition / Thickness: Die Backside reparation Method/Metallization: Die Separation Method: Solder Dip, 63%Sn, 37%b N/A Wafer Saw Die Attach Supplier: QMI Die Attach Material: QMI2569 Bond Diagram Designation Wire Bond Method: Wire Material/Size: ackage Cross Section Yes/No: Ultrasonic Al, 1.25 mil N/A Assembly rocess Flow: Name/Location of Assembly (prime) facility: VLSI USA (USA-V) ELECTRICAL TEST / FINISH DESCRITION Test Location: VLSI USA (USA-V) Fault Coverage: 100%

5 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 5 of 12 RELIABILITY TESTS ERFORMED ER SECIFICATION REQUIREMENT Stress/Test High Temperature Operating Life Early Failure Rate High Temperature Operating Life Latent Failure Rate 1) QT #99421, QT #96512 Test Condition (Temp/Bias) Dynamic Operating Condition, Vcc = 5.75, 125 C 2) QT #96104, QT #98267 Dynamic Operating Condition, Vcc = 5.75, 150C 1) QT #96104, QT #98267 Dynamic Operating Condition, Vcc = 5.75, 125 C Result /F Long Life Verification (Military) 1) QT # C, 5.75V MIL-STD-883C, Method 1005 Temperature Cycle Hermetic 1) QT #96512, QT #98461 MIL-STD-883C, Method 1010, Condition C, -65 C to 150 C Temperature Cycle lastic 1) QT #98461, QT #96104 MIL-STD-883C, Method 1010, Condition C, -65 C to 150 C recondition: JESD22 Moisture Sensitivity MSL Hrs, 30C/60%RH+3IR-Reflow, 220 C+5, 0 C ressure Cooker 1) QT #98267 MIL-STD-883C, Method 1010, Condition C, -65 C to 150 C recondition: JESD22 Moisture Sensitivity MSL 3 High Accelerated Saturation Test (HAST) 192 Hrs, 30C/60%RH+3IR-Reflow, 220 C+5, 0 C 1) QT # C, 5.5V,85%RH recondition: JESD22 Moisture Sensitivity MSL Hrs, 85C/60%RH+3IR-Reflow, 220 C+5, 0 C High Temperature Steady State Life 1) QT #96104 Static Operating Condition, Vcc =5.5V, 125C Read and Record Life Test 1) QT #96104 Electrostatic Discharge Charge Device Model (ESD-CDM) Dynamic Operating Condition, Vcc = 5.75, 125 C 1) QT #99422, QT #98267, QT #98461, QT #96104, QT # V Cypress Spec

6 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 6 of 12 RELIABILITY TESTS ERFORMED ER SECIFICATION REQUIREMENT (continuation) Stress/Test Electrostatic Discharge Human Body Model (ESD-HBM) Test Condition (Temp/Bias) 1) QT #99421, QT #98267, QT #96512, QT # ,200V MIL-STD-883, Method Result /F Military Life Group C 1) QT #98461, QT ## C, 5.75V, MIL-STD-883, Method Input/Output Capacitance Cypress Spec Latchup Sensitivity 1) QT # C, 8,5V, ± 300mA In accordance with JEDEC 17. Cypress Spec

7 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 7 of 12 RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Device Hours # Fails Activation Energy Thermal AF 3 Failure Rate 4 High Temperature Operating Life Early Failure Rate High Temperature Operating Life 1,2, Long Term Failure Rate N/A N/A 126 M 214,808 DHRs FIT. 1 Assuming an ambient temperature of 55 C and a junction temperature rise of 15 C 2 Chi-squared 60% estimations used to calculate the failure rate. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation AF = exp E k A 1 T T1 where: E A =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 ev/kelvin. T 1 is the junction temperature of the device under stress and T 2 is the junction temperature of the device at use conditions.. 4 Early Failure Rate based on QT 99421/98267 and Long Life Rate based on QT 99422/98267/96512 and

8 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 8 of 12 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp ReJ Failure Mechanism STRESS: ESD-CHARGE DEVICE MODEL CY7C960A-UM USA-V COM 3 0 STRESS: LONG LIFE VERIFICATION 150C, 5.75V (MILITARY) CY7C960A-UM USA-V

9 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 9 of 12 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp ReJ Failure Mechanism STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (125C, 5.75V, Vcc Max) CY7C960A-ASC /5/6 ASAT-B CY7C960A-ASC /5/6 ASAT-B STRESS: ESD-CHARGE DEVICE MODEL (1,000V) CY7C960A-ASC /5/6 ASAT-B COM 3 0 STRESS: ESD-HUMAN BODY CIRCUIT ER MIL STD 883, METHOD 3015 (3,300V) CY7C960A-ASC /5/6 ASAT-B COM 3 0 STRESS: STATIC LATCH-U TESTING (125C, 8.5V, +/-300mA) ) CY7C960A-ASC /5/6 ASAT-B COM 3 0

10 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 10 of 12 RELIABILITY TEST DATA QT#: / DEVICE ASSY-LOC FABLOT# ASSYLOT# DURATION S/S REJ FAIL MODE ==================== ======== ======== ============== ======== ==== === ================================ STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (125C, 5,75V) CY7C960-NC ASAT-B /1/ CY7C960-NC ASAT-B /1/ STRESS: ESD-CHARGE DEVICE MODEL (1000V) CY7C960-NC ASAT-B /1/2 COM 3 0 CY7C960-UMB USA-V COM STRESS: ESD-HUMAN BODY CIRCUIT ER MIL STD 883, METHOD 3015 (4400V) CY7C960-NC ASAT-B /1/2 COM STRESS: GROU C, SUBGROU 1, LIFE TEST (150C, 5.75V) CY7C960-UMB USA-V STRESS: HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE (150C, 5.75V) CY7C960-UMB USA-V CY7C960-UMB USA-V STRESS: RESSURE COOKER TEST (121C, 100%RH) CY7C960-NC ASAT-B /1/ STRESS: TC COND. C, -65 TO 150C, HERMETIC DEVICES CY7C960-UMB USA-V CY7C960-UMB USA-V

11 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 11 of 12 RELIABILITY TEST DATA QT#: / EVAL # DEVICE ASSY-LOC ASSYLOT# FABLOT# OINT S/S REJ Fail Mode ====== ============== ======== ============== ======== ===== === === ============================== STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (150C, 5.75V) CY7C960-UMB USA-V CY7C960-UMB USA-V CY7C960-UMB USA-V STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (125C, 5,75V) CY7C961-NC HK-B CY7C961-NC HK-B STRESS: ESD-CHARGE DEVICE MODEL CY7C961-NC HK-B V CY7C961-NC HK-B V CY7C960-UMB USA-V V 3 0 STRESS: ESD-HUMAN BODY CIRCUIT ER MIL STD 883, METHOD CY7C961-NC HK-B V CY7C961-NC HK-B V CY7C961-NC HK-B V 3 0 STRESS: GROU C, SUBGROU 1, LIFE TEST (150C, 5.75V) CY7C960-UMB USA-V STRESS: HI-ACCEL SATURATION TEST (130C, 5.5V), RECOND. 192 HRS 30C/60%RH CY7C961-NC HK-B STRESS: HI-ACCEL SATURATION TEST (130C, 5.5V), RECOND. 24 HRS 85C/60%RH CY7C961-NC HK-B STRESS: HIGH TEM STEADY STATE LIFE TEST (125C, 5.75V) CY7C960-NC HK-B CY7C961-NC HK-B CY7C960/961, L27 ROCESS, FAB3, LASTIC ACKAGE QUAL 2 CY7C960/961, L27 ROCESS, FAB3, HERMETIC ACKAGE QUAL

12 Cypress Semiconductor, Inc. QT# 99422, V. 1.0 VMEBus Interface Controller, L28ED Technology, Fab 2 age 12 of 12 RELIABILITY TEST DATA QT#: 96104/96512 EVAL # DEVICE ASSY-LOC ASSYLOT# FABLOT# OINT S/S REJ Fail Mode ====== ============== ======== ============== ======== ===== === === ============================== STRESS: HIGH TEM DYNAMIC OERATING LIFE-EARLY FAILURE RATE (150C, 5.50V) CY7C961-NC HK-B CY7C961-NC HK-B CY7C960-UMB USA-V STRESS: HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE (125C, 5,75V) CY7C961-NC HK-B CY7C961-NC HK-B STRESS: READ & RECORD LIFE TEST (125C, 5.75V) CY7C961-NC HK-B CY7C961-NC HK-B CY7C961-NC HK-B STRESS: TC COND. C, -65 TO 150C, HERMETIC DEVICES CY7C960-UMB USA-V CY7C960-UMB USA-V STRESS: TC JEDEC22 COND. B, -40 TO 125C, RECOND. 24 HRS 85C/60%RH CY7C961-NC HK-B CY7C961-NC HK-B CY7C961-NC HK-B CY7C961-NC HK-B