Commercial Qualification Plan/Results Summary

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Aldous Wood
6 years ago
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1 Objective: New Package Qualification for ER48 in a 40 pin Plastic Land Grid Array Freescale PN: SC9S08ER48 Customer Name(s): Insulet Part Name: "ER48, Eros-ASIC" PN(s): Commercial Qualification Plan/ Summary Plan or : Revision # & Date: Tech Code - E025FXXQ (0.25um LVLP) Technology: Package Code - 008V Package: (40 PLGA 6 X 6 X 0.96 P 0.5) Design Engr: Jim Carlquist QUARTZ Tracking #: Fab / Assembly / Final Test Sites: FSL-ATMC-FAB/ FSL-TJN-FM / FSL-TJN-FM Product Engr: Russ Walin Maskset#: N80A Rev#: 1 Prod. Package Engr: Matt Zapico PPE Approval (for DIM/BOM results) Signature & Date: Die Size (in mm) W x L x T 3.532x3.565 mm 2 NPI PRQE: Tammie Gause NPI PRQE Approval Signature & Date: Generic Data: YZME005UAW0 0 CTEZD1114A Generic Data: YZME005UAY00 CTEZT1114B Generic Data: YZME005UB000 CTEZD1114D Part Operating Temp. Grade: Target Dates Test Start: Test Finish: Customer Specific 05/13/11 05/14/11-29C to 60C static operation (STOP1 mode) 5C to 45C active operation (RUN mode) Test Program Name: ER48_B2 Trace/DateCode: ER48 Qual Lot: DD ER48 Qual Lot: DD Test Program Revision: ER48_B2 ER48 Qual Lot: CAB Approval Signature & Date: Customer Approval Signature & Date: TESTS HIGHLIGHTED IN YELLOW WILL BE PERFORMED FOR THIS STUDY PC PC HAST A113 J-STD-020 A113 J-STD-020 A101 A110 Preconditioning (PC) : PC required for SMDs only. MSL 260 C, +5/-0 C Preconditioning (PC) : PC required for SMDs only. MSL 260 C, +5/-0 C CSAM before and after Highly Accelerated Stress Test (HAST): PC before HAST (for SMDs only): Required HAST = 130 C/85%RH for 48 hrs ((for Commercial Qual Readpt) and 96hrs (for Industrial Qual Readpt) Bias = 3.6V (Vdd max, Maximize voltage within operating range.) Timed RO of 48hrs. MAX This testing is performed by Freescale Reliability Lab (FSL-ATX-FAB) unless otherwise noted in the. GROUP A - ACCELERATED ENVIRONMENTAL STRESS TESTS RH(C) All surface mount devices prior to HAST, AC, and TC, and as required YZME005UAW00-0/160 per test conditions. YZME005UAY00-0/160 YZME005UB000 (Unimicron) - 0/160 CSAM CSAM SS=11 units per qualification lot YZME005UAW00-0/11 YZME005UAY00-0/11 YZME005UB000 (Unimicron) - 0/11 RH hrs, 96hrs 48hrs. 96hrs YZME005UB000 (Unimicron) - 48hrs, 96hrs YZME005UB000 (Unimicron) - 48hrs, 504hrs THB Stress NVM should be in recommended state during stress AC A102 A118 Autoclave (AC): PC before AC (for SMDs only): Required AC = 121 C/100%RH/15 psig for 48 hrs (for Commercial Qual Readpt) and 96hrs (for Industrial Qual Readpt) Timed RO of 48hrs. MAX R N/A UHST A102 A118 Unbiased HAST (UHST): PC before UHST (for SMDs only): Required UHST = 130 C/85%RH for 96 hrs(qp), 192hrs(FIO) Timed RO of 48hrs. MAX RH Pass (Note 1)

2 A104 AEC Q100- Appendix 3 Temperature Cycle (TC): PC before TC (for SMDs only): Required TC = -65 C to 150 C for 200 cycles (Commercial Tier Rdpt) and 500 cycles (Industrial Tierr), 1000cycles (FIO) H(C) , 500 & 1000 cycles 200, 500 & 1000 cycles YZME005UB000 (Unimicron) - 200, 500 & 1000 cycles TC NVM should be in recommended state during stress PC + PTC A105 Preconditioning plus Power Temperature Cycle (PC+PTC): (See AEC-Q100 for test applicability criteria) PC before PC+PTC (for SMDs only) PC= C, +5/-0 C PTC =? C to? C for 1000 cycles; Bias =? RH 22+3 SMD only 0 0 N/A PTC HTSL A105 A103 Power Temperature Cycle (PTC): (See AEC-Q100 for test applicability.) PTC =? C to? C for 1000 cycles; Bias =? High Temperature Storage Life (HTSL): 150 C for 168hrs and 504hrs (for Commercial Qual Readpt) and 1008 hrs (for Industrial) Timed RO = 96hrs. MAX RH 23+3 SMDs; 45+3 non- SMD 0 0 N/A RH(C) hrs and 1008hrs HTOL A108 High Temperature Operating Life (HTOL): Ta = 125 C for 168hrs (5yr Commercial Rd Pt) Bias = 3.8V (Devices incorporating NVM shall receive NVM endurance preconditioning (EDR) prior to this test 85 o C for 10k Cycles), and special NVM test sequencing after this test; see AEC-Q100 for details) Timed RO of 96hrs. MAX TEST GROUP B - ACCELERATED LIFETIME SIMULATION TESTS RHC Pass HTOL A108 High Temperature Operating Life (HTOL): Ta = 125 C for 180hrs (Commercial Tier Rdpt) Bias = 2.8V (Devices incorporating NVM shall receive NVM endurance preconditioning (EDR) prior to this test 85 o C for 10k Cycles), and special NVM test sequencing after this test; see AEC-Q100 for details) Timed RO of 96hrs. MAX RHC Pass HTOL A108 High Temperature Operating Life (HTOL): Ta = 125 C for 180hrs (Commercial Tier Rdpt) Bias = 2.8V (Devices incorporating NVM shall receive NVM endurance preconditioning (EDR) prior to this test 85 o C for 10k Cycles), and special NVM test sequencing after this test; see AEC-Q100 for details) Timed RO of 96hrs. MAX RHC Pass

3 ELFR AEC Q Early Life Failure Rate ELFR): Ta = 125 C for 48 hrs Bias = 3.8V Timed RO of 48 hrs MAX (Devices incorporating NVM shall receive NVM endurance preconditioning (EDR) prior to this test 85 o C for 1k Cycles), and special NVM test sequencing after this test; see AEC-Q100 for details) RH(C) Pass ELFR AEC Q Early Life Failure Rate ELFR): Ta = 125 C for 48 hrs Bias = 2.8V Timed RO of 48 hrs MAX (Devices incorporating NVM shall receive NVM endurance preconditioning (EDR) prior to this test 85 o C for 1k Cycles), and special NVM test sequencing after this test; see AEC-Q100 for details) RH(C) Pass EDR AEC Q NVM Endurance, Data Retention, and Operational Life (EDR): (also known as NVM Endurance Preconditioning) 10K W/E 85 o C, Vdd = 3.3V for Flash (nominal) and 150 o C for 168hrs (Commercial Tier Rdpt) Timed RO of 48hrs. MAX RHC Pass EDR AEC Q NVM Endurance, Data Retention, and Operational Life RHC Pass (EDR): (also known as NVM Endurance Preconditioning) 10K W/E -40 o C, Vdd = 3.3V for Flash (nominal) and 150 o C for 168hrs (Commercial Tier Rdpt) Timed RO of 48hrs. MAX EDR AEC Q NVM Endurance, Data Retention, and Operational Life RHC Pass (EDR): (also known as NVM Endurance Preconditioning) 10K W/E -40 o C, Vdd = 1.8V for Flash (nominal) and 150 o C for 168hrs (Commercial Tier Rdpt) Timed RO of 48hrs. MAX WBS AEC Q Wire Bond shear (WBS) Cpk = or > bonds from minimum 5 units TEST GROUP C - PACKAGE ASSEMBLY INTEGRITY TESTS 2 10 Completed on all three lots, All Cpk's > 1.67 WBP MilStd Wire Bond Pull (WBP): Cond. C or D Cpk = or > bonds from minimum 5 units 2 10 Completed on all three lots, All Cpk's > 1.67

4 SD B102 Solderability (SD): 8hr.(1 hr. for Au-plated leads) Steam age prior to test. If production burn-in is done, samples must also undergo burn-in prior to SD. >95% lead coverage of critical areas Completed and passed PD B100 Physical Dimensions(PD): PD per FSL 98A drawing Cpk = or > Completed on all three lots, All Cpk's > 1.67 DIM & BOM Dimensional (DIM): PPE to verify PD results against valid 98A drawing. BOM Verification (BOM): PPE to verify qual lot ERF BOM is accurate. DIM: Completed BOM: Completed SBS AEC-Q Solder Ball Shear (SBS): Performed on all solder ball mounted packages e.g. PBGA, Chip Scale, Micro Lead Frame (but NOT Flip Chip). Two 220 C reflow cycles before shear. Cpk = or > (5 balls from a min. of 10 devices) 0 0 Not Required LI B105 Lead Integrity (LI): Not required for surface mount devices; Only required for through-hole devices. No lead breakage or cracks 5 (10 leads from each of 5 parts) 0 0 Not Required TEST GROUP D - DIE FABRICATION RELIABILITY TESTS Electro Migration (EM) Report avail upon request EM Time Dependent Dielectric Breakdown (TDDB) Report avail upon request TDDB Hot Carrier Injection (HCI) Report avail upon request HCI TEST Freescale 48A Pre- and Post Functional / Parametrics (TEST): For AEC, test software shall meet requirements of AEC- Q Testing performed to the limits of device specification in temperature and limit value. TEST GROUP E - ELECTRICAL VERIFICATION TESTS 0 Fails All All All Completed AEC-Q / JESD22 ElectroStatic Discharge/ Human Body Model Classification (HBM): RH 2KV min. 3 units per Voltage level 0 0 Pass HBM 500/1000/1500/2000Volts For AEC, see AEC-Q for classification levels. MM AEC-Q or JESD22 ElectroStatic Discharge/ Machine Model Classification (MM): 50/100/200 For AEC, see AEC-Q for classification levels. RH 200V min. 3 units per Voltage level 0 0 N/A CDM AEC-Q or JESD22 ElectroStatic Discharge/ Charged Device Model Classification (CDM): 250/500/750 FIO/1000 Volts FIO For AEC, see AEC-Q for classification levels. Timed RO of 96hrs MAX. RH All pins =/> 500V For AEC, Corner pins =/> 750V; RF pins =/>250V 3 units per Voltage level 1 12 YZME005UAW00-0/12 250V 500V 750V 1000V LU JESD78 plus AEC-Q for AEC Latch-up (LU): Test per JEDEC JESD78 with the AEC-Q requirements for AEC. Ta= Maximum operating temperature,45 o C Vsupply = Maximum operating voltage, 3.6V RH Pass

5 LU ED JESD78 plus AEC-Q for AEC AEC-Q , Freescale 48A spec Latch-up (LU): Test per JEDEC JESD78 with the AEC-Q requirements for AEC. Ta= Maximum operating temperature,60 o C Vsupply = Maximum operating voltage, 3.6V Electrical Distribution (ED) RH Pass RHC For AEC, Cpk = or > FG For AEC, AEC- Q Fault Grading (FG) FG shall be = or > 90% for qual units Digital Stuck At Coverage % w/o Iddq CHAR For AEC, AEC- Q003 Characterization (CHAR): Performed on new technologies and part families per AEC Q003. Required?:? GL For AEC, AEC- Q Electro-Thermally Induced Gate Leakage (GL): 155 C, 2.0 min, +400/-400 V Timed RO of 96 hrs MAX. For all failures, perform unbiased bake (4hrs/125 C, or 2hrs/150 C) and retest; recovered units are GL failures. R N/A EMC IEC Radiated Emission Measurement Electromagnetic Compatibility (EMC) Test per IEC Ta= Room Temp Vsupply = Typical operating voltage <40dBuV 150KHz - 1GHz Running "Typical, Worst-case Application Code" per "Pioneer2 EMC Software Specification_rev1 0" Completed, report stored at: / / / /MC9S08ER48_1N80A_40LGA_Radiated_RF_Emissio ns_test_report.pdf?nodeid= &vernum=-2 EMC Langer IC EFT - P201/P301 probes Electromagnetic Compatibility (EMC) Test per Langer IC EFT Test Specification - ger_ic_test_specification_00_01.doc?func=doc.fetch&n odeid= &readonly=true&vernum=- 2&nexturl=%2Flivelink%2Flivelink%3Ffunc%3Dll%26objId %3D %26objAction%3Dbrowse%26viewType% 3D1 Ta= Room Temp Vsupply = Typical operating voltage Not Required EMC Direct Electromagnetic Compatibility (EMC) contact/indirect Test per Powered ESD Test Specification - contact Powered ESD wered_esd_testing.ppt?func=doc.fetch&nodeid= &ReadOnly=True&VerNum=- 2&nexturl=%2Flivelink%2Flivelink%3Ffunc%3Dll%26objId %3D %26objAction%3Dbrowse%26viewType% 3D1 Ta= Room Temp Vsupply = Typical operating voltage Yes required, but for internal information only. This was done, with no major issues identified. Revision Date Rev Oct Generated qual results ER48 BOM: FGS ROOT PART ID PACKAGE CD PACK DESCRIPTION DIE PART ID DIE SIZE WAFER TECH CD PACKAGE KIT PACKAGE KIT SITE ER48 008V LGA 40 6 X 6 X 0.96 P 0.5 N80A X E025FXXQ K00165D005 Generic Data List for Die Qual: Quartz # Mask Set Product-Qual Description / Part Number(s) Fab Site Assembly Site Mold Compound Die Attach Die Size M30B ER48 FSL-ATMC-FAB TJN SUMITOMO G760L 2025D 3.532x3.565 mm2

6 Generic Data List of Package Qual Data: FGS ROOT PART ID PACKAGE CD PACK DESCRIPTION DIE PART ID DIE SIZE WAFER TECH CD PACKAGE KIT PACKAGE KIT SITE Havsau 007A 48 7*7*0.98 P0.5 N68B X E018AFXQ K00165D

7 see below (Signature/Date shown below may be electronic) 6 April 2011 ecab# m AEC Requirement. Only recommeded for Comm/Ind as FYI if generic package type has not received AC. Generic Data: See UHST Generic Data: Havasu ( N68B): 0/320 Only 30 units from each lot was tested at hot temperature at Qual read points (QP).

8 PC+PTC (when required) performed on SMD packages only; if package not SMD, perform PTC (when required) using non-smd sample size 10K W/E 1.8V, 85 o C HTOL Ta 125 o C for 168hrs 10K W/E 1.8V, 85 o C HTOL Ta 125 o C for 180hrs 10K W/E 3.3V, 85 o C HTOL Ta 125 o C for 180hrs

9 1K W/E 3.3V, 85 o C ME004YJX00-0/306 ME004ZV600-0/306 ME004WXF00-0/306 ELFR Ta 125 o C for 48hrs ME004YJX00-0/306 ME004ZV600-0/306 ME004WXF00-0/306 1K W/E 3.3V, 85 o C ME004YJX00-0/306 ME004ZV600-0/306 ME004WXF00-0/306 ELFR Ta 125 o C for 48hrs ME004YJX00-0/306 ME004ZV600-0/306 ME004WXF00-0/306 10K 85 o C, Vdd = 3.3V: DRB 150 o C for 168hrs 10K -40 o C, Vdd = 3.3V: DRB 150 o C for 168hrs 10K -40 o C, Vdd = 1.8V: DRB 150 o C for 168hrs Performed by Assembly Site during qual lot builds Performed by Assembly Site during qual lot builds

10 Performed by Assembly Site during qual lot builds Performed by Assembly Site during qual lot builds Performed by Assembly Site during qual lot builds - PE to include this requirement in the qual lot build ERF The data, test method, calculations and internal criteria should be available to the customer upon request for new technologies. The data, test method, calculations and internal criteria should be available to the customer upon request for new technologies. The data, test method, calculations and internal criteria should be available to the customer upon request for new technologies. Temp range: Spec Vdd range = 1.8V to 3.6V (Nominally 3.0V, A. Max = 3.8V) Spec Vregd range = 1.8V to 2.75V (Nominally 2.4V, A. Max = 2.8V) ME004YJX00 500V ME004WXF00-0/6

11 ME004ZV600-0/6 Compare to old package ED Only required for Auto Qual. Author T. Gause LEAD FRAME PART ID 84ENG00373D001 CAB Number/Date M 24Jan 2011

12 LEAD FRAME PART ID

AEC-Q100F Qualification Results Summary

AEC-Q100F Qualification Results Summary AEC-Q100F Qualification Summary Objective: To qualify NPI 9S08DZ60 M74K in a 64 LQFP Package Freescale PN: 9S08DZ60 Customer Name(s): Multiple Part Name: Longhorn PN(s): Technology: 0.25um Embedded Flash