EE247 Lecture 20. EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 1. Project

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1 EE247 Lecture 20 ADC Converters (continued) Comparator design (continued) Latched comparators Comparator architecture examples Techniques to reduce flash ADC complexity Interpolating Folding Interpolating & folding Interleaved ADCs Multi-Step ADCs Two-Step flash Pipelined ADCs Effect of sub-adc, sub-dac, gain stage non-idealities on overall ADC performance EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 1 Project Design & simulate an ADC ENOB=6bit for fsignal<10mhz Signal bandwidth 0 to 100MHz Architecture of your choice targeted for minimum power dissipation Description posted in the homework section Teams of two preferred Report due Dec. 3 rd Powerpoint presentation ~5min/person in class on Dec. 8 th EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 2

2 CMOS Latched Comparators Comparator amplification need not be linear can use a latch regeneration Latch Amplification + positive feedback EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 3 CMOS Latched Comparators Small Signal Model Latch can be modeled as a: Single-pole amp + positive feedback Small signal ac half circuit EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 4

3 V dv gv m = + C R dt L CMOS Latched Comparator Latch Delay gm 1 dv gm 1 dv 1 V 1 dt C gmr = L dt C gmr = L V g 1 t2 V2 1 a m 1 a a Integrating both sides: 1 dt dv dx ln x b ln a ln b ln C g t1 V1 b mr = = = = L V x b Latch Delay: C 1 V2 td = t2 t1 = ln g 1 m 1 V 1 gmr L For g R >> 1 m L t C V 2 D ln g m V 1 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 5 Latch-Only Comparator Much faster compared to cascade of openloop amplifiers Main problem associated with latch-only comparator topology: High input-referred offset voltage (as high as 100mV!) Solution: Use preamplifier to amplify the signal and reduce overall input-referred offset EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 6

4 Pre-Amplifier + Latch Overall Input-Referred Offset V os Preamp V os Latch f s V i+ D o+ A Latch V v i- D o- Preamp Latch offset attenuated by preamp gain when referred to preamp input. Assuming the two offset sources are uncorrelated: 1 σ σ σ 2 2 Input Re ferred _ Offset = Vos _ Pr eamp + 2 Vos _ Latch APr eamp Example : σ = 4 mv & σ = 50 mv & A = 10 σ Vos _Pr eamp Vos _ Latch Preamp 1 = = 6.4mV Input Re ferred _ Offset 2 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 7 Pre-Amplifier Tradeoffs f s V i+ D o+ A Latch V v i- D o- Preamp Example: Latch offset 50 to 100mV Preamp DC gain 10X Preamp input-referred latch offset 5 to 10mV Input-referred preamplifier offset 2 to 10mV Overall input-referred offset 5.5 to 14mV Addition of preamp reduces the latch input-referred offset reduced by ~7 to 9X ~allows extra 3-bit resolution for ADC! EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 8

5 Comparator Preamplifier Gain-Speed Tradeoffs Amplifier maximum Gain-Bandwidth product (f u ) or a given technology, typically a function of maximum device f t fu =unity gain frequency, f0 = 3 db frequency & τ 0 = settling time fu f0 = Apreamp Magnitude For example assuming preamp has a gain of 10: f 1 A u GHz v f0 = = = 100MHz Apreamp 10 f u =0.1-10GHz 1 Apreamp τ 0 = = = 1.6nsec f 0 f 2π f 2π f u freq. 0 u - Tradeoff: To reduce the effect of latch offset high preamp gain desirable Fast comparator low preamp gain Choice of preamp gain: compromise speed v.s. input-referred latch offset EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 9 Latched Comparator f s V i+ A v Latch D o+ V i- D o- Preamp Important features: Maximum clock rate f s settling time, slew rate, small signal bandwidth Resolution gain, offset Overdrive recovery Input capacitance (and linearity of input capacitance!) Power dissipation Input common-mode range and CMR Kickback noise EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 10

6 CMOS Preamplifier + Latch Type Comparator Delay in Response Latch delay previously found: C V2 τ D ln g m V 1 Assuming gain of A for the preamplifier then : V = A V v 1 v in C V0 τ D ln g AV m v in EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 11 Latched Comparator Including Preamplifier Example V DD M5 M3 M4 M6 Preamplifier gain: M3 M3 ( VGS Vth ) ( ) M 1 m v = = M 3 M1 M1 gm VGS Vth A g + - M1 M2 CLK M9 - V o + Comparator delay: (for simplicity, preamp delay ignored) τ C V 0 D ln g m AVin v bias Preamp M7 Latch M8 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 12

7 Comparator Dynamic Behavior Comparator Reset Comparator Decision CLK T CLK v O+ τ delay v OUT v O- EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 13 CLK Comparator Resolution v OUT V IN =10mV 1mV 0.1mV 10μV Note: For small Vin the comparator may not be able to make a decision within the allotted time output ambiguous Δt = (g m /C).ln(1 /2 ) EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 14

8 Comparator Voltage Transfer Function Non-Idealities V out ε V Offset -0.5LSB 0.5LSB V Offset ε Comparator offset voltage Meta-Stable region (output ambiguous) EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 15 CMOS Comparator Example Flash ADC Flash ADC: 8bits, +-1/2LSB fs=15mhz (Vref=3.8V, LSB~15mV) No offset cancellation Ref: A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 1985, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 16

9 Comparator with Auto-Zero Note: Reference & input both differential Ref: I. Mehr and L. Singer, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 17 Flash ADC Comparator with Auto-Zero V offset V V = V V V C+ C ( + ) Re f Re f Offset Ref: I. Mehr and D. Dalton, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 18

10 Flash ADC Comparator with Auto-Zero V offset Vo Vo = AP1 AP2[ ( VIn+ VIn ) ( VC+ VC ) VOffset] Substituting for ( VC+ VC ) from previous cycle: Vo = AP1 AP2 ( VIn+ VIn ) ( VRe f + VRe f ) Note: Offset is cancelled & difference between input & reference established Ref: I. Mehr and D. Dalton, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 19 Flash ADC Using Comparator with Auto-Zero Ref: I. Mehr and D. Dalton, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 1999, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 20

11 Auto-Zero Implementation Ref:I. Mehr and L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC, JSSC March 2000, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 21 Variation on Yukawa latch used w/o preamp Good for low resolution ADCs (in this case 1.5bit/stage for a pipeline we will see later are tolerant of high offset) Comparator Example Note: M1, M2, M11, M12 operate in triode mode x M11 & M12 added to vary comparator threshold Conductance at node X is sum of G M1 & G M11 Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mw pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp , March 1995 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 22

12 Comparator Example (continued) M1, M2, M11, M12 operate in triode mode with all having equal L Conductance of input devices: μc G ox 1= W1( VI1 Vth ) + W11( VR Vth ) L μc G ox 2= W1( VI2 Vth) + W11( VR+ Vth) L μcoxw1 W ( V V ) 11 Δ G = I1 I2 ( VR + VR ) L W1 To 1st order, for W1= W2 & W11=W12 V th latch = W11/W1 x V R where V R = V R+ -V R- V R fixed W11, 12 varied from comparator to comparator Eliminates need for resistive divider V o1 o1 Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mw pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp , March 1995 G1 G2 Vo2 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 23 Used in a pipelined ADC with digital correction No offset cancellation required Differential reference & input M7, M8 operate in triode region Preamp gain ~10 Input buffers suppress kick-back φ 1 high C s charged to VR & φ 2B is also high current diverted to latch comparator output in hold mode Comparator Example φ 2 high C s connected to S/Hout & comparator input (VR-S/Hout), current sent to preamp comparator in amplify mode Ref: S. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, NO. 6, Dec EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 24

13 Bipolar Comparator Example Used in 8bit 400Ms/s & 6bit 2Gb/s flash ADC Signal amplification during φ1 high, latch operates when φ1 low Input buffers suppress kick-back & input current Separate ground and supply buses for frontend preamp kickback noise reduction Preamp Latched Comparator Ref: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXX, pp , February 1987 Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXXI, pp , February 1988 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 25 Reducing Flash ADC Complexity E.g. 10-bit straight flash Input range: 0 1V LSB = Δ: ~ 1mV Comparators: 1023 with offset < 1/2 LSB Assuming Cin for each comparator is 0.1pF & power 3mW Total input capacitance: 1023 * 100fF = 102pF Power: 1023 * 3mW = 3W High power dissipation & large area & high input cap. Techniques to reduce complexity & power dissipation : Interpolation Folding Folding & Interpolation Two-step, pipelining EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 26

14 Interpolation Idea Reduce number of preamps & instead interpolate between preamp outputs Reduced number of preamps Reduced input capacitance Reduced area, power dissipation Same number of latches (2 B -1) Important side-benefit Decreased sensitivity to preamp offset Improved DNL EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 27 Preamp Output [V] Flash ADC Preamp Output A 2 A 1 Vin Vref2 Vref1 A 2 A 1 Zero crossings (to be detected by latches) at = Vin /Δ Vref1 Vref2 V ref1 = 1 Δ V ref2 = 2 Δ EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 28

15 Simulink Model Vi Vin 1 Vin 2*Delta Vref2 A2 Preamp2 2 Y 1*Delta Vref1 A1 Preamp1 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 29 Differential Preamp Output Preamp Output A 1 +A A 2 -A 2 A 1 -A 1 A 1 -(-A 2 ) Vin / Δ Differential output = V ref1 = 1 Δ V ref2 = 2 Δ Note: Additional crossing of A 1 &-A 2 (A 2 &-A 1 ) A 1 -(-A 2 )=A 1 +A 2 cross zero at: V ref12 = 0.5*(1+2) Δ=1.5Δ EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 30

16 Interpolation in Flash ADC Vin A 2 Half as many reference voltages and preamps Interpolation factor:x2 A 1 Example: For 10bit straight Flash ADC need 2 B =1024 preamps compared 2 B-1 =512 for x2 interpolation Compare A2& -A1 Comparator output is sign of A1+A2 Possible to accomplish higher interpolation factor Interpolation at the output of preamps EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 31 Vin Interpolation in Flash ADC Preamp Output Interpolation A 2 A 1. Z Z Z Z. V o 2 V o 1.5 = (V o 1 +V o 2 )/2 V o 1 Interpolate between two consecutive output via impedance Z Choices of Z: 1. Resistors (Kimura) 2. Capacitors (Kusumoto) 3. Current mode (Roovers) Ref: H. Kimura et al, A 10-b 300-MHz Interpolated-Parallel A/D Converter, JSSC, pp , April 1993 K. Kusumoto et al, "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," JSSC, pp , December R. Roovers et al, "A 175 Ms/s, 6 b, 160 mw, 3.3 V CMOS A/D converter," JSSC, pp , July EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 32

17 Interpolation in Flash ADC Preamp Output Interpolation Vin A 2.. Preamp Output A 2 -A 2 A 1 -A A 1.. With 2 sets of interpolation resistors at each preamp outputs three extra intermediate points 2extra bits EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 33 Higher Order Resistive Interpolation Resistors produce additional levels With 4 resistors per side, the interpolation factor M=8 extra 3bits (M ratio of latches/preamps) Ref: H. Kimura et al, A 10-b 300-MHz Interpolated-Parallel A/D Converter, JSSC April 1993, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 34

18 Preamp Output Interpolation DNL Improvement Preamp offset distributed over M resistively interpolated voltages: Impact on DNL divided by M Latch offset divided by gain of preamp Use large preamp gain Next: Investigate how large preamp gain can be Ref: H. Kimura et al, A 10-b 300-MHz Interpolated-Parallel A/D Converter, JSSC April 1993, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 35 Preamp Input Range Preamp Output A 1 +A Linear region of transfer curve not overlapping A 2 -A 2 A 1 -A 1 A 1 +A Vin / Δ If linear region of preamp transfer curve do not overlap Dead-zone in the interpolated transfer curve! Results in error Linear consecutive preamp input ranges must overlap i.e. input range w/o output saturation> Δ Sets upper bound on preamp gain: Preamp gain <V DD / Δ EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 36

19 Interpolated-Parallel ADC 10-bit overall resolution: 7-bit flash (127 preamps and Vref 128 resistors) & x8 interpolation Use of Gray Encoder minimizes effect of sparkle code & metastability Ref: H. Kimura et al, A 10-b 300-MHz Interpolated-Parallel A/D Converter, JSSC April 1993, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 37 Measured Performance (7+3) Low input capacitance Ref: H. Kimura et al, A 10-b 300-MHz Interpolated-Parallel A/D Converter, JSSC April 1993, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 38

20 Interpolation Summary Consecutive preamp transfer curve linear region need to have overlap Limits gain of preamp to ~V DD /Δ The added impedance at the output of the preamp typically reduces the bandwidth and affects the maximum achievable frequencies DNL due to preamp offset reduces by interpolation factor M Interpolation reduces # of preamps and thus reduces input C- however, the # of required latches the same as straight Flash Use folding to reduce the # of latches EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 39 Folding Converter V IN MSB ADC LSB ADC L O G I C Digital Output Folding Circuit Two ADCs operating in parallel MSB ADC Folder + LSB ADC Significantly fewer comparators compared to flash Fast Typically, nonidealities in folder limit resolution EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 40

21 Example: Folding Factor of 4 Folding factor number of folds MSB bits 11 V out Folder maps input to smaller range MSB ADC determines which fold input is in 10 LSB ADC determines position within fold 01 Logic circuit combines LSB and MSB results 00 To LSB Quantizer V FS /2 V FS EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 41 Example: Folding Factor of 4 V out How are folds generated? 11 Fold 1 V out =+ Fold 2 V out = - + V FS /2 Fold 3 V out =+ -V FS /2 Fold 4 V out = - + V FS Note: Sign change every other fold + reference shift V FS /2 V FS EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 42

22 V DD Generating Folds via Source-Coupled Pairs R1 -Vo+ R2 IS M1 M2 Vref1 M3 M4 Vref2 M5 M6 Vref3 M7 M8 Vref4 IS IS IS IS Vref1 < Vref2 < Vref3 < Vref4 As Vin changes, only one of M1, M3, M5, M7 is on depending on the input level EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 43 CMOS Folder Output Folder Output Error (Ideal-Real) ISxR Ideal Folder 0 CMOS Folder -ISxR Vref1 Vref2 Vref3 Vref4 20% 0-20% /Δ CMOS folder transfer curve max. min. portions: Rounded Accurate only at zero-crossings In fact, most folding ADCs do not use the folds, but only the zero-crossings! EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 44

23 Parallel Folders Using Only Zero-Crossings Folder 4 Comparator V ref + 3/4 * Δ Folder 3 Comparator V ref + 2/4 * Δ Folder 2 Comparator Logic LSB bits (to be combined with MSB bits) V ref + 1/4 * Δ Folder 1 Comparator V ref + 0/4 * Δ EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 45 Parallel Folder Outputs Folder Output F1 F2 F3 F Vin /Δ 4 folders with 4 folds each 16 zero crossings 4 LSB bits Higher resolution More folders Large complexity Interpolation EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 46

24 Folding & Interpolation Folder 4 V ref + 3/4 * Δ Folder 3 V ref + 2/4 * Δ Folder 2 V ref + 1/4 * Δ Fine Flash ADC E N C O D E R Folder 1 V ref + 0/4 * Δ EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 47 Folder / Interpolator Output Example:4 Folders + 4 Resistive Interpolator per Stage Folder / Interpolator Output F1 F2 I1 I2 I Vin / Δ Note: Output of two folders only + corresponding interpolator only shown EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 48

25 Folder / Interpolator Output Example:2 Folders + 8 Resistive Interpolator per Stage Folder / Interpolator Output F1 F2 I1 I2 I Vin / Δ Non-linear distortion Interpolate only between closely spaced folds to avoid nonlinear distortion EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 49 A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 50

26 A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter Note: Total of 40 (MSB=8, LSB=32) comparators compared to 2 8-1= 255 for straight flash EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 51 A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 52

27 2-bit ADC Two-Step Example: (2+2)Bits D out = + ε q ADC Input [LSB] Using only one ADC: output contains large quantization error "Missing voltage" or "residue" ( -ε q1 ) 2-bit ADC??? Idea: Use second ADC to quantize and add -ε q1 ε q1 [LSB] D out EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 53 Two Stage Example Vref1 Coarse 2-bit ADC + 2-bit DAC - -ε q1 +ε q2 D out = + ε q1 + Vref2 -ε q1 Fine 2-bit ADC -ε q1 +ε q2 Use DAC to compute missing voltage Add quantized representation of missing voltage Why does this help? How about ε q2? Since maximum voltage at input of the 2 nd ADC is Vref1/4 then for 2 nd ADC Vref2=Vref1/4 and thus ε q2 = ε q1 /4 =Vref1/16 4bit overall resolution EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 54

28 Two Step (2+2) Flash ADC 4-bit Straight Flash ADC Ideal 2-step Flash ADC EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 55 Two Stage Example ε q1 11 V ref1 /2 2 V ref V ref2 Second ADC Fine First ADC Coarse Fine ADC is re-used 2 2 times Fine ADC's full scale range needs to span only 1 LSB of coarse quantizer Vref 2 Vref 1 ε q2 = = EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 56

29 Two-Stage (2+2) ADC Transfer Function D out Coarse Bits (MSB) Fine Bits (LSB) V ref1 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 57 Residue or Multi-Step Type ADC Issues Vin Coarse ADC (B1-Bit) DAC (B1-Bit) Residue Fine ADC (optional) (B2-Bit) Bit Combiner (B1+B2)-Bit Operation: Coarse ADC determines MSBs DAC converts the coarse ADC output to analog- Residue is found by subtracting ( -V DAC ) Fine ADC converts the residue and determines the LSBs Bits are combined in digital domain Issue: 1. Fine ADC has to have precision in the order of overall ADC 1/2LSB 2. Speed penalty Need at least 1 clock cycle per extra series stage to resolve one sample EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 58

30 Solution to Issue (1) Reducing Precision Required for Fine ADC 2-bit ADC Coarse 2-bit DAC - + -ε q1 G=2 B1 2-bit ADC Fine + -ε q1 +ε q2 D out = + ε q1 -ε q1 +ε q2 Accuracy needed for fine ADC relaxed by introducing inter-stage gain Example: By adding gain of x(g=2 B1 =4) prior to fine ADC in (2+2)bit case, precision required for fine ADC is reduced to 2-bit only! Additional advantage- coarse and fine ADC can be identical stages EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 59 Solution to Issue (2) Increasing ADC Throughput 2-bit ADC Coarse 2-bit DAC - + T/H+(G=2 B1 ) -ε q1 Fine T/H 2-bit ADC + D out = + ε q1 - ε q1 +ε q2 Conversion time significantly decreased by employing T/H between stages All stages busy at all times operation concurrent During one clock cycle coarse & fine ADCs operate concurrently: First stage samples/converts/generates residue of input signal sample # n While 2 nd samples/converts residue associated with sample # n-1 EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 60

31 Pipelined A/D Converters Ideal operation Errors and correction Redundancy Digital calibration Implementation Practical circuits Stage scaling EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 61 Pipeline ADC Block Diagram Stage 1 B 1 Bits V res1 Stage 2 B 2 Bits V res2 Stage k B k Bits MSB......LSB Align and Combine Data Digital output (B 1 + B B k ) Bits Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!) Each stage performs coarse A/D conversion and computes its quantization error, or "residue All stages operate concurrently EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 62

32 Pipeline ADC Characteristics Number of components (stages) grows linearly with resolution Pipelining Trading latency for conversion speed Latency may be an issue in e.g. control systems Throughput limited by speed of one stage Fast Versatile: bits, MS/s One important feature of pipeline ADC: many analog circuit non-idealities can be corrected digitally EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 63 Pipeline ADC Concurrent Stage Operation φ 1 φ 2 acquire convert Stage 1 B 1 Bits convert acquire Stage 2 B 2 Bits Stage k B k Bits CLK φ 1 φ 2 Align and Combine Data Digital output (B 1 + B B k )Bits Stages operate on the input signal like a shift register New output data every clock cycle, but each stage introduces at least ½ clock cycle latency EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 64

33 Pipeline ADC Latency Note: One conversion per clock cycle & 8 clock cycle latency [Analog Devices, AD 9226 Data Sheet] EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 65 Pipeline ADC Digital Data Alignment φ 1 φ 2 acquire convert convert acquire Stage 1 B 1 Bits Stage 2 B 2 Bits Stage k B k Bits CLK φ 1 φ D out CLK CLK CLK Digital shift register aligns sub-conversion results in time EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 66

34 Cascading More Stages V ref Vref /2 B1 V ref /2 (B1+B2) V ref /2 (B1+B2+B3) B 1 bits B 2 bits B 3 bits ADC ADC DAC + - LSB of last stage becomes very small All stages need to have full precision Impractical to generate several V ref EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 67 Pipeline ADC Inter-Stage Gain Elements V ref V ref V ref V ref B 1 bits 2 B1 B 2 bits 2 B2 2 B3 B 3 bits ADC ADC DAC + - Practical pipelines by adding inter-stage gain use single V ref Precision requirements decrease down the pipe Advantageous for noise, matching (later), power dissipation EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 68

35 Complete Pipeline Stage + - ε q1 -G Vres B-bit ADC D Residue Plot E.g.: B=2 G=2 2 =4 B-bit DAC V ref V res 0 Note: Non of the blocks have ideal performance 0 Question: What is the effect of the non-idealities? Vref EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 69 Pipeline ADC Errors Non-idealities associated with sub-adcs, sub-dacs and gain stages error in overall pipeline ADC performance Need to find means to tolerate/correct errors Important sources of error Sub-ADC errors- comparator offset Gain stage offset Gain stage gain error Sub-DAC error EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 70

36 Pipeline ADC Single Stage Model Σ ε q Σ -G V res ε q Dout V res = Gxε q EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 71 Pipeline ADC Multi-Stage Model,ADC D1 D D Σ - V res1 Σ - V res2 Σ - V res(n-1) Σ ε q1 G 1 Σ ε q2 G 2 Σ ε q(n-1) G n-1 Σ 2 (n-1) D n ε qn Σ Σ D out 1/G d1 1/G d2 Σ 1/G d(n-1) G ε G D V q2 2 out = in,adc + εq1 + + G d1 G d1 G d2 ε G G G ε q(n 1) (n 1) qn n 2 n 1 dj d(n 1) j= 1 j= 1 G dj EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 72

37 Pipeline ADC Model If the "Analog" and "Digital" gain/loss is precisely matched: εqn Dout = Vin, ADC + n 1 G j j= 1 rms FS Signal D. R. = 20log = 20log rms Quant. Noise V 2 2 V 12 2 ref ref n 1 Bn j= 1 G j = 20 log Bn n 1 j= 1 G j B ADC Bn log 2 2 n 1 j= 1 G j B ADC B + log n n 1 2 j= 1 G j EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 73 Pipeline ADC Observations The aggregate ADC resolution is independent of sub-adc resolution! Effective stage resolution B j =log 2 (G j ) Overall conversion error does not (directly) depend on sub-adc errors! Only error term in D out contains quantization error associated with the last stage So why do we care about sub-adc errors? Go back to two stage example EECS 247 Lecture 20: Data Converters: Nyquist Rate ADCs 2009 Page 74