ECE332, Week 2, Lecture 3. September 5, 2007

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1 ECE332, Week 2, Lecture 3 September 5,

2 Topics Introduction to embedded system Design metrics Definitions of general-purpose, single-purpose, and application-specific processors Introduction to Nios II processor Programming model Instruction set categories Instruction decoding 2

3 References Chapter 1 (Introduction) of Embedded System Design Chapter 2 (Processor Architecture) of Nios II Processor Reference Handbook Chapter 3 (Programming Model) of Nios II Processor Reference Handbook Chapter 8 (Instruction Set Reference) of Nios II Processor Reference Handbook 3

4 Embedded systems overview Computing systems are everywhere Most of us think of desktop computers PC s laptops mainframes servers But there s another type of computing system far more common... 4

5 Embedded systems overview Embedded computing systems Computing systems embedded within electronic devices Hard to define - Nearly any computing system other than a desktop computer Billions of units produced yearly, versus millions of desktop units Perhaps 50 per household and per automobile Computers are in here... and here... and even here... Lots more of these, though they cost a lot less each. 5

6 Some common characteristics of embedded systems Single-functioned Executes a single program, repeatedly Tightly-constrained Low cost, low power, small, fast, etc. Reactive and real-time Continually reacts to changes in the system s environment Must compute certain results in real-time without delay Hard versus soft 6

7 Design challenge optimizing design metrics Obvious design goal: Construct an implementation with desired functionality Key design challenge: Simultaneously optimize numerous design metrics Design metric A measurable feature of a system s implementation Optimizing design metrics is a key challenge 7

8 Design challenge optimizing design metrics Common metrics Unit cost the monetary cost of manufacturing each copy of the system, excluding NRE cost NRE cost (Non-Recurring Engineering cost) The one-time monetary cost of designing the system Size the physical space required by the system Performance the execution time or throughput of the system Power the amount of power consumed by the system 8

9 Design challenge optimizing design metrics Common metrics (continued) Flexibility the ability to change the functionality of the system without incurring heavy NRE cost Time-to-prototype the time needed to build a working version of the system Time-to-market the time required to develop a system to the point that it can be released and sold to customers Maintainability the ability to modify the system after its initial release Correctness, safety, many more 9

10 Design metric competition -- improving one may worsen others Performance Power NRE cost Size Expertise with both software and hardware is needed to optimize design metrics Not just a hardware or software expert, as is common A designer must be comfortable with various technologies in order to choose the best for a given application and constraints Hardware/software codesign 10

11 NRE and unit cost metrics Costs: Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system total cost = NRE cost + unit cost * # of units per-product cost = total cost / # of units = (NRE cost / # of units) + unit cost Example NRE=$2000, unit=$100 For 10 units total cost = $ *$100 = $3000 per-product cost = $2000/10 + $100 = $300 Amortizing NRE cost over the units results in an additional $200 per unit 11

12 The performance design metric Widely-used measure of system, widely-abused Clock frequency, instructions per second not good measures Digital camera example a user cares about how fast it processes images, not clock speed or instructions per second Latency (response time) Time between task start and end e.g., Camera s A and B process images in 0.25 seconds Throughput Tasks per second, e.g. Camera A processes 4 images per second Throughput can be more than latency seems to imply due to concurrency, e.g. Camera B may process 8 images per second (by capturing a new image while previous image is being stored). 12

13 Processor technology The architecture of the computation engine used to implement a system s desired functionality Processor does not have to be programmable Processor not equal to general-purpose processor Controller Datapath Controller Datapath Controller Datapath Control logic and State register IR PC Register file General ALU Control logic and State register IR PC Registers Custom ALU Control logic State register index total + Data memory Data memory Program memory Assembly code for: Data memory Program memory Assembly code for: total = 0 for i =1 to General-purpose ( software ) total = 0 for i =1 to Application-specific Single-purpose ( hardware ) 13

14 General-purpose processors Programmable device used in a variety of applications Controller Datapath Also known as microprocessor Features Program memory General datapath with large register file and general ALU Control logic and State register IR PC Register file General ALU User benefits Low time-to-market and NRE costs High flexibility Program memory Assembly code for: Data memory Pentium the most well-known, but there are hundreds of others total = 0 for i =1 to 14

15 Single-purpose processors Digital circuit designed to execute exactly one program a.k.a. coprocessor, accelerator or peripheral Features Contains only the components needed to execute a single program No program memory Benefits Fast Low power Small size Controller Control logic State register Datapath index total + Data memory 15

16 Application-specific processors Programmable processor optimized for a particular class of applications having common characteristics Compromise between general-purpose and single-purpose processors Features Program memory Optimized datapath Special functional units Benefits Some flexibility, good performance, size and power Controller Control logic and State register IR PC Program memory Assembly code for: total = 0 for i =1 to Datapath Registers Custom ALU Data memory 16

17 Nios II Pipelined RISC Architecture 32-bit Instructions Flat Register File 32-bit Data Path 32 Prioritized Interrupts Optional Instruction & Data Cache Custom Instructions Branch Prediction 17

18 Standard Design Block Diagram Ethernet MAC/PHY 1MB SRAM 8MB FLASH 16MB Compact FLASH 32MB SDRAM 32-Bit Nios II Processor IRQ IRQ #(6) Address (32) Read Write Data In (32) Data Out (32) Avalon Switch Fabric Tri-State Bridge ROM (with Monitor) LED PIO Tri-State Bridge General Purpose Timer LCD PIO Compact Flash PIOs Periodic Timer 7-Segment LED PIO SDRAM Controller UART Reconfig PIO Button PIO Level Shifter On-Chip Off-Chip 8 LEDs Expansion Header J12 2 Digit Display 4 Momentary buttons 18

19 Nios II Processor Core 19

20 Nios II Versions Nios II Processor Comes In three ISA Compatible Versions FAST: Optimized for Speed STANDARD: Balanced for Speed and Size ECONOMY: Optimized for Size Software Code is Binary Compatible No Changes Required When CPU is Changed 20

21 Binary Compatibility / Flexible Performance Nios II /f Fast Nios II /s Standard Nios II /e Economy Pipeline 6 Stage 5 Stage None H/W Multiplier & Barrel Shifter 1 Cycle 3 Cycle Emulated In Software Branch Prediction Dynamic Static None Instruction Cache Configurable Configurable None Data Cache Configurable None None Custom Instructions Up to

22 SOPC Builder Flow Processor Library SOPC Builder GUI Configure Processor Custom Instructions Peripheral Library Hardware Development HDL Source Files Select & Configure Peripherals, IP Connect Blocks IP Modules Software Development Nios II IDE C Header files Testbench Generate Custom Library Peripheral Drivers Synthesis & Fitter Hardware Configuration File Verification & Debug Executable Code Compiler, Linker, Debugger User Design JTAG, Serial, or Ethernet User Code Other IP Blocks Quartus II Altera PLD On-Chip Debug Software Trace Hard Breakpoints SignalTap II Libraries RTOS GNU Tools 22

23 Nios II General Purpose Registers 23

24 Control Registers and Bits 24

25 Instruction Set Categories Data transfer instructions Arithmetic and logical instructions Move instructions Comparison instructions Shift and rotate instructions Program control instructions Other control instructions Custom instructions No-operation instructions Potential unimplemented instructions 25

26 Wide Data Transfer Instructions See ldw and ldwio at page 8-64 of Nios II Processor Reference Handbook See page 8-8 for conventions See Table 3-5 for narrow data transfer instructions 26

27 Arithmetic and Logical Instructions 27

28 Move Instructions 28

29 Comparison Instructions 29

30 Shift and Rotate Instructions 30

31 Program Control Instructions 31

32 Program Control Instructions 32

33 Program Control Instructions 33

34 Nios II Instruction Word Format I-type R-type J-type 34

35 Nios II Instruction Word Format Decode add r3,r4,r5 and and r6,r7,r8 35

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