Computer Architecture, RISC vs. CISC, and MIPS Processor

Transcription

1 CSE 2421: Systems I Low-Level Programming and Computer Organization Computer Architecture, RISC vs. CISC, and MIPS Processor Gojko Babić Computer Architecture A modern meaning of the term computer architecture covers three aspects of computer design: instruction set architecture, computer organization and computer hardware. Instruction set architecture - ISA refers to the (low level) programmer visible machine interface such as instruction set, data representations, addressing, registers, memory organization and exception/interrupt handling. One can think of a ISA as a hardware functionality of a given computer. A computer organization and computer hardware are two components of the implementation of a machine. 2 1

2 Typical Computer System Organization Processor chip System bus Memory bus I/O bridge Main memory USB controller Graphics adapter I/O bus Disk controller Expansion slots for other devices such as network adapters. Mouse Keyboard Monitor Disk 3 Main Memory (RAM) Read At the beginning of an instruction execution, CPU places an address (say ) from the program counter on the memory bus. reads address from the memory bus, retrieves instruction XX from address, and places it on the bus. XX XX XX 4 2

3 The processor reads instruction XX from the bus and copies it in the instruction register, and then continue its execution. Main Memory (RAM) Read (cont.) XX is accessed in the similar way by an instruction that reads from memory during its execution, with the following difference: the address is calculated by the processor using parameters in the instruction, a content from memory is loaded in one of registers. 5 Main Memory (RAM) Write Memory write happens during execution of an instruction that store some result into some memory location. The processor calculates address from parameters in the instruction and places address on bus. reads it and waits for the corresponding data to arrive. 6 3

4 CPU places data, from the register specified by the instruction, on the bus. Main Memory (RAM) Write (cont.) Memory reads data from bus and stores it at address. 7 Approaches to Instruction Set Architecture For many years the interaction between ISA and implementations was believed to be small, and implementation issues were not a major focus in designing instruction set architecture. In the 198 s, it becomes clear that both the difficulty of designing processors and performance inefficiency of processors could be increased by instruction set architecture complications. Two main approaches of ISA: CISC(Complex Instruction Set Computer) architecture. RISC(Reduced Instruction Set Computer) architecture And since mid 9 s all new processors are of RISC architecture. 8 4

5 CISC Instruction Set Architecture CISC Complex (and Powerful) Instruction Set Computer CISC goals, such as simple compilers and high code density, led to the powerful instructions, powerful addressing modes and efficient instruction encoding. VAX processor was a good example of CISC architecture. For example: accounting for all addressing modes and limiting to byte, word (16 bits) and long (32 bits), there are more than 3, versions of integer add in VAX. Question: What is today the main example of CISC architecture processor? Answer: Intel x86 and x86-64 processors (found in over 9% desktop computers) But note: All processors in smart phones and tablets are of RISC architecture. 9 CISC Instruction Set Architecture (cont.) Complex Instruction Set Computer: dominant style through mid-8 s. Philosophy: include instructions to perform typical programming tasks. Stack-oriented instruction set: use stack to pass arguments and save program counter, explicit push and pop instructions. Arithmetic instructions may access memory, e.g. the instruction addq %rax, 12(%rbx,%rcx,4) adds two 64-bit integers, one as a content of register %rax and another as a content of memory location (complex address calculation) and store result in the same memory location (requires memory read & write). Condition codes set as a side effect of arithmetic and logical instructions. Presentation J 1 5

6 RISC Instruction Set Architecture Reduced Instruction Set Computer: internal project at IBM, later popularized by Hennessy (Stanford) and Patterson (Berkeley) Fewer & simpler instructions, fewer addressing modes: thus it might take more instructions to get given task done, but can execute them with small and fast hardware. Register-oriented instruction set: many more (typically 32) registers, use for arguments, return pointer, temporaries. Only few load and store instructions can access memory. All instructions one size (usually 32 bits) and few instruction formats. No condition codes, slt instructions return or 1 in a register Presentation J 11 RISC ISA Characteristics: Summary All instructions on data apply to data in registers and typically change the entire register; The only instructions that affect memory are load and store instructions that move data from memory to a register or to memory from a register, respectively; A small number of memory addressing modes; The instruction formats are few in number with all instructions typically being one size; Large number of registers; These simple properties lead to dramatic simplifications in the implementation of advanced hardware design techniques, which is why RISC instruction set architectures were designed this way. 12 6

7 CISC vs. RISC Original debate in late 198 s: strong opinions! CISC proponents easy for compiler, fewer code bytes, RISC proponents better for optimizing compilers, can make run fast with simple chip design. Choice of ISA is not a technical issue for desktop processors today: with enough hardware, can make anything run fast, code compatibility may be more important. For embedded processors, RISC makes sense: smaller, cheaper, less power, Most cell phones and tablets use RISC ARM processor. Presentation J 13 MIPS Processor Memory Main Processor Coprocessor 1 (FPU) Registers $ Registers $ $31 $31 Control Arithm e tic Logic unit M u ltip ly divide Program Counter Lo Hi A rith m e tic unit Coprocessor (traps and memory) Registers BadVAddr Status Cause EPC 14 7

8 MIPS Registers Main Processor (integer manipulations): bit general purpose registers GPRs (r r31); r has fixed value of zero. Attempt to writing into r is not illegal, but its value will not change; two 32-bit registers Hi & Lo, hold results of integer multiply and divide 32-bit program counter PC; Floating Point Processor FPU (Coprocessor 1 CP1; real number manipulations): bit floating point registers FPRs (f f31); five control registers; Coprocessor registers 15 MIPS Instruction Layout 32-bit fixed format instruction and 3 formats; /ft /offset /ft /fs /fd and fd fs funct ft jump_target See link MIPS instructions. 16 8