Multi-Constraint Multi-Processor Resource Allocation

Transcription

1 Mult-Constrant Mult-Processor Resource Allocaton Ar R. B. Behrouzan 1, Dp Goswa 1, Twan Basten 1,2, Marc Gelen 1, Had Alzadeh Ara 1 1 Endhoven Unversty of Technology, Endhoven, The Netherlands 2 TNO Ebedded Systes Innovaton, Endhoven, The Netherlands eal: {a.r.baghban.behrouzan, d.goswa, a.a.basten,.c.w.gelen and s.h.seyyed.alzadeh}@tue.nl Abstract Ths work proposes a Mult-Constrant Resource Allocaton (MuCoRA) ethod for applcatons fro ultple doans onto ult-processors. In partcular, we address a appng proble for ultple throughput-constraned streang applcatons and ultple latency-constraned feedback control applcatons onto a ult-processor platfor runnng under a Te-Dvson Multple-Access (TDMA) polcy. The an objectve of the proposed ethod s to reduce resource usage whle eetng constrants fro both these two doans (.e., throughput and latency constrants). We show by experents that the overall resource usage for ths appng proble can be reduced by dstrbutng the allocated resource (.e., TDMA slots) to the control applcatons over the TDMA wheel nstead of allocatng consecutve slots. Control Applcatons Streang Applcatons Sensor Mult-Processor platfor M NI P Tle Actuator Keywords Resource allocaton, ult-processors, throughput constrants, latency constrants, control applcatons, streang applcatons, synchronous dataflow. I. INTRODUCTION Many applcaton doans ncludng autootve and healthcare systes requre to run ultple applcatons sultaneously wth strngent requreents on perforance to ensure correct functonalty. Often, the applcatons pose dfferent doan-specfc constrants for the correct functonal behavor at the syste-level. Exaple ncludes nterventonal - Ray (R) systes where precson oton control applcatons for patent support execute together wth copute-ntensve age/vdeo processng applcatons. In the one hand, the precson of the oton controller s crtcal for patent s safety and on the other hand, the age qualty after the processng s crucal for the clncal purposes. Together, desgn of such systes requres to eet dfferent types of constrants. A coon practce s to consder the dfferent types of constrants n an solated fashon to reduce the desgn coplexty. Whle such desgn flow s sutable for ntegraton for large ndustral systes and reduces the desgn effort, t ncreases the overall cost of the syste due to poor resource effcency. Ths partcularly becoes relevant when t coes to ebedded pleentatons snce resource (e.g., coputaton and councaton) s often lted and shared n such settngs. In ths context, ultprocessng copute platfors are wdely used n alost all such ndustral doans [1]. Approprate treatent of dfferent doan-specfc constrants n the desgn process can potentally prove the overall desgn effcency. Here, an portant desgn queston s the appng of applcaton tasks fro ultple functonal doans wth dfferent types of constrants onto the shared resource (e.g., processors n the case of copute resource). In ths work, we consder the appng proble of cobnaton of feedback control applcatons wth Fg. 1. Setup under consderaton: latency-constraned feedback control applcatons sharng processors wth throughput-constraned streang applcatons. P: processor, M: eory and NI: network nterface requreent on Qualty of Control (QoC) and streang applcatons wth age/vdeo qualty requreent. Fg. 1 shows the setup under consderaton. Generally, the qualty requreents of streang applcatons can be translated nto the nu throughput constrants. Slarly, the QoC requreent of a feedback control applcaton can be translated nto the constrant on the axu saplng perod [2]. Further, dependng on the odel of the feedback control loops, the constrant on the saplng perod can be expressed as a axu latency or a deadlne allowed by the correspondng tasks. Thus, for the setup shown n Fg. 1, the appng proble deals wth a cobnaton of applcatons wth throughput and latency constrants. Syste-level functonalty requres to eet both constrants at the applcaton level. In ths process, not only perforance of ndvdual applcatons needs guarantees, but perforance of one applcaton should not drectly nfluence that of others. Achevng such syste-level requreents on predctablty or tng s partcularly challengng on shared platfors due to nterference between applcatons through resources. One well-known approach to acheve the above-entoned teporal predctablty on a shared resource s by budget schedulers that guarantee a fxed access te for every scheduled applcaton (task) n a gven te nterval [4]. Therefore, applcatons would have access to the resource n a te-solated fashon provdng hgher predctablty. Te- Dvson Multple-Access (TDMA) s a budget scheduler that defnes a perodc workng cycle for resources [5]. Each cycle s dvded nto a nuber of te slots. Usually, each te slot s assgned to one task (of an applcaton). Mnzaton of

2 t ' a Watng te t a Watng te Worst-case latency e t ' b e (a) Worst-case latency (b) Fg. 2. Exaple: each work cycle of a processor s dvded nto (a) two, and (b) four slots each assgned to ether steang applcatons or control applcatons. Streang applcatons are processed durng tes t a and t' a whle control applcatons are processed durng tes t b and t' b. resource usage then ples that the nu nuber of te slots s allocated to an applcaton that guarantees the requred perforance. In the above context, a resource allocaton strategy defnes a polcy for resource sharng aong applcatons wth tng predctablty and ndependence aong the. For worst-case perforance guarantees, a resource allocaton strategy often consders worst-case tng behavor of an applcaton to deterne the budget t needs to eet the perforance constrants (even n the worst case). Budget allocaton can ether be perfored by allocatng specfc slots to the applcatons [3] or t can be perfored by allocatng a percentage of slots to an applcaton wthout specfc slot-to-applcaton appng. Based on the tng constrants at the applcaton level (.e. throughput/latency constrants), dfferent resource allocaton strateges can be used [6],[7]. Key observaton and our approach: Tradtonally, resource allocaton for applcatons wth dfferent types of constrants on shared resources s perfored by te-solated resource-toapplcaton appng [7]. Fg. 2 (a) and (b) show two exaples of such allocaton n vew of the setup llustrated n Fg. 1. In Fg. 2(a), the t a nterval wthn a work cycle s allocated to the streang applcatons whle t b s allocated to the control applcatons. Whle such schedulng polcy provdes applcatonlevel ndependence, t can be notced that no sensng update for the control applcatons s possble durng t a and the saplng perod of the control loops ust be longer than ths duraton. That s, the nu saplng perod of the control (.e., latency-constraned) applcatons would be the su of t a and the executon te of the applcaton e (.e., ( t a e ) n Fg. 2(a)). Towards eetng a gven latency constrant, one needs to allocate enough resources n order to take nto account the above t ' a t b t ' b worst-case scenaro,.e., t a should be sall enough such that ( t a e ) eets the latency constrant. As opposed to Fg. 2 (a) n whch there s only one partton each for the streang and control applcatons, Fg. 2 (b) shows an allocaton wth dstrbuted resource budget to control applcatons. The resources allocated to the latency- and throughput-constraned applcatons are stll teporally solated lke the exaple n Fg. 2 (a). Wth the dstrbuted allocaton shown n Fg. 2 (b), the saplng perod for the control applcatons would be shorter than that of exaple n Fg. 2 (a). That s, ( t a e ) > ( t' a e ). Ths further ples a control applcaton wth shorter saplng perod can be scheduled wth such dstrbuted allocatons. Snce a shorter saplng perod can potentally be translated to a hgher QoC, ths observaton s partcularly relevant for the feedback control loops. Whle ths observaton suggests that the resource should be as dstrbuted as possble for the control applcatons leadng to a hgh nuber of te slots, each te slots needs to accoodate certan overhead for context swtchng fro one applcaton to the other. Such overhead restrcts the granularty of the te slots allowed by the syste snce a hgher nuber of slots n a work cycle poses a hgher overhead (leadng to a poor resource effcency). In ths work, we assue that the te slots are long enough to gnore such overhead. Moreover, these choce of paraeters of a work cycle s a desgn decson often taken at the early desgn phase and ths work deals wth a gven set of work cycle paraeters. In ths work, we further consder the worst-case scenaro for throughput-constrant applcatons. That s, the resource s allocated to eet the throughput constrant for any dstrbuton. Thus, our observaton for allocatng resource to control applcatons can be ntegrated wth any ethod that allocates budget (.e., does not perfor applcaton-to-slot appng) to streang applcatons wth throughput guarantees. For ths purpose, we rely on the state-of-the-art ethod reported n [6] and the exstng toolng support SDF 3 [11]. Our Contrbutons: Ths work proposes a resource allocaton flow for co-appng ultple streang applcatons (wth throughput constrants) and ultple control applcatons (wth saplng perod/latency constrants) on a ult-processng platfor (as llustrated n Fg. 1). Consderng both constrants n a sngle schedule and appng wth effcent resource usage are two an contrbutons of ths work. Processors run under a TDMA polcy wth a gven work cycle. The proposed ethod deternes both () task-to-processor appng () and task-tote slot appng wthn a processor such that both throughput and latency constrants are et. The pleentaton consdered the control applcatons can be odeled by a sngle task whle Synchronous Data Flow (SDF) graphs are used to odel the streang applcatons. We refer to our ethod as Mult- Constrant Resource Allocaton (MuCoRA). In Secton II, related work s dscussed. Secton III descrbes the setup under consderaton. The ult-processor archtecture s presented n Secton IV. Secton V llustrates the overall proble forulaton. The proposed resource allocaton strategy s descrbed n Secton VI. Secton VII presents the experental results and evaluaton. Secton VIII concludes.

3 II. RELATED WORK In vew of the setup, we consder n ths work (Fg. 1), the exstng lterature can be classfed nto two categores: () resource allocaton and appng ethods for the feedback control applcatons and general latency-constraned applcatons () resource allocaton/appng ethods to eet or optze throughput of streang applcatons. Whle our work addresses a cobnaton of () and () and lted/no exstng work address such proble, the lterature on both () and () are relevant. In the followng, we present the state-of-the-art n these drectons. Over the last decade, there has been consderable aount of work on control/archtecture co-desgn. The dea s to allocate/optze shared councaton/coputaton resource for pleentng one/ultple control loops. Ths s n lne wth drecton (). The proble s addressed consderng dfferent abstractons both for syste dynacs (.e., control pont of vew) and the archtecture odel. The ethod n [13] forulates a dynac progra to fnd the optal schedulng for ultple control tasks runnng under non-preeptve polcy and slarly, [14] presents a ethod to fnd the optal saplng perods (.e., latency constrants) n a slar setup as [13]. In [15], the resource requreents of control loops are translated nto a copute-bandwdth constrant (rather than latency constrant). In [16], [2], schedulng control applcatons for both councaton and coputaton resource s consdered. In these classes of work, several schedulng polces n councaton (e.g,, TDMA, Fxed-Prorty Non-Preeptve) and coputaton (e.g., deadlne onotonc, EDF, TDMA) are consdered to derve the stablty and perforance regon for a gven cobnaton of schedulng polces. The event-based controller proposed n [17] perfors saplng (.e., sensng, coputng and actuatng) only at the occurrence of events (e.g., crossng an error threshold) and saves councaton bandwdth by avodng unnecessary saplng. The appng and schedulng proble for a cobnaton of real-te and control applcatons s consdered for autootve archtectures n [2]. It should be noted that tradtonal real-te schedulng ethods [9] are not drectly applcable to schedule feedback control applcatons snce t needs to explctly consder the pact of jtter unlke deadlne-drven real-te applcatons. Along drecton (), a large body of work has been reported on resource allocaton strategy for appng of throughputconstraned applcatons onto ult-processors [6], [19], [23]. [6] proposes resource allocaton technques for task bndng and schedulng drectly on an SDF graph of the throughput constrant applcatons. In [23], the throughput constrant streang applcatons are odeled and apped to the ultprocessor by an acyclc odel n whch an applcaton task graph allows to run each tasks once. [19] encodes the proble of appng and schedulng of dataflow applcatons on a ultprocessor platfor n the for of logcal constrants and present t to a Satsfablty Modulo Theory (SMT) solver. Gven several cost constrants (e.g. eory usage, throughput, statc power consupton), the SMT solver uses a cobnaton of search technques and constrant propagaton to fnd a set of Pareto optal solutons. A key pont n a resource usage effcent appng ethod s how accurately the throughput s estated. The ore pessstc throughput estaton s, the ore resources are requred. The worst-case throughput calculaton s x( k 1) = Ax( k) Bu( k) uk ( ) = Kxk ( ) Fg. 3. Ipleentaton and tng dagra of feedback control loop. Sensng and actuatng tasks are perfored n dedcated hardware; the task uses the ult-processor platfor. coplcated. [21] proposes throughout analyss based on Hoogeneous SDF (HSDF) graph. Therefore, throughput analyss needs to transfor SDF graph of applcatons to HSDF graph, whch leads to a large graph sze. [20] propose a throughput analyss ethod whch works drectly on an SDF graph. Executng an SDF graph, ths ethod akes and analyses ts dynac state-space. [22] prove throughput calculaton for tghter throughput guarantees usng ax-plus algebra cobned wth worst-case resource avalablty curves. The appng and schedulng to answer both () and () drectly are not yet explored. However, soe work try to address solaton of applcatons n shared resources. Based on Worst- Case Executon Te (WCET) of ntra-applcaton tasks, runnng on ult-processors, [24] proposes a bus schedulng ethod to share Network on Chp (NoC) aong several processors. The approach n [25] uses vrtualzaton ethod for schedulng several applcaton n dfferent shared resources (e.g. processors, nterconnects and eory) aong applcatons. In ths ethod, usng preeptve te-dvson ultplexng (TDM) aong applcatons, each resources s dvded nto saller vrtual resources. Ths allows ndependent desgn, verfcaton and executon. III. SETUP UNDER CONSIDERATION The setup under consderaton s llustrated n Fg. 1. In the followng, we descrbe the odels of the control applcatons and streang applcatons used n our analyss. A. Control applcaton A feedback controller regulates behavor of a dynac syste called plant. The plant s consdered to be a lnear te nvarant (LTI) syste odeled by a set of dfference equatons of the followng for. x ( k 1) = Ax( k) Bu( k) (1) where A and B are the syste atrces, x (k) s the plant state and uk ( ) s the control nput. A feedback control loop perfors three sequental operatons: sensng, coputng, and actuatng. Fg. 3 shows pleentaton and tng dagra of these

4 Fg. 4. SDF graph of H.263 encoder operatons. The sensng operaton obtans syste state x (k) fro the plant perodcally wth perod h. The perod h s referred to as the saplng perod (see Fg. 3). Next, the copute operaton coputes the control nput u (k). The copute operaton s perfored by the Control Applcaton () task. The executon of the task ust be copleted before the actuaton operaton starts. The te needed for coputaton of the task on a processor s referred to as executon te of the task. The task passes the control nput u(k) to the actuaton operaton whch apples to the control nput to the plant. As shown n Fg. 3 sensng and actuatng operatons are perfored together by a task T p that runs on dedcated hardware n a te-trggered fashon wth perod h. The task runs on the ult-processor platfor. We defne the te nterval fro the pont that the saples arrve to coputaton unt tll the oent the task fnshes as latency, whch should be less than or equals to the saplng perod h to guarantee that all sapled data are processed for actuaton. Let = { 1, 2,...} be the set of all tasks correspondng to dfferent control applcatons. A control applcaton s characterzed by a tuple e, ) wth t 1 t 2 S 1,1 S 1,2 S1, 3 S1,4 S 1, 5 S1, 6 S 1, 1 S 2,5 SA 1 S 2,6 S 2,1 S 2,2 S2, 3 S 2,4 S 2, 5 SA 1 Fg. 5. Worst-case senaro for data councaton between tles. ( h e N (postve natural nubers) the executon te (n te unts, further dscussed n Secton IV) and h N the saplng perod (n te unts) of the task. B. Streang applcatons We use the SDF graph to odel the streang applcatons and for throughput analyss as suggested n a nuber of recent works [6][7]. We llustrate our proposed ethod consderng soe streang applcatons such as the H.263 encoder [8] (see Fg. 4). In an applcaton SDF graph (applcaton graph), nodes (actors) councate by sendng data (tokens) over edges (channels). Upon frng of an actor, nput tokens are reoved fro ts nput channels and after a certan aount of te (executon te) new tokens are produced on ts output channels; the nubers of consued and produced tokens are gven by the annotatons (rates) attached to the channel ends n the graph. The executon te of soe of the actors and ther nput/output rate ay vary (e.g. for varable-length encodng actor n the exaple shown on Fg. 4) fro once executon to another. By conservatve overestaton t s possble to have a fx nuber for the. Let SA = { SA 1, SA 2,... } be the set of all streang applcatons. Each applcaton SA SA ( N) has a throughput constrant of λ actor frngs per te unt, for soe dedcated actor. IV. ARCHITECTURE MODEL In ths work, a tle-based teplate [6] s used as the ultprocessor platfor. Fg. 1 shows an exaple archtecture platfor wth four connected tles that process ultple control and streang applcatons. Each tle contans a processor (P), a local eory (M), and a network nterface (NI) that connects the eory to the local processor, and nterconnectons between tles. Let T = { t 1, t 2,...} denotes the set of tles under consderaton. All tles run a TDMA schedulng polcy. Under the TDMA polcy, the resource access schedule repeats cyclcally accordng to a cycle called a te wheel. The te wheel conssts of ultple equally szed parts, called te slots. It should be noted that the context swtchng overhead between applcatons s neglgble copared to the sze of each te slot (as explaned n the ntroducton). Many archtectures [3] allow such choce of the TDMA confguraton. Each te slot can be allocated to a dfferent applcaton durng whch the applcaton can run wthout any nterference fro other applcatons. Each tle t T has a te wheel consstng of w equally szed te slots. Wthout loss of generalty, we consder one te slot to be unt te. For each tle t T, we defne S as the set of all te slots as S = { S, 1, S,2,.. S, }. w We consder the councaton between tles to be asynchronous. The presented analyss on tng behavor of data councated between tles s based on the worst-case tng scenaro. In other words, any data travellng fro one tle to another, s assued to arrve at the destnaton tle at the oent such that t wll have to wat the ost untl t reaches the next assgned te slot. Fg. 5 llustrates the worst-case tng scenaro for data that s councated between two tles t 1 and t 2 wth w 1 = w2 = 6. As shown n Fg. 5, S1, 2 n t 1 and S 2,6 n t 2 are assgned to applcaton SA 1. Therefore, the worstcase scenaro for data sent fro t 1 to t 2 s to arrve just after S2,6 fnshes. In ths scenaro, the data has to wat for w 2 1 = 5 te unts before ts processng starts. V. PROBLEM STATEMENT We can now foralze the precse proble descrpton for ths paper. For a set of nputs as follows: I1. a set of streang applcatons SA wth SA SA odeled by an SDF graph, I2. a set of control applcatons wth characterzed by tuples ( e, h ),

5 I3. a set of tles T, each tle t T runnng a TDMA polcy wth a te wheel sze of w te slots, we address the followng resource allocaton proble: P1. bndng actors (for SA) and tasks (for ) to the tles and P2. assgnng te slots (.e., S, j ) n a tle to applcatons (.e., SA and ) bound to that partcular tle such that the followng constrants are satsfed: C1. throughput constrants λ of the streang applcatons SA SA, C2. latency constrants h of control applcatons. Gven I1-I3, a soluton to P1 and P2 whch satsfes both C1 and C2 for all the applcatons (eetng both perforance requreents) s a vald soluton to the above resource allocaton proble. VI. MUCORA: RESOURCE ALLOTION FLOW Resource allocaton s done n two stages (see Fg. 6): () bndng the applcatons to tles (.e., P1) () assgnng the te slots to the applcatons (.e., P2). In the followng, we descrbe the two stages for the control and the streang applcatons. A. Control applcaton appng Gven I2 and I3, we address P1 and P2 for control applcatons n ths subsecton. Resource allocaton for the control applcatons conssts of two stages. In the frst stage, each control applcaton s bound to only one tle (.e. P1). Frst, ths avods latency overhead due to asynchronous nteracton aong the tles. Second, ths avods connecton delay caused by the nterconnects. Further, the control tasks are coputatonally lght akng the easer to run on a sngle tle. The bndng soluton of control applcatons ust guarantee that the latency constrant C2 s et. We use a load balancng polcy for task-to-tle bndng slar to [6]. Resource usage for the control applcatons corresponds to the nuber of te slots that s requred to eet C2. We defne the load functon of control applcaton as l e =. (1) h It deternes the nu fracton of a te wheel that s requred for a control applcaton to eet C2. It s noteworthy that a total load of less than 1 s a necessary condton for schedulablty on a sngle tle,.e. [9] l < 1. To balance the load of control applcatons aong tles, we sort the applcatons n decreasng order of ther loads. To balance the load aong tles we bnd applcatons n that order Fg. 6. Resource allocaton flow for appng several control and streang applcatons on a ult-processor platfor. to the tles. For exaple, assue bndng of four control applcatons wth load functon values of [ l, l, l, l ] = [0.6, 0.4, 0.3, 0.1] The best case for bndng these applcatons to two tles accordng to the resource load balancng polcy s to bnd 1 and 4 to one tle and 2 and 3 to the other tle. Ths addresses P1 for the control applcatons. In the followng, we descrbe how te slots are assgned to the control applcatons towards addressng P2. Defnton 1. For any te slot S, j (.e. slot nuber j n tle nuber ), we defne an occupaton varable, j, that takes value 1 when slot S, j s assgned to applcaton and takes value 0 f not. For each applcaton apped on a tle we ntally allocate all avalable te slots,.e.,, j, = 1 for all j whch are not allocated to other applcatons and next, we attept to unassgn the te slots that are unnecessary. That s, we check f an assgned slot can be unassgned wthout volatng constrant C2. Proposton 1. Assgned te slot S, j (.e. slot nuber j n tle nuber ) to a control applcaton can be unassgned wthout volatng C2 f the followng nequalty s satsfed for all j n < j h 1, < n, k, e k= n h 1 1, where e and h are executon te and saplng perod of the applcaton respectvely. (2) Proof. For a schedule that already satsfes latency constrant C2 of an applcaton, te slot S, whch s assgned to j

6 S,10 S,1 S,10 S,1 S,10 S,1 S,10 S,1 S,9 S,2 S,9 S,2 S,9 S,2 S,9 S,2 S,8 S,3 S,8 S,3 S,8 S,3 S,8 S,3 S,7 S,4 S,7 S,4 S,7 S,4 S,7 S,4 S,6 S, 5 S,6 S, 5 S,6 S, 5 S,6 S, 5,10,,2,,1,,3, = 3,1,,3,,2,,4, = 3,2,,4,,3,,5, = 3,3,,5,,4,,6, = 3 Fg. 7. All cobnatons of 4 consecutve te slots ncludng S, 3 are checked to fnd f, 3 w =10 S can be unassgned of applcaton, wth ( e, h )=(2,4), S,10 S,1 S,10 S,1 S,10 S,1 S,10 S,1 S,9 S,2 S,9 S,2 S,9 S,2 S,9 S,2 S,8 S,3 S,8 S,3 S,8 S,3 S,8 S,3 S,7 S,4 S,7 S,4 S,7 S,4 S,7 S,4 S,6 S, 5 S,6 S,5 S,6 S, 5 S,6 S,5 (a) (b) (c) (d) Fg. 8. All cobnaton of 4 consecutve te slots ncludng S, 1 are checked to fnd f S, 1 can be unassgned of applcaton. applcaton, can be unassgned f there s no cobnaton of h consecutve slots, ncludng S, j, for whch the su of occupaton varables s less than e 1. Ths coes fro the dea that a TDMA schedule satsfes latency constrant C2 of an applcaton only f e te slots are allocated to n every h consecutve te slots. Equaton (2) coputes the total executon te n every h slots. Ths copletes the proof. Fg. 7 llustrates the above proposton by checkng f slot S,1 of tle t that s already assgned to control applcaton wth ( e, h ) = (2,4) can be unassgned. In ths exaple, slots ( S, 1, S,5) are already assgned to another applcatons and cannot be assgned to. So, 0 and 0., 1, =, 5, = Next, all cobnatons of four consecutve te slots ncludng S, 1 are checked to ensure that there s always ore than one te slot assgned to the applcaton (see Fg. 7). If so, S,1 can be unassgned (.e., 1, = 0 ) whle there s at least one te slot allocated to whch guarantees satsfacton of the latency constrant C2. The nu e slots n each h consecutve slots should be allocated to applcaton to eet C2. Thus, the nu load of an control applcaton n each te wheel of tle t s obtaned by e l = w. (3) h As llustrated n Fg. 2, a dstrbuted allocaton of resource for control applcatons proves the resource effcency requrng less te slots. Therefore, we a to nze the axu dstance between any two consecutve slots that are assgned to a control applcaton. We assgn the slots n such a way that the axu nuber of slots between every two assgned te slots s h. (4) e In the above process, soe slots ght already be occuped by other applcatons and t s not possble to assgn those slots to the control applcaton. In those cases, ore slots are needed to guarantee the perforance,.e., eet the latency constrant C2. To axze the dstrbuton n resource allocaton, the order of slots that are consdered for unassgnent s chosen perodcally wth a perod as Eq. (4). Fg. 8 shows two orders of selectng te slots n exaple n Fg. 7 for unassgnent. In Fg 8 (a), consecutve avalable slots are consdered for unassgnent. Fg. 8 (b) shows the resultng allocaton. In Fg 8 (c), the te slots are chosen wth a perod of 2 obtaned by Eq. (4). The order of selectng the slots would be S, S, S, S, S,... {,1,3,5,7,9 }

7 TABLE I. CONTROL APPLITIONS: UNIT IS TDM TIME SLOTS Fg. 9. SDF graph of H.263 decoder. {, 1, S,5 } all other slots, we fnd that { S S } S are not allowed to be assgned to. By checkng S, 3,,7,,9 can be unassgned. Fg. 8 (d) shows the resultng allocaton. Although both schedules (Fg. 8 (b) and Fg. 8 (d)) satsfy the latency constrants of applcaton, the second schedule n Fg. 8 (d) requres less te slots than the one shown n Fg. 8 (b). Maxu dstance between two consecutve assgned te slots n the second soluton s 2 as per Eq. (4). Thus, the results are n lne wth the observaton descrbed n ntroducton. B. Mappng of streang applcatons We use the exstng ethod of [6] as pleented n the SDF 3 tool [11] to allocate resources to streang applcatons. Bndng actors to tles. Ths step bnds every actor of a streang applcaton SDF graph to a tle. The actors that have large pact on the throughput are bound frst. The pact of an actor s too expensve to copute exactly. Therefore t s estated for each cycle n the SDF graph n whch s partcpates, by the total coputaton te of the actor dvded by the ppelnng parallels n that cycle. The ppelnng s, n turn, estated by the total nuber of ntal tokens n the cycle, noralzed by the actor frng rates on the correspondng edge on whch they resde. Snce an actor ay be part of ultple cycles n the SDF graph, the ost crtcal cycle s consdered an estate for the pact of the actor. After sortng the actors accordng to ther pact on throughput they are bound to the tles. Bndng tres to acheve load balancng, where the load of a tle s estated as the total executon te of frngs of actors bound to the tle dvded by the total executon te of all actor frngs. The an strategy s a greedy algorth that bnds an actor to the least loaded tle. The SDF 3 tool balances the load of tles not only n ters of coputaton, but also n ters of eory usage and bandwdth requreents, both of whch we do not consder n ths paper. SDF 3 allows us however to set weghtng factors for these aspects, whch then enables us to perfor load balancng n ters of coputaton only. Constructng frng order. After bndng the actors of an applcaton to the tles, the statc order of ther frng s obtaned usng a lst-scheduler. Budget allocaton. A bnary search algorth s used n cobnaton wth a throughput analyss algorth to fnd the nu nuber of te slots requred on each tle to satsfy the requred throughput rate. The throughput analyss algorth that s used s conservatvely pessstc, both n vew of whch of the te slots n the te wheel wll be allocated, and n ters of the salgnent of slots on dfferent tles due to asynchronous executon of ther TDMA wheels. Thus, proble P1 s solved for the streang applcatons and proble P2 s Executon te trvally satsfed by any slot allocaton we ay choose. After obtanng the budget (.e. nuber of te slots) that s requred for streang applcaton by SDF 3, we allocate the te slots that are not allocated to control applcaton. The rest of te slots that are not allocated to none of the applcatons rean epty. They can be used to ap ore applcatons. VII. EPERIMENTAL RESULTS Syste descrpton: We consder four control loops and two streang applcatons for evaluatng our MuCoRA desgn flow. The ult-processor platfor has two tles both runnng under TDMA polcy wth a te wheel sze of 20 slots. The streang applcatons are an H.263 vdeo encoder ( SA 1 ) [8] and an H.263 decoder ( SA 2 ) [10]. The SDF graphs of the streang applcatons are shown n Fg. 4 and Fg. 9 respectvely. The control loops have executon te and saplng perod as shown n Table I. Fro the seven control loops, we choose 35 subsets of four control loops for our experents. Ths shows how senstve our results are to the paraeters of the control applcatons. We choose the executon te and the saplng perod of control applcatons and te wheel sze to be of the sae order of agntude. The perods of the control applcatons are fro 6 to 15 te slots whle the te wheel s 20 slots. The pact of sgnfcantly longer or shorter saplng perods than the te wheel sze s not explored n ths work. Intutvely, the pact of the relatve length of saplng perods affects the scalablty whle ths work focuses on establshng the potental beneft of the proposed ethod. Allocaton wth MuCoRA: We frst apply MuCoRA to solve the appng proble. Table II shows one result. 1 and 2 are apped to Tle 1 whle 3 and 4 are apped to Tle 2. Fg. 10 (a) llustrates the resource allocaton n Tle 1. Te slots { S 1,1, S1,8, S1,14 } are allocated to 1 (shown n Fg. 10(a) n blue), { S 1,2, S1,7, S1,12, S1,17} are allocated to 2 (shown n Fg. 10(a) n red), { S 1,3, S1,5, S1,9, S1,13} are allocated to SA 1, { S 1,18,S1,19} are allocated to SA 2 and S, S, S, S, S, S S are epty. { } 1,4 1,6 1,10 1, ,16, 1,20 Saplng perod Evaluaton: For evaluatng the proposed ethod, we consder an allocaton where only two parttons are consdered one for the feedback control applcatons and one for the streang applcatons (slar to Fg. 2(a)) [5]. We refer to ths ethod as parttonng ethod. In ths case, snce ultple control loops are sharng the sae partton (e.g., t b n Fg. 2(a)), we need an arbtraton polcy to schedule the applcatons n the control

8 TABLE II. RESOURCE ALLOTION FOR MUCORA AND PARTITIONING METHOD. Tle 1 2 Mappng ethod MuCoRA Parttonng ethod MuCoRA Parttonng ethod H.263 Enc.(SA1) H.263 Dec.(SA2) SA 1 and 2 occupaton Control applcaton occupaton Epty porton of tle 30% 35% 35% 30% 60% 10% 45% 15% 40% 45% 50% 5% partton. For ths purpose, we adapt the EDF (Earlest Deadlne Frst) polcy of [18]. For the appng of streang applcatons, we use SDF 3 descrbed n Secton VI.B. SDF 3 assgns a budget and does not consder the exact slot allocaton. Therefore, the resource budget for the streang applcatons s dentcal to MuCoRA. The sze of the partton for streang applcatons equals the coputed budget. The partton sze for control applcatons s derved fro the worst-case arrval of control saples relatve to the partton, whch s just after the partton for control applcatons. The sze of control applcaton partton s therefore obtaned such that the saples are executed before deadlne. Let w denotes the sze of te wheel, t s and t c denote the sze of the partton of streang and control applcaton respectvely (see Fg 10.). Then, for ths exaple, the epty porton of the te wheel s obtaned as follows: t = n{( l e e t ),( l e t )}, e s 2 2 s where, l 1 and l 2 are deadlne of 1 and 2 and e 1 and e2 are executon te of 1 and 2. Next, t c s obtaned by tc = w ts te. For the exaple, as MuCoRA, the parttonng ethod aps 1 and 2 to Tle 1 and 3 and 4 to Tle 2. Fg. 10 llustrates the workng cycle n Tle 1. As shown n Table II, the partton for streang applcatons takes 30% of the te wheel) and the one for control applcatons 60%. The resource budget consders the worst-case arrval of saples, at the end of the partton assgned to control applcatons; ths s shown by arrows n Fg. 10(b). All saples then have to wat untl the end of the partton allocated to the streang applcatons. Coparson and dscusson: We copared results of both ethods for all possble 35 cobnatons of four out of seven control loops shown n Table I. For both ethods, we easure the resource usage by the percentage of assgned te slots of the te wheel after appng both categores of applcatons. The resource effcency s hgher f the percentage of the unassgned te slots s hgher. Table II shows the epty and allocated portons of two tles. For these partcular exaples, MuCoRA coes up wth an allocaton wth 18% ore epty space on average over all cobnatons. Table II provdes one exaple of the 35 experents. The experents show that MuCoRA s robust to the changes n control paraeters, wth a nu savng of 15% across all experents. VIII. CONCLUSIONS In ths work, we addressed a appng proble of ultple control and streang applcatons onto a ult-processor. Whle state-of-the-art resource allocaton ethods ether consder one type of constrant or translate all constrants to one category, our 1 2 S 1,1 S 1,2 S1, 3 S 1, e2 e1 tc Fg. 10. Mult-constrant applcaton appng on Tle 1 wth two ethods, (a) MuCoRA and (b) parttonng ethod. ethod treats the constrants fro dfferent doans separately. We have shown by experents that dstrbutng the allocated resources reduces the resource requreent by control applcatons and that ths proves overall resource effcency. As future work, we plan to explore the pact of the relatve length between saplng perods (.e., latency constrants) of the control applcatons. ACKNOWLEDGMENT Ths research was supported by the ARTEMIS jont undertakng under grant agreeent no (ALMARVI). REFERENCES [1] K. Zhang, Y. Yao, O. Labann, Z. Lu,. Wu, A New Unversal- Envronent Adaptve MultProcessor Scheduler for Autonoous Cyber- Physcal Syste, Proceedngs Internatonal Conference on Inforaton Systes (ICIS), [2] D. Goswa, M. Lukasewycz, R. Schneder and S. Chakraborty, Tetrggered pleentatons of xed-crtcalty autootve software, Proceedngs Desgn, Autoaton and Test n Europe (DATE), [3] A. B. Nejad, A. Molnos, K. Goossens, A Software-Based Technque Enablng Coposable Herarchcal Preeptve Schedulng for Te- Trggered Applcatons, Proceedngs Ebedded and Real-Te Coputng Systes and Applcatons (RTCSA), [4] G. C. Buttazzo, Hard Real-Te Coputng Syste, Sprnger, Vrgna, [5] B. Akesson, A. Mnaeva, P. Sucha, A. Nelson, Z. Hanzalek, An Effcent Confguraton Methodology for Te-Dvson Multplexed Sngle t s t e

9 Resources, Proceedngs Real-Te and Ebedded Technology and Applcaton Syposu (RTAS), [6] S. Stujk, T. Basten, M.C.W. Gelen and H. Corporaal, Multprocessor Resource Allocaton for Throughput-Constraned Synchronous Dataflow Graphs Proceedngs Desgn Autoaton Conference (DAC), [7] S. Srra, S. Bhattacharyya, Ebedded Multprocessors: Schedulng and Synchronzaton, Marcel Dekker, [8] F. Syou, B. Akesson, S. Stujk, K. Goossens, and H. Corporaal, Resource-Effcent Real-Te Schedulng Usng Credt-Controlled Statc-Prorty Arbtraton Proceedngs Ebedded and Real-Te Coputng Systes and Applcatons (RTCSA), [9] C. Lu and J. Layland, Schedulng Algorths for Multprograng n Hard Real-Te Envronents, Journal of the Assocaton for Coputng Machnery, 20(1), 40 61, [10] K. Srnvasan, K. Chatha, and G. Konjevod, Lnear-Prograng Based Technques for Synthess of Network-on-Chp Archtectures, IEEE Transactons on Very Large Scale Int. Sys, 14(4), , [11] S. Stujk, M. Gelen, T. Basten, SDF3: SDF For Free, Proceedngs Applcaton of Concurrency to Syste Desgn (ACSD), [12] P. Mart, J. M. Fuertes, G. Fohler, K. Raarta, Iprovng Qualtyof-Control Usng Flexble Tng Constrants: Metrc and Schedulng Issues, Proceedngs Real-Te Systes Syposu (RTSS), [13] A. Cervn, P. Alrksson, Optal On-Lne Schedulng of Multple Control Tasks: A Case Study, Proceedng of Eurocro Conference on Real-Te Systes (ECRTS), [14] E. Bn, A. Cervn, Delay-Aware Perod Assgnent n Control Systes, Proceedng of Real-Te Systes Syposu (RTSS), [15] A. Anfar, E. Bn, P. Eles, Z. Peng, Bandwdth-effcent controllerserver co-desgn wth stablty guarantees, Proceedngs Desgn, Autoaton and Test n Europe (DATE), [16] P. Naghshtabrz, J. P. Hespanha, Analyss of dstrbuted control systes wth shared councaton and coputaton resource, Proceedngs Aercan Control Conferences (ACC), [17]. Wang and M. Leon, Event-trggerng n dstrbuted networked control systes, IEEE Transactons on Autoatc Control, 56(3): , [18] A. K. Mok,. A. Feng, D. Chen, Resource Partton for Real-Te Systes, Proceedngs Real-Te and Ebedded Technology and Applcaton Syposu (RTAS), [19] P. Tendulkar, Mappng and Schedulng on Mult-Core Processors Usng SMT Solver, PhD thess, L Unversté de Grenoble, [20] A.H. Ghaaran, M. Gelen, S. Stujk, T. Basten, A. Moonen, M. Bekooj, B. Theelen, M. Mousav, Throughput Analyss of Synchronous Data Flow Graphs, Proceedngs Applcaton of Concurrency to Syste Desgn (ACSD), [21] A. Dasdan, Experental analyss of the fastest optu cycle rato and ean algorths, IEEE Transactons on Desgn Autoaton of Electronc Systes, 9(4): , [22] F. Syou, M. Gelen, H. Corporaal, Sybolc Analyss of Dataflow Applcatons Mapped onto Shared Heterogeneous Resources, Proceedngs Desgn Autoaton Conference (DAC), [23] J. Hu, R. Marculescu, Energy- and Perforance-aware appng for regular NoC Archtecture, IEEE Transactons on Coputer-Aded Desgn of Int. Crcuts and Sys. 24(4), , [24] A. Andre, P. Eles, Z. Peng, J. Rosen, Predctable Ipleentaton of Real-Te Applcatons on Multprocessor Systes-on-Chp, Proceedngs VLSI Desgn (VLSID), [25] K. Goossens, A. Azevedo, K. Chandrasekar et al., Vrtual executon platfors for xed-te-crtcalty systes: the CopSOC archtecture and desgn flow, ACM SIGBED, 10(3), 23-34, 2013.