A high-level model of embedded flash energy consumption
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1 A high-level model of embedded flash energy consumption To appear in CASES, ESWEEK 2014 James Pallister, PhD Student Kerstin Eder, Primary PhD Supervisor Simon Hollis, PhD Supervisor Jeremy Bennett, Embecosm
2 Outline Embedded flash memory Effect on energy Modelling Modelling instruction streams Optimisation
3 Outline Hardware Embedded flash memory Effect on energy Modelling Modelling instruction streams Software Optimisation
4 What is embedded flash memory? Not what we typically think of Similar to flash drives/ssds Flash memory that is on the same die as the processor
5 Deeply embedded SoCs
6 Deeply embedded SoCs Small, cache-less, SoCs
7 Deeply embedded SoCs Small, cache-less, SoCs Simple processors
8 Deeply embedded SoCs Small, cache-less, SoCs Simple processors Typically flash and RAM
9 Deeply embedded SoCs Small, cache-less, SoCs Simple processors Typically flash and RAM Single cycle access to both
10 Deeply embedded SoCs Small, cache-less, SoCs Simple processors Typically flash and RAM Single cycle access to both Code executed directly out of flash
11 Deeply embedded SoCs Small, cache-less, SoCs Simple processors Typically flash and RAM Single cycle access to both Code executed directly out of flash Low energy requirements
12 Deeply embedded SoCs Small, cache-less, SoCs Simple processors Typically flash and RAM Single cycle access to both Code executed directly out of flash Low energy requirements Position of code in flash affects the energy?
13 Flash memory
14 Flash memory Precharge bit-lines
15 Flash memory Address is fed into the decoder
16 Flash memory Decode the address, select the block
17 Flash memory Assert the control gate on the desired word-line
18 Flash memory Connect the flash cell to the bit-line with the select gates
19 Flash memory The precharged bit-lines are pulled up or down, depending on the charge in the flash cell
20 Flash memory Sense amplifiers Detect the change and buffer the output onto the data bus
21 Expected energy effect Pages, blocks, word-lines, bit-lines Changing each of these has an energy cost
22 Expected energy effect Bit-lines Decoder Decoder Word-lines
23 Expected energy effect Bit-lines Word-lines Decoder Decoder n-bit length instructions loop: nop nop subs r0, #1 bne loop
24 Expected energy effect Bit-lines Word-lines Decoder n-bit length instructions loop: nop nop subs r0, #1 Decoder bne loop
25 Expected energy effect Bit-lines Word-lines Decoder n-bit length instructions loop: nop nop subs r0, #1 Decoder bne loop Straddling two blocks.
26 Expected energy effect Bit-lines Word-lines Decoder n-bit length instructions loop: nop nop subs r0, #1 Decoder bne loop Straddling two blocks. Each iteration must repeatedly power up one, then the other
27 Expected energy effect Bit-lines Word-lines Decoder n-bit length instructions loop: nop nop subs r0, #1 Decoder bne loop Straddling two blocks. Each iteration must repeatedly power up one, then the other Higher energy cost when an instruction jumps from one 'region' to another.
28 Expected energy effect Bit-lines Word-lines Decoder Decoder n-bit length instructions Straddling two blocks. loop: nop nop subs r0, #1 bne loop Each iteration must repeatedly power up one, then the other Higher energy cost when an instruction jumps from one 'region' to another.
29 Actual results Bottom line (blue) 8-byte loop Top line (green) 10-byte loop
30 Actual results Bottom line (blue) 8-byte loop Top line (green) 10-byte loop
31 Actual results Bottom line (blue) 8-byte loop Top line (green) 10-byte loop
32 Actual results Bottom line (blue) 8-byte loop Top line (green) 10-byte loop
33 Modelling Each consecutive memory access has an address dependent energy consumption. E.g
34 Modelling Each consecutive memory access has an address dependent energy consumption. E.g
35 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
36 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
37 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
38 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
39 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
40 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
41 Modelling Each consecutive memory access has an address dependent energy consumption. E.g
42 Modelling Each consecutive memory access has an address dependent energy consumption. E.g
43 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
44 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
45 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
46 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
47 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
48 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
49 Modelling Each consecutive memory access has an address dependent energy consumption. E.g byte
50 Modelling - formula
51 Modelling - formula
52 Modelling - formula
53 Modelling - formula
54 Modelling - formula
55 Modelling multiple instructions Addr Code loop: add ldr cmp bne r1, #1 r0, [r3, #4] r1, r2 loop Each instruction is 2 byte Each memory access is two bytes
56 Modelling multiple instructions Addr Code loop: add ldr cmp bne r1, #1 r0, [r3, #4] r1, r2 loop 0 2
57 Modelling multiple instructions Addr ? Code loop: add ldr cmp bne r1, #1 r0, [r3, #4] r1, r2 loop.word 0x ?
58 Modelling multiple instructions Addr ? Code loop: add ldr cmp bne r1, #1 r0, [r3, #4] r1, r2 loop.word 0x ?? 4
59 Modelling multiple instructions Addr Code loop: add ldr cmp bne r1, #1 r0, [r3, #4] r1, r2 loop 0 2 2?? 4 4 6
60 Modelling multiple instructions Addr Code loop: add r1, #1 ldr r0, [r3, #4] cmp r1, r2 bne loop prefetched 0 2 2??
61 Modelling multiple instructions Addr Code loop: add r1, #1 ldr r0, [r3, #4] cmp r1, r2 bne loop prefetched 0 2 2??
62 Modelling multiple instructions Addr Code loop: add r1, #1 ldr r0, [r3, #4] cmp r1, r2 bne loop prefetched 0 2 2??
63 Approximating Ignore the data accesses Mostly to RAM Infrequently to flash (if so, usually one time loads) Almost allows us to statically analyse code for flash energy consumption Conditional branches still unknown
64 Parameters
65 Cross validation STM32F0
66 A potential optimisation For code which is executed frequently, ensure it crosses as few costly boundaries as possible. Use the model to make these decisions.
67 A potential optimisation For code which is executed frequently, ensure it crosses as few costly boundaries as possible. Use the model to make these decisions.
68 A potential optimisation For code which is executed frequently, ensure it crosses as few costly boundaries as possible. Use the model to make these decisions.
69 Conclusion 5-15% energy reduction Flexible model Validated on 5 SoCs Average error: 11% Compiler optimisation to be implemented Analysis indicates 30-40% of all loops can be better aligned 4% increase in executable size
70 Thanks! Preprint: Final version to appear in CASES, ESWEEK 2014.
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